CN112578272A - JTAG control device and method for realizing JTAG control - Google Patents

Abstract

The JTAG control device simply supports a plurality of sub JTAG TAP test control circuits to be connected with a main TAP control circuit, and effectively realizes JTAG test. The JTAG control device with the master-slave structure has good expansibility, and can mount an infinite number of slave TAP control units theoretically.

Description

JTAG control device and method for realizing JTAG control

Technical Field

The present application relates to, but not limited to, electronic control technologies, and in particular, to a JTAG control apparatus and a method for implementing JTAG control.

Background

Joint Test Action Group (JTAG) provides a standard Test access port, including: a Test Data Input (TDI) port, a Test Data Output (TDO) port, a Test Mode Select (TMS) port, a Test Clock (TCK) port, a Test Reset (TRST) port. JTAG can realize boundary scan test and state control and observation of the internal circuit of the chip. JTAG is the most commonly used Test control technique in Design For Test (DFT). The JTAG protocol evolved from the initial 1149.1 stepwise optimization to the later IEEE1500, IEEE1687(IJTAG, Internal JTAG); the IEEE1500 protocol defines a standard Wrapper TAP interface and a communication mechanism between a Test Access Port (TAP) and a module; the IEEE1687 protocol defines an Internal JTAG (IJTAG, Internal JTAG) interface and a communication mechanism between a chip TAP and a module, or between modules.

At present, the chip scale is getting bigger and bigger, the functional requirements are getting bigger and bigger, in order to simplify the design complexity, the design is carried out by adopting a modularized and Intellectual Property (IP) mode, the sub-module and the IP may integrate the JTAG TAP controller when carrying out DFT test design, a plurality of JTAG TAP controllers exist in the chip, no matter the traditional 1149.1 protocol, or the later evolved IEEE1500 and IEEE1687 JTAG protocols, can not control the existing JTAG TAP in the JTAG TAP subsystem at the top layer.

Disclosure of Invention

The application provides a JTAG control device and a method for realizing JTAG control, which can simply and effectively realize JTAG test.

The application provides a joint test action group JTAG control device, which comprises: a main test access port TAP control unit and at least one slave TAP control unit;

wherein the main TAP control unit at least comprises: the system comprises a TAP control module, an enabling operation control module and a selection module; wherein the content of the first and second substances,

the TAP control module is used for connecting a chip JTAG interface; determining the number of bits of the enable signal and the output selection signal according to the number of the slave TAP control units;

the enabling operation control module is used for configuring an enabling signal and an output selection signal according to the bit number of the enabling signal and the output selection signal;

the selection module is used for realizing the output selection of the multi-path input signals according to the enabling signals and the output selection signals;

wherein the slave TAP control unit includes at least: the device comprises a conversion module and a test control module; wherein the content of the first and second substances,

the conversion module is used for realizing interface conversion of the JTAG TAP test control circuit of the main TAP control unit and the slave TAP control unit;

and the test control module is used for performing DFT test control on the generated JTAG test control vector after the slave TAP control unit of the test control module is enabled, and mapping the JTAG test control vector to the selection module through the conversion module.

In one illustrative example, the enable operation control module is a data register set DR-Chain;

the enabling of the configuration of the enable signal in the operation control module includes: and writing a numerical value into the DR-Chain, and setting the enabling signal of the slave TAP control unit needing to acquire JTAG interface communication.

In one illustrative example, the main TAP control unit further comprises: and the data operation control module is used for enabling the operation control module to carry out the configuration of the enabling signal and the output selection signal under the control of the main TAP control module.

In an exemplary embodiment, the selection module is specifically configured to: and realizing the output selection of the multi-path input signals according to the enable control signal, the enable signal and the output selection signal.

In an exemplary embodiment, the data operation control module is specifically configured to: the TAP control module is connected with the input end of; and determining whether to enable the operation control module according to the instruction encoding operation signal.

In one illustrative example, the data operation control module comprises: the device comprises an instruction register group, an instruction comparison storage circuit, a first instruction comparison circuit, a second instruction comparison circuit and a decision circuit; wherein the content of the first and second substances,

the instruction register group is used for being connected with the TAP control module, and the connecting signal comprises an instruction coding operation signal of the TAP control module; storing the loaded IR instructions;

the first instruction comparison circuit is preset with an expected instruction code, compares the expected instruction code with the preset expected instruction code after the first IR instruction is loaded, and outputs a first comparison result signal to the instruction comparison storage circuit;

the instruction comparison storage circuit is controlled by the instruction register group, and a first comparison result signal of a previous IR instruction is latched into the instruction comparison storage circuit before a next IR instruction is loaded;

the second instruction comparison circuit is preset with an expected instruction code, compares the second IR instruction code with the preset expected instruction code after the second IR instruction is loaded, and outputs a comparison result signal to the instruction comparison storage circuit;

and the decision circuit is used for receiving the first comparison result signal from the instruction comparison storage circuit and the second comparison result signal from the second instruction comparison circuit, and determining to enable the operation control module and outputting an enable control signal when the first comparison result signal and the second comparison result signal are enabled.

In one illustrative example, the first IR instruction and the second IR instruction differ in bit width, and the loading of the first IR instruction and the second IR instruction requires sequential loading in a preset order.

The application also provides a method for realizing JTAG control, which comprises the following steps:

continuously loading different IR instructions according to a preset sequence;

loading the IR instruction each time, comparing the loaded IR instruction with a preset expected instruction code, and obtaining an effective comparison result when the loaded IR instruction is completely consistent with the preset expected instruction code;

and when the comparison result of each IR instruction loaded continuously is effective, loading the data register code to enable the slave TAP control unit which needs to communicate with the master TAP control unit through the JTAG interface.

In one illustrative example, the IR instructions include one or more.

In one illustrative example, the loaded IR instruction is fully consistent with a preset expected instruction encoding, comprising: the IR instructions loaded are consistent with the length of the preset expected instruction encoding.

The JTAG control device simply supports a plurality of sub JTAG TAP test control circuits to be connected with the main TAP control circuit, and effectively realizes JTAG test. The JTAG control device with the master-slave structure has good expansibility, and can mount an infinite number of slave TAP control units theoretically.

In one illustrative example, the main TAP control unit must be continuously loaded with a plurality of specific instruction codes of different lengths before triggering a data operation of the main TAP control unit, which effectively avoids instruction conflicts between the main TAP control unit and the slave TAP control unit.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter.

FIG. 1 is a schematic diagram of the JTAG control device of the present application;

FIG. 2 is a schematic diagram of a component structure of an embodiment of a data manipulation control module according to the present application;

FIG. 3 is a schematic diagram of a component structure of an embodiment of a conversion module of the present application;

FIG. 4 is a diagram of an exemplary implementation of a conversion module of the present application;

FIG. 5 is a flowchart illustrating a method for implementing JTAG control according to the present application.

Detailed Description

In one exemplary configuration of the present application, a computing device includes one or more processors (CPUs), input/output interfaces, a network interface, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include non-transitory computer readable media (transient media), such as modulated data signals and carrier waves.

To make the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

For a chip with a plurality of JTAG TAP structures, a universal serial solution is to adopt a Daisy-chain (Daisy-chain) mode for all the JTAG TAPs in the chip, and share the TDI and the TDO serial chains, the TMS, the TCK and the TRST, so that although the whole system can be controlled by 5 standard JTAG interfaces, along with the increasing huge scale of network chips, a great number of JTAG TAP controllers may exist in one design, the Daisy-chain structure performs instruction coding operation on any JTAG TAP, and a complex and lengthy instruction has to be constructed, so that the JTAG control efficiency may be very low; moreover, in some low power consumption tests, the power domain where some JTAG TAPs are located needs to be turned off, which may cause the JTAG chain to be disconnected, resulting in limited application.

The parallel solution for the existence of a plurality of JTAG TAP structures in a chip is a STAR (STAR) connection mode, the TDI and the TDO of each TAP are distributed to independent pins by sharing three ports of TMS, TCK and TRST, the demand for test pins is increased along with the increase of the number of JTAG TAPs, and the available test pins are very limited which is a characteristic of the current chip, so the STAR connection mode is limited in application.

In a large-scale complex chip, JTAG control is adopted by DFT designs of many sub-modules (such as Harden block or IP) or DFT circuits generated by EDA tools, some of them may have integrated JTAG TAP circuits, some of them are based on IJTAG interface (IEEE1687), WTAP interface (IEEE 1500) and so on, and currently, existing solutions such as daisy chain or star structure have their own application limitations, and there is no way to uniformly control a plurality of JTAG TAP circuits in an efficient and concise manner. Moreover, most of the existing chips adopt a modular design, and the communication interfaces of the sub-module and the top-layer TAP in the existing scheme are as follows: the interface signals of the schemes such as the WTAP interface of IEEE1500 and the SIB of IJTAG are more, and the verification vector of the sub-module cannot be simply and efficiently mapped to the top layer. Meanwhile, in a large-scale chip, the number of sub-modules is very large, each module is provided with a JTAG control circuit, the control of the sub-modules is in a serial mode in the existing design, and the control efficiency is very low.

With the design scale of high-end chips becoming larger and larger, more and more used IPs and higher and more complex, the inventor of the present application thinks that the DFT design of the chip requires a set of unified and efficient JTAG control system, and at the same time, the inventor is also able to compatibly control the existing JTAG TAP circuit in the chip.

Fig. 1 is a schematic diagram of a composition structure of a JTAG control apparatus according to the present application, as shown in fig. 1, which at least includes: a master TAP control unit, at least one slave TAP control unit; wherein the content of the first and second substances,

the main TAP control unit includes at least: the system comprises a TAP control module, an enabling operation control module and a selection module; wherein the content of the first and second substances,

the TAP control module is used for connecting a chip JTAG interface (comprising a TCK interface, a TMS interface, a TRST interface, a TDI interface and a TDO interface); determining the bit number of an enable signal, i.e., a TAP _ E signal, and an output selection signal, i.e., a Sub _ TDO signal, according to the number of the slave TAP control units;

an enable operation control module for configuring an enable signal, i.e., a TAP _ E signal, and an output selection signal, i.e., a Sub _ TDO signal, according to the bit number of the enable signal, i.e., the TAP _ E signal, and the output selection signal, i.e., the Sub _ TDO signal;

the selection module is used for realizing the output selection of the multi-path input signals according to the enable signals and the output selection signals, namely the Sub _ TDO signals;

the slave TAP control unit includes at least: the device comprises a conversion module and a test control module; wherein the content of the first and second substances,

the conversion module is used for realizing interface conversion of the JTAG TAP test control circuit of the main TAP control unit and the slave TAP control unit;

and the test control module is used for performing DFT test control on the generated JTAG test control vector after the slave TAP control unit of the test control module is enabled, and mapping the JTAG test control vector to the selection module through the conversion module. JTAG control circuitry belonging to a standard protocol may be described in detail with reference to the IEEE1149.1 protocol.

In an illustrative example, the TAP control module is part of a JTAG standard protocol, and the JTAG circuitry enters different control states according to different control sequences of the TMS signal.

In one illustrative example, the number of bits of the enable signal, i.e., the TAP _ E signal, and the output select signal, i.e., the Sub _ TDO signal, are each equal to the number of slave TAP control units.

In an exemplary embodiment, the enabling operation control module may be a data register set (DR-Chain), and the TAP _ E signal of the slave TAP control unit, which needs to acquire JTAG interface communication, is set to 1, for example, by writing a value into the DR-Chain. For example, assuming that the slave TAP control unit includes 5 slave TAP control units, the number of bits of the enable signal, i.e., TAP _ E signal, is 5, and if it is necessary to enable the first, third and fourth slave TAP control units, the value of the enable signal, i.e., TAP _ E signal, may be equal to 10110.

In an illustrative example, the TCK interface, the TMS interface, the TRST interface, and the TDI interface in the JTAG interface on the chip enable the TAP _ E signal and the Sub _ TDO signal on the operation control module to be connected with the TAP _ E signal and the TDOi signal of the conversion module, wherein i is 1,2,3 … N.

The JTAG control device simply supports a plurality of sub JTAG TAP test control circuits to be connected with the main TAP control circuit, and effectively realizes JTAG test. The JTAG control device with the master-slave structure has good expansibility, and can mount an infinite number of slave TAP control units theoretically.

In one illustrative example, the main TAP control unit further comprises: a data operation control module for enabling the enable operation control module to perform a configuration of an enable signal, i.e., a TAP _ E signal, and an output select signal, i.e., a Sub _ TDO signal, under the control of the TAP control module in the main TAP control unit. In other words, the data operation control module generates an enable signal that enables the enable operation control module to implement the data operation of the main TAP control unit.

Through the data operation control module, the conflict of operation instructions among different TAPs is avoided, for example, the problem of misoperation of an instruction register of the main TAP control unit when the slave TAP control unit performs instruction coding operation is avoided.

In an exemplary embodiment, the data operation control module is specifically configured to:

the main TAP control unit is connected with the TAP control module in the main TAP control unit, and the connecting signal comprises an instruction coding operation signal of the TAP control module; and determining whether to enable the enabling operation control module according to the instruction encoding operation signal.

In an exemplary embodiment, fig. 2 is a schematic structural diagram of a data operation control module according to an embodiment of the present application, and as shown in fig. 2, the data operation control module may include: an instruction register set, an instruction comparison storage circuit, at least one instruction comparison circuit (in fig. 2, two instruction comparison circuits are taken as an example, namely a first instruction comparison circuit and a second instruction comparison circuit), and a decision circuit; wherein the content of the first and second substances,

an instruction register set for interfacing with the TAP control modules in the main TAP control unit, the interfacing signals including instruction encoding operation signals of the TAP control modules, such as: capture _ IR, Update _ IR, Shift _ IR, Select _ IR (these signals correspond to the status signals output by the TAP control module, i.e. the signals of the TAP state machine in the related art); store a loaded Instruction Register (IR) instruction;

the first instruction comparison circuit is preset with an expected instruction code, compares the expected instruction code with the preset expected instruction code after the first IR instruction is loaded, and outputs a first comparison result signal to the instruction comparison storage circuit; optionally, the loaded first IR instruction is compared and judged with the encoding length of the expected instruction encoding preset by the instruction comparison circuit itself (for example, the encoding length may be implemented by a counting function), and if the contents are completely consistent, the first comparison result signal is output to enable (or validate);

an instruction comparison storage circuit controlled by an instruction register set (such as a Capture _ IR signal), wherein before a next IR instruction is loaded, a first comparison result signal of a previous IR instruction is latched into the instruction comparison storage circuit;

the second instruction comparison circuit is preset with an expected instruction code, compares the second IR instruction code with the preset expected instruction code after the second IR instruction is loaded, and outputs a comparison result signal to the instruction comparison storage circuit; optionally, the loaded second IR instruction is compared and judged with the encoding length of the expected instruction encoding preset by the instruction comparison circuit itself (for example, the encoding length may be implemented by a counting function), and if the contents are completely consistent, a second comparison result signal is output to enable (or validate);

and the decision circuit is used for receiving the first comparison result signal from the instruction comparison storage circuit and the second comparison result signal from the second instruction comparison circuit, and when the first comparison result signal and the second comparison result signal are enabled, determining to enable the enabling operation control module and outputting an enabling control signal, namely a Select _ stop _ en signal. In one illustrative example, the decision circuit may be a gate circuit representing an and logical relationship.

In one illustrative example, the first IR instruction and the second IR instruction differ in bit width, and the loading of the first IR instruction and the second IR instruction requires sequential loading in a preset order.

It should be noted that, in the case where two or more instruction comparison circuits are included, the bit widths of the IR instructions loaded by the respective instruction comparison circuits in the preset order are different, which makes the present application have a stronger anti-collision capability. Of course, only one stage of the instruction comparison circuit may be provided, and at this time, the enable operation control module may be enabled by inputting the instructions according to the preset sequence and width, and the Data Register (DR) instruction may be loaded to operate the register in the operation control module.

With the embodiment of the data operation control module shown in fig. 2, only when the IR instruction is loaded twice consecutively and the requirement of the comparison code preset by the first IR instruction comparing circuit is met for the previous time, and the requirement of the comparison code preset by the second IR instruction comparing circuit is met for the second time, the enabling operation control module is enabled, and the DR instruction is also loaded to operate the register in the operation control module. The processing of the present application realizes anti-collision processing of the instruction codes of the main TAP control unit, that is, the main TAP control unit must continuously load a plurality of (e.g. two in fig. 2) specific instruction codes with different lengths before triggering the data operation of the main TAP control unit, and this processing effectively avoids instruction collision between the main TAP control unit and the slave TAP control unit.

In one illustrative example, where the main TAP control unit of the present application includes a data operation control module, the selection module is configured to:

the selection of the output of the multiplexed input signal is realized according to the enable control signal, the enable signal, and the Sub _ TDO signal, which is the output selection signal.

In an exemplary embodiment, the selection module controls the outputs of the data operation control module and the enable operation control module together to realize the output selection of the multi-input signal, i.e., the Sub _ TDO signal. In the default state (after TRST reset release), the TDO signal selects the TDO output from a slave TAP control unit, e.g., TDO _ i; the output from the data operation control module circuit or the enable operation control module may also be selected. When the control signal TAP _ E of a certain slave TAP control unit is enabled, then the TDO signal is selected from the TDO output of the slave TAP control unit.

Fig. 3 is a schematic structural diagram of an embodiment of a conversion module according to the present application, and as shown in fig. 3, the conversion module may include interface conversion circuits, which are JTAG TAP test control circuits of a master TAP control unit and a slave TAP control unit, connected to logic gate circuits, where the interface of the master TAP control unit and the conversion module includes: the chip comprises a TRST, a TCK, a TMS, a TDI and a TAP _ E, Sub _ TDO, wherein TCK, TMS, TRST and TDI signals are in butt joint with a JTAG interface on the chip, TAP _ E, TDO signals are in butt joint with TAP _ E, Sub _ TDO signals output by an enabling control operation module respectively, and TAP _ E signals are communication enabling control signals of the TMS and the TDI and are realized through the TMS and a first control logic circuit and the TDI and a second control logic circuit respectively.

It should be noted that, if a chip subsystem has a control circuit based on an IJTAG interface (IEEE1687) or a WTAP interface (IEEE 1500), a JTAG TAP controller, such as the IJTAG slave TAP controller in fig. 4 or the IEEE1500 slave TAP controller, is added to the JTAG control device of the present application, and then the JTAG TAP is converted into an interface of the slave TAP control circuit for connection by the interface connection manner shown in fig. 3.

According to the JTAG control device with the master-slave structure, the test signals of the whole chip can be controlled by the JTAG control device, and the JTAG TAP circuit which is existing in an IP or generated by an EDA tool is well compatible. In the JTAG control device, the number of the interfaces between the slave TAP control unit and the master TAP control unit is only 6 (namely, one slave TAP enabling signal and 5 standard JTAG signals), and the control of the slave TAP control unit is also based on the JTAG protocol, so that the vector of the slave TAP control unit is very efficiently mapped to the master TAP control unit, and the generation efficiency of the vector of the master TAP control unit is greatly improved.

In an exemplary embodiment, the same control signals in the slave TAP control units can be controlled in parallel in a broadcasting manner, and the control efficiency is greatly improved.

When the master TAP control unit needs to communicate with the JTAG TAP test control circuit (i.e., the test control module in fig. 1) of the slave TAP control unit, as shown in fig. 5, the method at least includes:

step 500: different IR instructions are loaded sequentially in a preset order.

In one illustrative example, the IR instructions may include one or more than one.

Step 501: and each time the IR instruction is loaded, comparing the loaded IR instruction with the preset expected instruction code, and obtaining a valid comparison result when the loaded IR instruction is completely consistent with the preset expected instruction code.

In one illustrative example, the loading of IR instructions that are fully consistent with the preset expected instruction encodings may include: the loaded IR instruction is consistent with a preset length of the expected instruction encoding.

Step 502: and when the comparison result of each IR instruction loaded continuously is effective, loading the data register code to enable the slave TAP control unit which needs to communicate with the master TAP control unit through the JTAG interface.

Therefore, after the data register code loading is completed, the JTAG interface is communicated with a JTAG TAP test control circuit of the slave TAP control unit. Particularly, in the bottom-Up design, the JTAG TAP test control circuit of the slave TAP control unit already has the JTAG application stimulus passed through the debugging, and the application stimulus of the sub-module can be mapped to the top layer only by the operations of the steps 500 to 502 based on the vector loading of the sub-module, i.e., the slave TAP control unit, in the top layer, i.e., the master TAP control unit.

The above description is only a preferred example of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A joint test action group, JTAG, control apparatus, comprising: a main test access port TAP control unit and at least one slave TAP control unit;

wherein the main TAP control unit at least comprises: the system comprises a TAP control module, an enabling operation control module and a selection module; wherein the content of the first and second substances,

the TAP control module is used for connecting a chip JTAG interface; determining the number of bits of the enable signal and the output selection signal according to the number of the slave TAP control units;

the enabling operation control module is used for configuring an enabling signal and an output selection signal according to the bit number of the enabling signal and the output selection signal;

the selection module is used for realizing the output selection of the multi-path input signals according to the enabling signals and the output selection signals;

wherein the slave TAP control unit includes at least: the device comprises a conversion module and a test control module; wherein the content of the first and second substances,

the conversion module is used for realizing interface conversion of the JTAG TAP test control circuit of the main TAP control unit and the slave TAP control unit;

and the test control module is used for performing DFT test control on the generated JTAG test control vector after the slave TAP control unit of the test control module is enabled, and mapping the JTAG test control vector to the selection module through the conversion module.

2. The JTAG control arrangement of claim 1, wherein the enable operation control module is a data register set DR-Chain;

the enabling of the configuration of the enable signal in the operation control module includes: and writing a numerical value into the DR-Chain, and setting the enabling signal of the slave TAP control unit needing to acquire JTAG interface communication.

3. The JTAG control arrangement of claim 1 or 2, the main TAP control unit further comprising: and the data operation control module is used for enabling the operation control module to carry out the configuration of the enabling signal and the output selection signal under the control of the main TAP control module.

4. The JTAG control of claim 3, wherein the selection module is specifically configured to: and realizing the output selection of the multi-path input signals according to the enable control signal, the enable signal and the output selection signal.

5. The JTAG control of claim 3, wherein the data manipulation control module is further configured to: the TAP control module is connected with the input end of; and determining whether to enable the operation control module according to the instruction encoding operation signal.

6. The JTAG control of claim 3, wherein the data operation control module includes: the device comprises an instruction register group, an instruction comparison storage circuit, a first instruction comparison circuit, a second instruction comparison circuit and a decision circuit; wherein the content of the first and second substances,

the instruction register group is used for being connected with the TAP control module, and the connecting signal comprises an instruction coding operation signal of the TAP control module; storing the loaded IR instructions;

the first instruction comparison circuit is preset with an expected instruction code, compares the expected instruction code with the preset expected instruction code after the first IR instruction is loaded, and outputs a first comparison result signal to the instruction comparison storage circuit;

the instruction comparison storage circuit is controlled by the instruction register group, and a first comparison result signal of a previous IR instruction is latched into the instruction comparison storage circuit before a next IR instruction is loaded;

the second instruction comparison circuit is preset with an expected instruction code, compares the second IR instruction code with the preset expected instruction code after the second IR instruction is loaded, and outputs a comparison result signal to the instruction comparison storage circuit;

and the decision circuit is used for receiving the first comparison result signal from the instruction comparison storage circuit and the second comparison result signal from the second instruction comparison circuit, and determining to enable the operation control module and outputting an enable control signal when the first comparison result signal and the second comparison result signal are enabled.

7. The JTAG control of claim 6, wherein the first IR instruction and the second IR instruction differ in bit width and the loading of the first IR instruction and the second IR instruction require sequential loading in a preset order.

8. A method of implementing JTAG control, comprising:

continuously loading different IR instructions according to a preset sequence;

loading the IR instruction each time, comparing the loaded IR instruction with a preset expected instruction code, and obtaining an effective comparison result when the loaded IR instruction is completely consistent with the preset expected instruction code;

and when the comparison result of each IR instruction loaded continuously is effective, loading the data register code to enable the slave TAP control unit which needs to communicate with the master TAP control unit through the JTAG interface.

9. The method of claim 8, wherein the IR instructions comprise one or more.

10. The method of claim 8, wherein the loaded IR instruction is fully consistent with a preset expected instruction encoding, comprising: the IR instructions loaded are consistent with the length of the preset expected instruction encoding.

Images