CN112565778B - Data access method based on time slice management - Google Patents
Data access method based on time slice management Download PDFInfo
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- CN112565778B CN112565778B CN202011575381.8A CN202011575381A CN112565778B CN 112565778 B CN112565778 B CN 112565778B CN 202011575381 A CN202011575381 A CN 202011575381A CN 112565778 B CN112565778 B CN 112565778B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
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Abstract
The invention discloses a data access method based on time slice management, which realizes data reading and writing through an AXI bus, distributes reading and writing work based on DDR bus bandwidth limitation, sets the generation time sequence of each path of data according to task needs, ensures that modules cooperatively operate, distributes the occupation situation of the bus as evenly as possible, and reserves certain redundancy to deal with newly added tasks at the same time so as to maximize the bus efficiency. The method is used for data caching and framing, the system is small in occupied bandwidth and good in real-time performance, time sequences among modules are independent, and the algorithm is easy to realize and transplant.
Description
Technical Field
The invention discloses a data access method, in particular to a data access method based on time slice management.
Background
In the engineering implementation process of the system, sometimes, the data volume needing to be processed and stored in real time is large, and the storage requirement must be met by matching an off-chip memory with an FPGA. The off-chip memory must have the characteristics of large capacity and high-speed storage, thereby further ensuring the overall performance of the infrared imaging system. Therefore, DDR3 is selected as a data memory, and the control of the DDR3 memory is realized by using the MIG core of xilinx, and at this time, DDR3 needs to be mounted on the AXI bus for data caching. The conventional read-write mode is usually realized based on a DMA mode, the read-write sequence is controlled through data priority, but the bus time occupied by data is fixed, the modules have strong pipeline dependence relationship, once a certain module changes data, the time sequence of each module needs to be adjusted, and the independence is poor. The method is used for data caching and framing, has good real-time performance, and is easy to realize and transplant the algorithm.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses a data access method based on time slice management, which realizes data reading and writing through an AXI bus, distributes reading and writing work based on DDR bus bandwidth limitation, sets the occurrence time sequence of each path of data according to task needs, ensures that all modules cooperate to distribute the occupation condition of the bus as evenly as possible, and reserves certain redundancy to deal with newly added tasks at the same time so as to maximize the bus efficiency.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a data access method based on time slice management comprises the following steps:
s01), selecting an AXI bus clock, taking 40ms as a frame period according to an analog video coding standard, and dividing time slices within 40ms to complete module operation; DDR is adopted as a data cache chip, and the DDR performs data interaction with each functional module through an AXI bus; selecting an AXI bus clock as T according to the communication bandwidth required by the system and data streams generated by interaction of each functional module and DDR data;
s02), setting a master control clock for each functional module according to the bus clock and the processing task of each functional module, wherein the master control clock of each functional module meets the bandwidth requirement of the AXI bus clock, and the master control clock of each functional module has positive correlation with the complexity of the processing task;
s03), dividing the DDR into blocks according to the functional modules, wherein each block stores the data of the detector at a specific moment so as to avoid read-write collision;
s04), designing the starting time and the occupied bandwidth time sequence of each functional module, multiplexing the bus communication in a time-sharing manner, and dividing the bus communication into time slices with variable lengths, wherein each time slice is responsible for the communication of one functional module; the data reading time of each functional module is continuous, but the starting time between each functional module occurs randomly.
Furthermore, when a new functional module is added, firstly, the occupied bandwidth and time length of the module are calculated according to the processing task and the clock of the module, then, the starting time of the new module is designed according to the time sequence occupation condition of the existing functional module, and the data reading and processing time of the new module is staggered with the data writing of the previous frame, so that the problem that the acquired images of the frames before and after one reading and writing operation are inconsistent is avoided.
Further, the AXI bus clock is 100M to 150M.
Further, the AXI bus clock is 108M.
Furthermore, the method is used for data access of infrared images, the functional module comprises a detector driving framing module, a non-uniform correction module, an enhanced filtering algorithm module, a character superposition module and a video coding output module, the main control clock of the detector driving framing module is 10M, the main control clock of the non-uniform correction module is 13.5M, the main control clock of the enhanced filtering algorithm module is 108M, the main control clock of the non-uniform correction module is 54M, and the main control clock of the video coding output module is 27M.
Furthermore, the DDR is divided into blocks according to the functional modules, the size of each block is 1MB, the first block stores original 16-bit data of the current frame, and the size is 640 multiplied by 512 pixels; the second block stores the 16-bit data of the previous frame, and the size of the second block is 640 multiplied by 512 pixels; the third block stores 16-bit K-value data, the size of which is 640 x 512 pixels; the fourth block stores 16-bit B value data, and the size of the data is 640 multiplied by 512 pixels; the fifth block stores the non-uniformly corrected 16-bit data, and the size of the data is 640 multiplied by 512 pixels; the sixth block stores 8-bit data after the enhanced filtering algorithm, and the size of the data is 640 multiplied by 512 pixels; the seventh block stores 8-bit data after character superposition, and the size of the data is 768 × 576 pixels.
The invention has the beneficial effects that: the bus time sequence design of the invention is reasonable and efficient, the system behavior can be predicted, the condition of initiating communication in a burst way can be avoided, in addition, the AXI bus load can be reduced, and the collision of bus data frames can be avoided. The master control clock and the starting time of each functional module are determined at will, and the flexibility is strong. The method is used for data caching and framing, the system is small in occupied bandwidth and good in real-time performance, time sequences among modules are independent, and the algorithm is easy to realize and transplant.
Drawings
FIG. 1 is a schematic diagram of functional modules of an infrared image data acquisition and display system related to data caching;
FIG. 2 is a schematic diagram of time slice division of functional modules.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The embodiment discloses a data access method based on time slice management, which is used for an infrared image data acquisition and display system to perform data access on an infrared image. The method of the embodiment comprises the following steps:
s01), one high-speed AXI bus clock is selected first. According to the analog video coding standard, 40ms is taken as the period of one frame, and the module operation including data acquisition and video coding output of odd fields and even fields is completed within 40ms by dividing a time slice. DDR3 is adopted as a data cache chip, and DDR3 carries out data interaction with a functional module through an AXI bus. And selecting the AXI bus clock to be 108M according to the communication bandwidth required by the system and the data volume generated by the interaction of the functional module and the DDR data.
S02), setting a master control clock for each functional module according to the bus clock and the processing task of each functional module to ensure the normal work of each functional module. The master control clock of each functional module should meet the bandwidth requirement of the AXI bus clock, and the master control clock of each functional module has positive correlation with the complexity of the processing task thereof.
In this embodiment, as shown in fig. 1, the modules of the infrared image data acquisition and display system related to the data cache include a detector driving framing module, a non-uniformity correction module, an enhanced filtering algorithm module, a character superposition module, and a video encoding output module. Fig. 1 shows each module and its master clock frequency setting. The main control clock of the detector driving framing module is 10M, the main control clock of the non-uniform correction module is 13.5M, the main control clock of the enhanced filtering algorithm module is 108M, the main control clock of the non-uniform correction module is 54M, and the main control clock of the video coding output module is 27M.
S03), dividing the DDR3 into blocks according to the functional modules, wherein the size of each block is 1MB, and each block stores probe data at a specific certain moment so as to avoid read-write collision.
In the embodiment, the DDR3 is divided into 7 blocks, the first block stores the original 16-bit data of the current frame, and the size of the first block is 640 multiplied by 512 pixels; the second block stores the 16-bit data of the previous frame, and the size of the second block is 640 multiplied by 512 pixels; the third block stores 16-bit K-value data, the size of which is 640 x 512 pixels; the fourth block stores 16-bit B value data, and the size of the data is 640 multiplied by 512 pixels; the fifth block stores the non-uniformly corrected 16-bit data, and the size of the data is 640 multiplied by 512 pixels; the sixth block stores 8-bit data after the enhanced filtering algorithm, and the size of the data is 640 multiplied by 512 pixels; the seventh block stores 8-bit data after character superposition, and the size of the data is 768 × 576 pixels.
The K value data and the B value data are correction values.
S04), designing the starting time and the occupied bandwidth time sequence of each functional module, multiplexing the bus communication in a time-sharing way, and dividing the bus communication into time slices with variable lengths, wherein each time slice is responsible for the communication of one functional module.
In the present embodiment, 40ms is taken as a timing cycle, and the time occupied by each module in 40ms is shown in fig. 2, and (1) - (5) respectively correspond to the five sub-function modules in fig. 1. As can be seen from the time slice flow chart of fig. 2, the data reading time of each module is continuous, but the starting time between modules can occur randomly. Therefore, on the basis of limited bus bandwidth, to ensure that data read and write do not conflict, each module needs to be reasonably distributed within 40 ms.
When a new functional module is added, firstly, the occupied bandwidth and time length of the module are calculated according to the processing task and the clock of the module, then, the starting time of the new module is designed according to the time sequence occupation condition of the existing functional module (figure 2), and the new module is added into the system. The time of data reading and processing of the new module is staggered with the time of data writing of the previous frame, so that the problem of inconsistent image acquisition of the previous frame and the next frame after one reading and writing operation is avoided.
The operation completion time interval for reading data once by any module of the method is 40 ms; in each turn, data transmission is carried out on the data of each module on the time slice to which the data belong; in each turn, data is communicated and transmitted with the DDR through the AXI bus, and current frame data is transmitted only once; in each turn, the data side read DDR operations do not conflict with each other. The bus time sequence is reasonable and efficient in design, the system behavior can be predicted, the condition of burst communication initiation can be avoided, in addition, the AXI bus load can be reduced, and the collision of bus data frames can be avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the present invention and do not limit the technical solutions described in the present invention. Therefore, although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the present invention may be modified and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and protected by the following claims.
Claims (6)
1. A data access method based on time slice management is characterized in that: the method comprises the following steps:
s01), selecting an AXI bus clock, taking 40ms as a frame period according to an analog video coding standard, and dividing time slices within 40ms to complete module operation; DDR is adopted as a data cache chip, and the DDR performs data interaction with each functional module through an AXI bus; selecting an AXI bus clock as T according to the communication bandwidth required by the system and data streams generated by interaction of each functional module and DDR data;
s02), setting a master control clock for each functional module according to the bus clock and the processing task of each functional module, wherein the master control clock of each functional module meets the bandwidth requirement of the AXI bus clock, and the master control clock of each functional module has positive correlation with the complexity of the processing task;
s03), dividing the DDR into blocks according to the functional modules, wherein each block stores the data of the detector at a specific moment so as to avoid read-write collision;
s04), designing the starting time and the occupied bandwidth time sequence of each functional module, multiplexing the bus communication in a time-sharing manner, and dividing the bus communication into time slices with variable lengths, wherein each time slice is responsible for the communication of one functional module; the data reading time of each functional module is continuous, but the starting time between each functional module occurs randomly.
2. The method of claim 1, wherein the data access method based on time slice management comprises: when a new functional module is added, firstly, the occupied bandwidth and time length of the module are calculated according to the processing task and the clock of the module, then, the starting time of the new module is designed according to the time sequence occupied condition of the existing functional module, and the data reading and processing time of the new module is staggered with the data writing of the previous frame, so that the problem that the acquired images of the previous frame and the acquired images of the next frame are inconsistent before and after one reading and writing operation is avoided.
3. The method of claim 1, wherein the data access method based on time slice management comprises: the AXI bus clock is 100M to 150M.
4. The method of claim 3, wherein the data access method based on time slice management comprises: the AXI bus clock is 108M.
5. The method of claim 2, wherein the data access method based on time slice management comprises: the method is used for data access of infrared images, the functional module comprises a detector driving framing module, a non-uniform correction module, an enhanced filtering algorithm module, a character superposition module and a video coding output module, a main control clock of the detector driving framing module is 10M, a main control clock of the non-uniform correction module is 13.5M, a main control clock of the enhanced filtering algorithm module is 108M, a main control clock of the non-uniform correction module is 54M, and a main control clock of the video coding output module is 27M.
6. The method of claim 5, wherein the data access method based on time slice management comprises: DDR is divided into blocks according to functional modules, the size of each block is 1MB, the first block stores original 16-bit data of a current frame, and the size of each block is 640 multiplied by 512 pixels; the second block stores the 16-bit data of the previous frame, and the size of the second block is 640 multiplied by 512 pixels; the third block stores 16-bit K-value data, the size of which is 640 x 512 pixels; the fourth block stores 16-bit B value data, and the size of the data is 640 multiplied by 512 pixels; the fifth block stores the non-uniformly corrected 16-bit data, and the size of the data is 640 multiplied by 512 pixels; the sixth block stores 8-bit data after the enhanced filtering algorithm, and the size of the data is 640 multiplied by 512 pixels; the seventh block stores 8-bit data after character superposition, and the size of the data is 768 × 576 pixels.
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Inventor after: Niu Huizhuo Inventor after: Liu Guoxing Inventor after: Wei Guangxu Inventor after: Zhu Lei Inventor after: Gao Guojing Inventor after: Lv Junjie Inventor after: Su Mingchen Inventor after: Liu Jianliang Inventor before: Niu Huizhuo Inventor before: Liu Guoxing Inventor before: Wei Guangxu Inventor before: Zhu Lei Inventor before: Gao Guojing Inventor before: Lv Junjie Inventor before: Su Mingchen Inventor before: Liu Jianliang |
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