CN112565762B - Method and device for equalizing coding of multichannel video images suitable for carrier rocket - Google Patents
Method and device for equalizing coding of multichannel video images suitable for carrier rocket Download PDFInfo
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- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
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- H—ELECTRICITY
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
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Abstract
The invention discloses a balanced coding method and a balanced coding method of a multichannel video image suitable for a carrier rocket, wherein the method comprises the following steps: s1: creating coding library examples of N channels, and setting an H264 image balanced coding strategy in the coding library examples; s2: receiving collected multi-channel video images with the same resolution ratio in real time, and storing each video image in different cache regions; s3: and dynamically coding the video images in different buffer areas at the same moment by using an H264 image balanced coding strategy to balance the coded data in multiple channels, and packaging and outputting the coded data of the multiple channel video images at the same moment after the coding is finished. The invention dynamically balances the code rate of multiple channels by an H264 image balanced coding strategy, fully and effectively utilizes the channel bandwidth and outputs low-delay high-quality images.
Description
Technical Field
The invention relates to the field of video coding, in particular to a method and a device for balanced coding of a multichannel video image suitable for a carrier rocket.
Background
With the maturity of image compression technology, images have been used as the most common information transmission method, can provide richer contents than other data forms, and are also indispensable in aerospace launch tasks. However, in space launch vehicle applications, because the transmission channel bandwidth is limited, only a small number of channels are often allocated for transmitting image data. However, due to the weight limitation of the carrier rocket on the carried products, when video images in multiple directions need to be observed, a plurality of image coding devices only with single-channel images cannot be installed on the carrier rocket, so that the multi-channel image coding device is developed.
The H.264 image compression technology has a high data compression ratio, and under the condition of equal image quality, the compression ratio of the H.264 is more than 2 times of that of MPEG-2 and 1.5-2 times of that of MPEG-4. Meanwhile, H.264 has high-quality smooth images while having a high compression ratio; meanwhile, the aerospace field has high reliability requirements on products and equipment, and the H.264 image compression technology has high maturity and high reliability after years of iteration, so that the H.264 image compression technology is adopted in the image compression data technology of the image equipment of the launch vehicle.
Because the shooting angles and positions of the channels are different, the image complexity is different, so that the actually generated code rate of each channel image is different under the condition of setting the same H.264 coding code rate, and the simpler the image, the lower the code rate, the more complicated the image, the higher the code rate. Meanwhile, although the installation position of each channel camera is known in advance, the code rate of each channel image coding can change along with the change of the external illumination environment, so that the preset code rate cannot be installed.
Disclosure of Invention
The embodiment of the application provides an H.264 image equalization coding method of a multichannel video image, solves the problem that the coding code rate of each channel video image in the prior art can not be determined, adopts multichannel H.264 coding, realizes dynamic equalization control of the coding code rate of the multichannel image, and achieves the purposes of fully and effectively utilizing channel bandwidth and outputting low-delay high-quality images.
In a first aspect, an embodiment of the present application provides an equalizing encoding method for a multichannel video image suitable for a launch vehicle, where the method includes:
s1: creating coding library examples of N channels, and setting an H264 image balanced coding strategy for the coding library examples;
the H264 image equalization coding strategy comprises the following steps: calculating the initial code rate of H264 coding of each channel according to the preset total code rate M of the channel so as to encode H264 images according to the initial code rate in the initial state; acquiring the real-time code rate of each channel according to the preset key frame interval and the frame rate so as to dynamically adjust the H264 coding code rate of the corresponding channel in real time;
s2: receiving collected multi-channel video images with the same resolution ratio in real time, and storing each video image in different cache regions;
s3: and respectively dynamically coding the video images in different buffer areas at the same moment by using an H264 image balanced coding strategy so as to balance the coded data in multiple channels, and packaging and outputting the coded data of the multiple channel video images at the same moment after the coding is finished.
Further, in step S3, the method for dynamically encoding the video images in different buffer areas at the same time by using the H264 image equalization encoding policy includes:
s31: receiving an initial code rate Ki, (M/N) 90% for each channel H264 encoding;
s32: calculating the real-time code rate Li of the H264 code of each channel based on a preset statistical period S;
s33: calculating the ratio Ri of the real-time code rate Li of each channel to the initial code rate Ki;
s34: screening out a channel X with the maximum ratio Ri and a channel Y with the minimum ratio Ri according to the ratio Ri;
s35: adjusting the H264 coding rate Kx, Kx ═ 110% Ki of the channel X, and adjusting the H264 coding rate Ky, Ky ═ 90% Ki of the channel Y, so as to equalize the H264 coding rates of the multiple channels;
s36: and encoding the video image of the buffer area according to the adjusted H264 encoding code rate, and repeating the steps S31-S36.
In a second aspect, the present application provides an apparatus for equalizing and encoding multichannel video images suitable for a launch vehicle, which includes a hardware portion and a software portion configured therewith, where the hardware portion includes: the system comprises an FPGA chip, a DSP processor and a plurality of paths of cameras; the software part comprises: an H264 image equalization coding program arranged on the DSP processor; the H264 dynamic coding program adopts the balanced coding method of the multi-channel video image suitable for the carrier rocket, which is described in the first aspect;
the FPGA chip is connected with the multi-path cameras to acquire acquired video images in a multi-channel mode;
the DSP processor is connected with the FPGA chip through an EMIF, a VPIF, a GPIO and a reset pin and is used for receiving the video image of each channel; and respectively carrying out H264 image coding on the multi-channel video images by utilizing an H264 image equalization coding program.
Furthermore, the hardware part comprises a FLASH register, and the FLASH register is connected with the DSP processor and stores the original video image before encoding in a multi-channel partition mode.
Furthermore, the hardware part comprises a DDR register, the DDR register is externally connected with the DSP processor, and encoded data of the encoded video images are stored in a time sequence through the DDR register.
Further, the hardware part also comprises a clock module, wherein the clock module is connected with the DSP processor and is used for configuring a clock value meeting the requirement of H264 coding; and is used for providing reset signals, including reset signals for power-on initialization and watchdog reset signals when work is abnormal.
Further, the DSP processor adopts a TMS320DM6467 chip of TI company.
Further, the FPGA chip adopts an XC4VLX25 chip of XILINX company.
The method and the device for the balanced coding of the multichannel video image suitable for the carrier rocket provided by the embodiment of the application have the following technical effects:
1. due to the adoption of the H264 image equalization coding strategy, the code rate of multiple channels is dynamically equalized within the total code rate of the fixed H264 coding, the channel bandwidth is fully and effectively utilized, and low-delay high-quality images are output.
2. Because a plurality of channels are adopted to dynamically adjust the code rate, the coding transmission of the multi-channel video image is effectively controlled.
Drawings
Fig. 1 is a flowchart of an equalizing encoding method for multi-channel video images according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating dynamic encoding using an H264 image equalization encoding strategy according to an embodiment of the present application;
fig. 3 is a block diagram of an equalizing encoding apparatus for multi-channel video images suitable for a launch vehicle according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.
Implementation mode one
Referring to fig. 1, an embodiment of the present application provides an equalizing encoding method for a multi-channel video image suitable for a launch vehicle, and the method includes the following steps.
Step S1: and creating coding library examples of N channels, and setting an H264 image balanced coding strategy for the coding library examples.
The H264 image equalization coding strategy comprises the following steps: calculating the initial code rate of H264 coding of each channel according to the preset total code rate M of the channel so as to encode H264 images according to the initial code rate in the initial state; and acquiring the real-time code rate of each channel according to the preset key frame interval and the preset frame rate so as to dynamically adjust the H264 coding code rate of the corresponding channel in real time.
In step S1, code library instances of N channels are created according to the set parameters such as the width, height, total code rate of the channel, and frame rate of the video image.
The equalizing coding method in the embodiment is suitable for multi-channel video image transmission on a running rocket, wherein due to the fact that complexity of video images is uneven in the video image transmission process, due to environmental changes and complexity of the video images, coding of the video images cannot be carried out according to the preset H264 coding rate. For example, shot video images are acquired in real time from different angles and positions, and a plurality of video images are generated at the same time, and the encoding efficiency is directly influenced by the different complexity of the video images. In the embodiment, an H264 image equalization coding strategy is adopted, and dynamic coding is performed on each path of collected video images in a multi-channel mode, so that the code rate of each channel is dynamically adjusted according to the complexity of the video image of each channel or the environment and other reasons on the premise of fixing the total code rate of the channel, and the code rate of each channel is automatically and dynamically adjusted on the premise of realizing the equalization of the total code rate.
Step S2: and receiving the collected multi-channel video images with the same resolution ratio in real time, and storing each video image in different cache regions. In this step, video images of different channels at the same time are stored in different buffer areas, so that when H264 encoding is performed, video images at unused times are obtained from different buffer areas.
Step S3: and respectively carrying out dynamic coding on the video images in different buffer areas at the same time by using an H264 image balanced coding strategy so as to balance the coded data in multiple channels, and packaging and outputting the coded data of the multiple channel video images at the same time after the coding is finished.
Further, in step S3, referring to fig. 2, the method for dynamically encoding video images in different buffer areas at the same time by using the H264 image equalization encoding policy includes:
step S31: the initial code rate Ki, (M/N) 90% for each channel H264 encoding is received.
Step S32: and calculating the real-time code rate Li of the H264 code of each channel based on a preset statistical period S. The predetermined statistical period may be between 2 seconds and 10 seconds.
Step S33: and calculating the ratio Ri of the real-time code rate Li of each channel to the initial code rate Ki.
Step S34: and screening the channel X with the maximum ratio Ri and the channel Y with the minimum ratio Ri according to the ratio Ri.
Step S35: adjusting the H264 coding rate Kx, Kx ═ 110% × Ki for channel X, and adjusting the H264 coding rate Ky, Ky ═ 90% × Ki for channel Y, to equalize the H264 coding rates of the multiple channels.
Step S36: and encoding the video image of the buffer area according to the adjusted H264 encoding code rate, and repeating the steps S31-S36.
As can be seen from steps S31 to S36, in the present embodiment, the ratio of the real-time code rate of H264 coding of each channel to the set initial code rate of H264 coding is used, and the H264 coding code rate setting value of the corresponding channel is adjusted according to the obtained maximum ratio and minimum ratio.
Further, N code library instances are created according to the set parameters of the image width, the height, the total code rate, the frame rate and the like. I.e. one code library instance per channel. H264 encoding of N-channel video pictures, for example, N channels each encode a frame of pictures independently, one I-frame every 25 frames, followed by 24P-frames, each in a period of 40 milliseconds. The I frame represents a key frame in H264 encoding, and the P frame represents a predictive encoded frame in H264 encoding. In the embodiment, every fixed time of S seconds, S can be selected to be 2 seconds to 10 seconds, and the h.264 real-time code rate of each channel is counted once. And at the same moment, calculating the real-time code rate of each channel, and counting the real-time code rate of the H264 code of each channel.
Second embodiment
Referring to fig. 3, the present embodiment provides an apparatus for equalizing and encoding multichannel video images suitable for a launch vehicle, which includes a hardware component and a software component configured with the hardware component. The hardware portion in the present embodiment includes: the system comprises an FPGA chip, a DSP processor and a plurality of paths of cameras; the software part comprises: an H264 image equalization coding program arranged on the DSP processor; the H264 dynamic coding program adopts the equalization coding method of the multi-channel video image suitable for the launch vehicle in the first embodiment.
The FPGA chip in the embodiment is connected with a plurality of paths of cameras, and video images acquired by the cameras are acquired in a multi-channel mode; that is, each channel acquires a video image acquired by one camera. The DSP processor is connected with the FPGA chip through an EMIF, a VPIF, a GPIO and a reset pin and is used for receiving video images of all channels; and respectively carrying out H264 image coding on the multi-channel video images by utilizing an H264 image equalization coding program.
The embodiment is described by taking three channels as an example, and certainly not limited to three channels, it is understood that the invention is applicable to any number of channels, and optionally, the number of channels is not more than eight.
As shown in table 1, basic information of the image device.
TABLE 1
In one embodiment, the DSP processor employs a TMS320DM6467 chip from TI, Inc. The FPGA chip adopts XC4VLX25 chip of XILINX company. Further, the H264 dynamic encoding program in the DSP processor adopts C code and Verilog code.
Further, each channel of the coding library example in the DSP processor is simultaneously aligned with the first camera, the second camera and the third camera, and H264 coding processing is carried out on the three paths of video images. In this embodiment, the resolution of the video image collected by none of the cameras is 704 × 288, and the FPGA chip is responsible for receiving the video images collected by the three cameras and transmitting the original video images to the DSP processor through the VPIF interface. At this time, the DSP processor does not directly perform the encoding process.
Further, it is assumed that the total code rate allocated to the image channel is 3Mbps, and further, during the encoding process, the maximum code rate of each channel is 3Mbps/3 — 1Mbps, and in order to ensure the channel margin, the initial code rate of each channel is set to Ki ═ 3/2 × -90% > -900 kbps, so that when each channel is encoded, a dynamic adjustment space is included. In the present embodiment, in order to ensure image equalization and recoverability after channel error, the I-frame interval of an image is set to 1 second, and the frame rate is set to 25 frames.
By calling the code library function CH264AppObj H264APP _ create (int32_ t ihehight, int32_ t iWidth, int32_ t iPitch, int32_ t iFrameRate, int32_ t iBitRate, int32_ t iGop).
Three code library examples, pH264Obj1, pH264Obj2, and pH264Obj3, were created in sequence, where the parameters ihehight are image height, iWidth is image width, iPitch is image width memory occupied byte, iFrameRate is frame rate, iBitRate is code rate, and iGop is I frame interval.
In one embodiment, three channels independently encode one frame of image every 40 milliseconds, one I-frame every 25 frames, followed by 24P-frames, when three channel image encoding is performed by the DSP processor.
The hardware part in the embodiment comprises a FLASH register which is connected with the DSP processor and used for storing the video image before processing. Namely, the original video image received by the DSP processor is firstly stored in the FLASH register. In order to distinguish the video images collected by the cameras of each channel conveniently, in the embodiment, the storage space in the FLASH register is partitioned, and the video images collected by the cameras of different channels are stored in the partitions with different addresses.
The hardware part in the embodiment comprises a DDR register, the DDR register is externally connected with a DSP processor, and the DDR register is used for storing the encoded data of the processed video image. Further, in the embodiment, the DDR register stores the encoded data of the video images in time series, that is, stores the encoded data of the video images captured by all the cameras in the multiple channels at the same time. Further, in this embodiment, the video images are captured simultaneously by the multi-channel camera, so that it can be understood that the video images including multiple channels in the same time period need to be transmitted simultaneously with the encoded data of all the video images at the same time when receiving and transmitting the video images. The DSP processor realizes H264 coding by calling an H264APP _ encode function, the three channels are distinguished and coded by using respective coding library examples, the three channels are independent from each other and do not influence each other, coded data are placed in a DDR register, and byte lengths EncLEN1, EncLEN2 and EncLEN3 output by the DSP processor are recorded.
According to the image data format, the DSP packages the coded data and sends the coded data to the FPGA chip through the EMIF interface, the FPGA chip outputs the coded data to the outside through the LVDS interface, and the image data format is shown in the table 2.
TABLE 2 image data Format
The hardware part in this embodiment further includes a clock module, where the clock module is connected to the DSP processor, and is configured to configure several clock values that meet the H264 coding requirement, and is configured to provide reset signals, including a reset signal for power-on initialization and a watchdog reset signal when the work is abnormal. In the embodiment, h.264 real-time code rate Li of each channel is counted once every fixed time S seconds (S is suggested to be between 2 seconds and 10 seconds), and a ratio Ri of the real-time code rate Li and the encoding target code rate Ki is calculated. Namely, the real-time code rate of each channel is counted once every 5 seconds, the 5-second average real-time code rate L1 of the first channel is sigma EncLEN1j/5, and j is more than or equal to 1 and more than or equal to 125; the 5-second average real-time code rate L2 of the second channel is sigma EncLEN2j/5, and j is more than or equal to 1 and more than or equal to 125; the 5-second average real-time code rate L3 of the third channel is sigma EncLEN3j/5, and j is more than or equal to 1 and more than or equal to 125. Calculating a ratio K of the real-time code rate and the coding target code rate, wherein the ratio R1 of the first channel is L1/K1, the ratio R2 of the second channel is L2/K2, and the ratio R3 of the third channel is L3/K3; acquiring a channel i with the maximum ratio and a channel j with the minimum ratio, and adjusting the H.264 coding code rates of the channel i and the channel j, wherein Ki is (Ki) 110%, and Kj is (Kj) 90%; assuming that the channel with the largest ratio is the first channel and the channel with the smallest ratio is the third channel at a certain time, the coding rate K1 of the first channel is adjusted to be K1 × 110%, and the coding rate K3 of the third channel is adjusted to be K3 × 90%. And further coding each channel according to the newly set code rate.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A method for equalized encoding of a multi-channel video image suitable for a launch vehicle, the method comprising:
s1: creating coding library examples of N channels, and setting an H264 image balanced coding strategy for the coding library examples;
the H264 image equalization coding strategy comprises the following steps: calculating the initial code rate of H264 coding of each channel according to the preset total code rate M of the channel so as to encode H264 images according to the initial code rate in the initial state; acquiring the real-time code rate of each channel according to the preset key frame interval and the frame rate so as to dynamically adjust the H264 coding code rate of the corresponding channel in real time;
s2: receiving multi-channel video images with the same resolution ratio in real time, and storing each video image in different cache regions;
s3: respectively dynamically encoding the video images of different cache regions at the same time by using an H264 image equalization encoding strategy to equalize encoded data in multiple channels, and packaging and outputting the encoded data of the multiple channels of video images after encoding is completed;
the method for respectively dynamically coding the video images in different cache regions at the same time by using the H264 image equalization coding strategy comprises the following steps:
s31: receiving an initial code rate Ki, (M/N) 90% for each channel H264 encoding;
s32: calculating the real-time code rate Li of the H264 code of each channel based on a preset statistical period S;
s33: calculating the ratio Ri of the real-time code rate Li of each channel to the initial code rate Ki;
s34: screening out a channel X with the maximum ratio Ri and a channel Y with the minimum ratio Ri according to the ratio Ri;
s35: adjusting the H264 coding code rate Kx and Kx to 110% Ki of the channel X, and adjusting the H264 coding code rate Ky and Ky to 90% Ki of the channel Y to balance the H264 coding code rates of the multiple channels;
s36: and encoding the video image of the buffer area according to the adjusted H264 encoding code rate, and repeating the steps S31-S36.
2. An equalizing coding device of multi-channel video images suitable for a carrier rocket is characterized by comprising a hardware part and a matched software part,
the hardware part includes: the system comprises an FPGA chip, a DSP processor and a plurality of paths of cameras;
the software part comprises: an H264 image equalization coding program arranged on the DSP processor; the H264 dynamic coding program adopts the equalizing coding method of the multichannel video image of the carrier rocket in claim 1;
the FPGA chip is connected with the multiple cameras to acquire video images acquired by the cameras in a multi-channel mode;
the DSP processor is connected with the FPGA chip through an EMIF, a VPIF, a GPIO and a reset pin and is used for receiving the video image of each channel; and respectively carrying out H264 image coding on the multi-channel video images by utilizing an H264 image equalization coding program.
3. The apparatus of claim 2, wherein the hardware portion comprises a FLASH register, the FLASH register is coupled to the DSP processor and stores the original video image before encoding in a multi-channel partition manner.
4. The apparatus of claim 2, wherein the hardware portion comprises a DDR register, the DDR register is externally connected to the DSP processor, and encoded data of the encoded video image is stored in time series through the DDR register.
5. The apparatus for equalized encoding of multichannel video images with a launch vehicle according to claim 2, wherein the hardware portion further comprises a clock module, the clock module is connected to the DSP processor and is configured to configure clock values that satisfy H264 encoding requirements; and is used for providing reset signals, including reset signals for power-on initialization and watchdog reset signals when work is abnormal.
6. The apparatus for equalized encoding of multiple-channel video images using a launch vehicle according to claim 2, wherein the DSP processor employs a TMS320DM6467 chip from TI corporation.
7. The apparatus for equalized encoding of multiple channel video images using a launch vehicle of claim 2 wherein the FPGA chip is XC4VLX25 chip from XILINX corporation.
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| WO2015118841A1 (en) * | 2014-02-10 | 2015-08-13 | 日本電気株式会社 | Video encoding device, video encoding method, and program |
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| CN103338375A (en) * | 2013-06-27 | 2013-10-02 | 公安部第一研究所 | Dynamic code rate allocation method based on video data importance in wideband clustered system |
| CN111107382A (en) * | 2018-10-29 | 2020-05-05 | 阿里巴巴集团控股有限公司 | Data flow control method, device and system |
| CN111209119A (en) * | 2020-01-21 | 2020-05-29 | 成都国翼电子技术有限公司 | Load balancing method for face snapshot rifle bolt |
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