CN112563151A - Overlay precision measuring method - Google Patents
Overlay precision measuring method Download PDFInfo
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- CN112563151A CN112563151A CN202110222691.XA CN202110222691A CN112563151A CN 112563151 A CN112563151 A CN 112563151A CN 202110222691 A CN202110222691 A CN 202110222691A CN 112563151 A CN112563151 A CN 112563151A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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Abstract
The invention provides a measuring method of overlay accuracy, which comprises the steps of providing a substrate, sequentially forming an interlayer dielectric layer and a metal layer on the substrate, etching the metal layer to completely expose a front layer marking pattern in the interlayer dielectric layer, then forming a current layer marking pattern on the metal layer, exposing the current layer marking pattern by the current layer marking pattern, and then measuring the overlay accuracy. According to the invention, the metal layer in the region where the front layer mark pattern is located is opened through the etching process, so that the problem that the small-size overlay mark cannot be detected or the large-size overlay mark is inaccurate in measurement due to asymmetric stress of the metal layer is solved, the overlay measurement precision of the metal layer is improved, and the product rejection risk caused by inaccurate measurement is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for measuring alignment precision.
Background
In semiconductor manufacturing, a photolithography process is developed as a core technology of each technology generation. In a standard CMOS process, tens of photolithography steps are required, and factors affecting the photolithography process error, in addition to the resolution of the photolithography machine, also have the accuracy of alignment. That is, each layer must achieve a range of alignment with the previous layer, i.e., Overlay (OVL) accuracy is required to meet design requirements.
The pattern (current layer) remaining on the photoresist after exposure and development must be aligned with the pattern (previous layer) already present on the wafer substrate to ensure proper connection between the parts of the device. Too large an alignment error is one of the main causes of short and open circuits of the device, which greatly affects the yield of the device. In the integrated circuit manufacturing process, there is a special equipment to determine the overlay error by measuring the relative position between the current layer pattern and the previous layer pattern on the wafer. Patterns on the wafer that are specifically used to measure overlay errors are overlay marks that have been placed in designated areas during mask design, usually at the edges of the exposure unit, and modified overlay marks are placed near the devices in the exposure unit. Overlay error quantitatively describes the deviation of the current layer from the previous layer along the X and Y directions, and the distribution of this deviation on the wafer surface, which is a key indicator for detecting the quality of the photolithography process, and ideally, the overlay error is zero when the patterns of the current layer and the previous layer are perfectly aligned.
In the conventional metal process, as shown in fig. 1a and 1b, an interlayer dielectric layer 101, a metal layer 102 and a photoresist layer 103 are sequentially formed on a substrate 100, and the penetration of light is weakened after metal deposition, which results in poor measurement accuracy of overlay after the pattern definition of an overlay mark 110 is completed. For small sized overlay marks 110, the overlay mark is difficult to detect due to the weak penetration of the metal layer (e.g., aluminum layer), as shown in fig. 1 a. For the large-sized overlay mark 110, due to the effect of stresses in different directions in the metal deposition process, the topography formed on the surface of the overlay mark 110 after the metal deposition process is completed usually has an asymmetric problem, as shown in fig. 1b, the asymmetric overlay mark topography may cause an error in measurement accuracy, and may affect the process compensation value fed back to the exposure machine.
At present, the overlay precision difference caused by the overlay mark morphology difference after metal deposition is mainly used for controlling the stability of the previous metal deposition process, and simultaneously monitoring the overlay data and comparison after photoetching and etching to determine the real compensation value required by the exposure process, but the monitoring method has the risk of wafer scrap caused by the overlay exceeding the specification after etching.
Disclosure of Invention
The invention aims to provide a measuring method of overlay accuracy, which is used for improving the overlay measuring accuracy of a metal layer and reducing the product rejection risk caused by inaccurate measurement.
The invention provides a measuring method of overlay accuracy, which comprises the following steps:
providing a substrate, wherein an interlayer dielectric layer and a metal layer are sequentially formed on the substrate, a front layer marking pattern is formed in the interlayer dielectric layer, and the metal layer covers the front layer marking pattern;
etching the metal layer to completely expose the front layer mark pattern;
forming a current layer marking pattern on the metal layer, the current layer marking pattern exposing the previous layer marking pattern, an
And measuring the alignment precision.
Optionally, etching the metal layer to completely expose the front layer mark pattern includes:
forming a first photoresist layer on the metal layer, patterning the first photoresist layer to form an opening at the position of the front layer mark pattern, wherein the size of the opening is larger than that of the front layer mark pattern;
etching the metal layer by taking the patterned first photoresist layer as a mask; and the number of the first and second groups,
and removing the first photoresist layer.
Optionally, forming a layer-current mark pattern on the metal layer includes:
forming a second photoresist layer on the metal layer;
and patterning the second photoresist layer to form the current layer mark pattern.
Optionally, after the measuring of the overlay accuracy, the method further includes: and etching the metal layer by using the patterned second photoresist layer.
Optionally, the forming an alignment mark pattern in the interlayer dielectric layer, and after forming the second photoresist layer on the metal layer, before forming a layer mark pattern includes: and carrying out alignment measurement on the alignment mark pattern.
Optionally, the metal layer is etched to completely expose the front layer mark pattern and completely expose the alignment mark pattern.
Optionally, the metal layer is an aluminum layer.
Optionally, tungsten layers are further formed on the inner wall and the side wall of the front layer mark pattern, and the metal layer covers the tungsten layers.
Optionally, the previous layer mark pattern and the current layer mark pattern are squares having the same center and mutually parallel sides.
Optionally, the overlay accuracy is measured by using an overlay accuracy measuring method based on image signal processing.
In summary, the overlay accuracy measuring method provided by the present invention includes providing a substrate, sequentially forming an interlayer dielectric layer and a metal layer on the substrate, etching the metal layer to completely expose a previous layer mark pattern in the interlayer dielectric layer, forming a current layer mark pattern on the metal layer, exposing the current layer mark pattern from the current layer mark pattern, and measuring the overlay accuracy. According to the invention, the metal layer in the region where the front layer mark pattern is located is opened through the etching process, so that the problem that the small-size overlay mark cannot be detected or the large-size overlay mark is inaccurate in measurement due to asymmetric stress of the metal layer is solved, the overlay measurement precision of the metal layer is improved, and the product rejection risk caused by inaccurate measurement is reduced.
Drawings
FIGS. 1a and 1b are schematic diagrams illustrating measurement of overlay marks in a metal process;
FIG. 2 is a flowchart illustrating a method for measuring overlay accuracy according to an embodiment of the present invention;
fig. 3a to 3f are schematic structural diagrams corresponding to steps of a measurement method of overlay accuracy according to an embodiment of the present invention;
wherein the reference numerals are:
100-a substrate; 101-interlayer dielectric layer; 102-a metal layer; 103-a photoresist layer; 110-overlay mark;
200-a substrate; 201-interlayer dielectric layer; 202-a metal layer; 203-a first photoresist layer; 204-a second photoresist layer; 210-a front layer marking pattern; 220-current layer marking pattern; 211-a tungsten layer; 200 a-an array region; 200 b-peripheral zone.
Detailed Description
The method for measuring overlay accuracy of the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description. Furthermore, it should be noted that the techniques of this disclosure may be implemented in hardware and/or software (including firmware, microcode, etc.).
Fig. 2 is a flowchart of the measurement method of overlay accuracy according to the present embodiment, and referring to fig. 2, the measurement method of overlay accuracy according to the present embodiment includes:
s01: providing a substrate, wherein an interlayer dielectric layer and a metal layer are sequentially formed on the substrate, a front layer marking pattern is formed in the interlayer dielectric layer, and the metal layer covers the front layer marking pattern;
s02: etching the metal layer to completely expose the front layer mark pattern;
s03: forming a current layer marking pattern on the metal layer, the current layer marking pattern exposing the previous layer marking pattern, an
S04: and measuring the alignment precision.
Fig. 3a to 3f are schematic structural diagrams corresponding to steps of the alignment precision measurement method provided in this embodiment. The method for measuring the overlay accuracy according to the present embodiment will be described in detail with reference to fig. 2 and fig. 3a to 3 f.
First, referring to fig. 3a, step S01 is executed to provide a substrate 200, where an interlayer dielectric layer 201 and a metal layer 202 are sequentially formed on the substrate 200, a front layer mark pattern 210 is formed in the interlayer dielectric layer 201, and the metal layer 202 covers the front layer mark pattern 210.
The substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. The substrate 200 includes an array region 200a and a peripheral region 200b, the array region 200a is a chip region, such as a memory array region, and the peripheral region 200b is a scribe line region disposed between two chip regions. The array region 200a is used for manufacturing chips, and the peripheral region 200b is used for manufacturing marks (e.g., overlay marks, alignment marks) or Test keys (Test keys). It should be noted that, the present embodiment mainly provides a measurement method of overlay accuracy for convenience of subsequent description, and the corresponding drawing only shows a part of the substrate, and other structures and devices on the substrate are omitted, but those skilled in the art should know how to implement the present invention according to the disclosure of the present invention and the common general knowledge of those skilled in the art.
The material of the interlayer dielectric layer 201 includes, but is not limited to, silicon dioxide, silicon nitride, TEOS, etc. The metal layer 202 is, for example, aluminum metal. In the array region 200a, a contact via (not shown) is formed in the interlayer dielectric layer 201, and the contact via is filled with metal tungsten. A front layer mark pattern 210 is formed in the interlayer dielectric layer 201 in the peripheral region 200b, a tungsten layer 211 is further formed on the inner wall and the side wall of the front layer mark pattern 210, and the tungsten layer 211 is covered by the metal layer 202. The overlay mark used In this embodiment is a general overlay mark bib (Box In Box or Bar In Bar), the outer Box or Bar is left during the previous layer photolithography step, and the inner Box or Bar exposes a pattern during the current layer photolithography step. And obtaining corresponding overlay accuracy by measuring the offset of the centers of the overlay mark of the previous layer and the current layer. The front layer mark pattern 210 is an outer Box or Bar formed by a front layer photolithography step. The two recesses formed in the interlayer dielectric layer 201 in the peripheral region 200b of fig. 3a can be seen as cross-sectional views of two opposite sides of the outer face Box or Bar. For example, the previous layer mark pattern 210 and the next layer mark pattern 220 are squares having the same center and parallel sides.
Next, referring to fig. 3a to 3c, step S02 is performed to etch the metal layer 202 to completely expose the front layer mark pattern 210.
Specifically, first, a first photoresist layer 203 is formed on the metal layer 202, and the first photoresist layer 203 is patterned to form an opening at the position of the front layer mark pattern 210, where the size of the opening is larger than the size of the front layer mark pattern 210, as shown in fig. 3 a; then, the metal layer 202 is etched by using the patterned first photoresist layer 203 as a mask to completely expose the front layer mark pattern 210, as shown in fig. 3 b; and removing the first photoresist layer 203, as shown in fig. 3 c.
Next, referring to fig. 3d and fig. 3e, step S03 is executed to form a current-layer mark pattern 220 on the metal layer 202, wherein the current-layer mark pattern 220 exposes the previous-layer mark pattern 210. Specifically, a second photoresist layer 204 is formed on the metal layer 202, and then the second photoresist layer 204 is patterned to form the current layer mark pattern 220. That is, the Box or Bar inside the overlay mark BIB in the layer mark pattern 220 is exposed during the layer lithography step, and the photoresist columns formed on the metal layer 202 in the peripheral region 200b in fig. 3e can be regarded as the cross-sectional views of the opposite sides of the Box or Bar inside.
In this embodiment, an Alignment mark pattern (Alignment mark) is further formed in the interlayer dielectric layer 201, and in the process of etching the metal layer 202 to completely expose the front layer mark pattern 210, the metal layer 202 on the Alignment mark pattern is simultaneously etched to completely expose the Alignment mark. Thus, after the second photoresist layer 204 is formed on the metal layer 202, the alignment mark pattern may be measured before the layer mark pattern 220 is formed. Since the metal layer 202 is etched to expose the alignment mark pattern completely, even for the small-sized alignment mark pattern, the alignment mark pattern is not covered by the weak-penetrability metal layer, so that the alignment mark pattern is easy to detect, and the alignment precision is improved. Good alignment accuracy in turn further improves the accuracy of subsequent overlay mark measurements. In this embodiment, the alignment mark pattern and the front layer mark pattern 210 may be the same pattern mark, or may be different pattern marks respectively disposed in the scribe line region, which is not limited in the present invention.
Subsequently, step S04 is executed to measure the overlay accuracy. For example, an overlay accuracy measurement method (IBO) based on image signal processing is used to measure the overlay accuracy, and the corresponding overlay accuracy is obtained by measuring the offset between the centers of the previous layer mark and the current layer mark. In the embodiment, a photoetching process is added after metal deposition is finished, the metal layer in the area where the front layer mark pattern 210 is located is etched by photoetching and etching methods, and subsequent measurement of overlay marks is performed after the front layer mark pattern 210 is exposed, so that the measurement precision of overlay alignment after the definition of the front layer mark pattern is finished due to weakened penetrability of light after metal deposition is avoided from being deteriorated, the measurement precision of high-metal layer overlay is reduced, and the product rejection risk caused by inaccurate measurement is reduced.
In this embodiment, after the alignment precision measurement, the metal layer 202 is etched by the patterned second photoresist layer 204, as shown in fig. 3 f.
It should be noted that, in the process of patterning the second photoresist layer 204 to form the current-layer mark pattern 220, only the photoresist patterns corresponding to two opposite sides of the inner Box or Bar need to be formed on the metal layer 202 in the peripheral region 200b, and other patterning schemes may also be adopted for patterning the second photoresist layer 204, for example, the second photoresist layer 204 is correspondingly retained in the peripheral region of the previous-layer mark pattern 210 in the peripheral region 200 b.
In summary, the present invention provides a method for measuring overlay accuracy, which includes providing a substrate, sequentially forming an interlayer dielectric layer and a metal layer on the substrate, etching the metal layer to completely expose a front layer mark pattern in the interlayer dielectric layer, forming a current layer mark pattern on the metal layer, exposing the front layer mark pattern from the current layer mark pattern, and measuring the overlay accuracy. According to the invention, the metal layer in the region where the front layer mark pattern is located is opened through the etching process, so that the problem that the small-size overlay mark cannot be detected or the large-size overlay mark is inaccurate in measurement due to asymmetric stress of the metal layer is solved, the overlay measurement precision of the metal layer is improved, and the product rejection risk caused by inaccurate measurement is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A method for measuring overlay accuracy is characterized by comprising the following steps:
providing a substrate, wherein an interlayer dielectric layer and a metal layer are sequentially formed on the substrate, a front layer marking pattern is formed in the interlayer dielectric layer, and the metal layer covers the front layer marking pattern;
etching the metal layer to completely expose the front layer mark pattern;
forming a current layer mark pattern on the metal layer, the current layer mark pattern exposing the previous layer mark pattern, and,
measuring the overlay precision;
wherein forming a layer-as-layer marker pattern on the metal layer comprises:
forming a second photoresist layer on the metal layer; and the number of the first and second groups,
patterning the second photoresist layer to form the current layer mark pattern;
and an alignment mark pattern is also formed in the interlayer dielectric layer, and after the second photoresist layer is formed on the metal layer, the forming of the current layer mark pattern comprises the following steps: and carrying out alignment measurement on the alignment mark pattern.
2. The overlay accuracy measuring method of claim 1, wherein etching the metal layer to completely expose the front layer mark pattern comprises:
forming a first photoresist layer on the metal layer, patterning the first photoresist layer to form an opening at the position of the front layer mark pattern, wherein the size of the opening is larger than that of the front layer mark pattern;
etching the metal layer by taking the patterned first photoresist layer as a mask; and the number of the first and second groups,
and removing the first photoresist layer.
3. The overlay accuracy measuring method of claim 1, further comprising, after the overlay accuracy measurement: and etching the metal layer by taking the patterned second photoresist layer as a mask.
4. The overlay accuracy measuring method of claim 3, wherein the metal layer is etched to completely expose the front layer mark pattern and completely expose the alignment mark pattern.
5. A method for measuring overlay accuracy as recited in claim 1, wherein said metal layer is an aluminum layer.
6. A method for measuring overlay accuracy as claimed in claim 1, wherein a tungsten layer is further formed on an inner wall and a sidewall of the front layer mark pattern, and the metal layer covers the tungsten layer.
7. A method for measuring overlay accuracy according to claim 1, wherein the previous layer mark pattern and the current layer mark pattern are squares having the same center and parallel sides.
8. The overlay accuracy measuring method of claim 1, wherein the overlay accuracy is measured by an overlay accuracy measuring method based on image signal processing.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115877672A (en) * | 2023-01-09 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Overlay accuracy acquisition method and correction method |
| CN117826547A (en) * | 2024-03-05 | 2024-04-05 | 合肥晶合集成电路股份有限公司 | Overlay detection method |
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| CN1567532A (en) * | 2003-07-03 | 2005-01-19 | 旺宏电子股份有限公司 | Structure of superposition mark and method for forming same |
| US20070246843A1 (en) * | 2006-04-25 | 2007-10-25 | Macronix International Co., Ltd. | Pattern registration mark designs for use in photolithography and methods of using the same |
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2021
- 2021-03-01 CN CN202110222691.XA patent/CN112563151A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567532A (en) * | 2003-07-03 | 2005-01-19 | 旺宏电子股份有限公司 | Structure of superposition mark and method for forming same |
| US20070246843A1 (en) * | 2006-04-25 | 2007-10-25 | Macronix International Co., Ltd. | Pattern registration mark designs for use in photolithography and methods of using the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115877672A (en) * | 2023-01-09 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Overlay accuracy acquisition method and correction method |
| CN115877672B (en) * | 2023-01-09 | 2023-06-02 | 合肥晶合集成电路股份有限公司 | Overlay accuracy acquisition method and correction method |
| CN117826547A (en) * | 2024-03-05 | 2024-04-05 | 合肥晶合集成电路股份有限公司 | Overlay detection method |
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Application publication date: 20210326 |