CN112563131A - Preparation method of metal gate device - Google Patents
Preparation method of metal gate device Download PDFInfo
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- CN112563131A CN112563131A CN202011461041.2A CN202011461041A CN112563131A CN 112563131 A CN112563131 A CN 112563131A CN 202011461041 A CN202011461041 A CN 202011461041A CN 112563131 A CN112563131 A CN 112563131A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a preparation method of a metal gate device, which is characterized in that a first opening is formed in a pseudo gate layer of a second area, and an extension line of one side wall of the first opening is aligned with an intersection line of the first area and the second area; forming a first sacrificial layer and a second sacrificial layer filling the first opening on the dummy gate layer; etching the first sacrificial layer and the pseudo gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; and forming a first gate structure in the second opening. According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that the etching defect of the side wall of the pseudo gate layer of the second region is avoided in the process of removing the pseudo gate layer of the first region by adopting a wet etching process, and meanwhile, the damage of the dry etching process to the gate dielectric layer is also avoided, and the method has a remarkable significance.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation method of a metal gate device.
Background
For half a century driven by moore's law, the number of transistors that can be accommodated in an integrated circuitThe amount doubles every 18 months and the transistor size shrinks accordingly. With the continuous reduction of the transistor characteristic dimension in CMOS circuit, the gate dielectric SiO2The thickness of (2) is also continuously reduced, and an insulating layer SiO in the transistor2Has reached a physical limit of about 10A, SiO 2nm or less2Is no longer an ideal insulator, obvious tunneling leakage occurs, and the leakage current increases exponentially with decreasing thickness, below 1nm of SiO2The leakage of (A) can be unacceptably large, and therefore High-K/Metal Gate (HKMG) technology is enabled in High performance processes.
The HKMG technology refers to high-k gate dielectric + metal gate electrode stack technology, wherein the high-k gate dielectric technology is realized by replacing SiO with high-dielectric-constant dielectric2As a gate dielectric layer, a high dielectric constant dielectric has a K value compared to SiO2The dielectric is about 6 times higher, and the physical thickness of the dielectric can be SiO under the same voltage and electric field intensity2The dielectric layer is 6 times of the dielectric layer, so that the process difficulty of the high-quality dielectric layer is reduced, the electric leakage caused by quantum tunneling effect is reduced, and the grid electric leakage of the semiconductor device is greatly reduced.
The Metal gate technology refers to a Metal gate technology, and because the work function of a high-k gate dielectric material is not matched with that of a traditional polysilicon gate material, if the polysilicon gate is continuously used, the Fermi level pinning phenomenon of the gate can occur, so that the work function of the gate material can not be adjusted, a new gate material needs to be replaced, and the Metal electrode is an ideal solution for replacing polysilicon.
The forming process of the conventional metal gate comprises the process steps of deposition and removal of a pseudo gate layer, formation of the metal gate and the like, the pseudo gate layer needs to be removed before the metal gate is prepared, and the conventional method for removing the pseudo gate layer comprises a mode of combining dry etching, wet etching or a dry humidifying method, but the three methods have respective defects in the implementation process.
Fig. 1 is a cross-sectional view of a PMOS region after a dummy gate layer is removed by a dry etching process, and the dry etching plasma damages a gate oxide layer above an active region, thereby causing degradation of device characteristics and failure of reliability.
FIG. 2 is a cross-sectional view of a PMOS region dummy gate layer removed by a wet etching process, wherein due to isotropic characteristics of the wet etching, the NMOS region dummy gate layer is simultaneously eroded to form an arc-shaped defect of the NMOS dummy gate layer, which causes subsequent intrusion of a PMOS metal gate into the NMOS region and causes failure of an MOS device; meanwhile, the arc-shaped side wall of the pseudo gate layer causes the discontinuity of the subsequent metal gate barrier layer deposition and the diffusion of metal elements, and also causes the degradation of device characteristics and the failure of reliability.
Fig. 3 is a cross-sectional view of a PMOS region dummy gate layer removed by using a dry process and then a wet process, which can avoid damage to the gate oxide layer by dry-etched plasma, but the wet process can cause an inscribed morphology at the bottom of the dummy gate layer, thereby causing discontinuity of subsequent metal gate barrier layer deposition and diffusion of metal elements, and finally causing degradation of device characteristics and failure of reliability.
Therefore, a method for forming a metal gate device is needed, which can avoid damage to the gate oxide layer when removing the dummy gate layer in the PMOS region, and simultaneously, the sidewall of the remaining dummy gate layer in the NMOS region is steep, so as to prevent the PMOS metal gate from invading the NMOS region and ensure the continuity of the metal gate barrier layer deposited subsequently, thereby improving the device performance and reliability.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a preparation method of a metal gate device, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area adjacent to the first area;
forming a shallow trench isolation structure in the substrate;
forming a gate dielectric layer covering the shallow trench isolation structure on the substrate;
forming a pseudo gate layer on the gate dielectric layer;
forming a first opening in the dummy gate layer of the second region, wherein an extension line of a side wall of the first opening is aligned with a cross-over line of the first region and the second region;
forming a first sacrificial layer and a second sacrificial layer filling the first opening on the dummy gate layer;
etching the first sacrificial layer and the pseudo gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer;
forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer;
removing the second sacrificial layer and the first sacrificial layer of the second region;
etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening is exposed out of the side wall of the first gate structure;
and forming a second grid structure in the third opening, wherein the second grid structure is adjacent to the first grid structure, and the top surface of the second grid structure is flush with the top surface of the first grid structure.
Preferably, the material of the dummy gate layer comprises polysilicon, and the material of the first sacrificial layer comprises one or more of silicon nitride, silicon oxynitride, titanium nitride and tantalum nitride.
Preferably, the material of the second sacrificial layer comprises one or more of silicon nitride, silicon oxynitride, titanium nitride and tantalum nitride.
Preferably, the gate dielectric layer comprises a gate oxide layer and a barrier layer located on the gate oxide layer, and the material of the gate oxide layer comprises one or more combinations of silicon dioxide, silicon oxynitride, hafnium oxide and aluminum oxide.
Preferably, the first opening is formed by a first etching process, and the first etching process includes anisotropic dry etching.
Preferably, the first sacrificial layer of the first region is etched by using a second etching process, where the second etching process includes one or a combination of dry etching and wet etching.
Preferably, the dummy gate layer of the first region is etched by using a third etching process, and the third etching process includes wet etching.
Preferably, the first gate structure includes a first diffusion barrier layer located on a sidewall and a bottom of the second opening, a first work function layer located on the first diffusion barrier layer, and a first electrode layer located on the first work function layer.
Preferably, the second sacrificial layer and the first sacrificial layer of the second region are removed by a fourth etching process, and the fourth etching process includes wet etching.
Preferably, the first region is an NMOS region, and the second region is a PMOS region; or, the first region is a PMOS region, and the second region is an NMOS region.
According to the technical scheme, the invention provides the preparation method of the metal gate device, the first opening is formed in the pseudo gate layer of the second area, and the extension line of the side wall of one side of the first opening is aligned with the intersection line of the first area and the second area; forming a first sacrificial layer and a second sacrificial layer filling the first opening on the dummy gate layer; etching the first sacrificial layer and the pseudo gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer; removing the second sacrificial layer and the first sacrificial layer of the second region; etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening is exposed out of the side wall of the first gate structure; and forming a second grid structure in the third opening, wherein the second grid structure is adjacent to the first grid structure, and the top surface of the second grid structure is flush with the top surface of the first grid structure.
According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that the etching defect of the side wall of the pseudo gate layer of the second region caused by isotropic etching is avoided in the process of removing the pseudo gate layer of the first region by adopting a wet etching process, and meanwhile, the damage of the dry etching process to the gate dielectric layer is also avoided because the wet etching process is adopted. In addition, after the second sacrificial layer is removed, the side wall of the pseudo gate layer of the second region is steep, so that the first electrode layer of the first region is prevented from invading the second region, the continuity of the side wall of the first diffusion barrier layer deposited subsequently is ensured, the purpose of improving the performance and the reliability of the device is achieved, and the method has obvious significance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a cross-sectional view of a device after a dummy gate layer in a PMOS region is removed by a dry etching process
FIG. 2 is a cross-sectional view of the device after the dummy gate layer in the PMOS region is removed by a wet etching process
FIG. 3 is a cross-sectional view of the device after removing the dummy gate layer in the PMOS region by a dry-first wet-second process
Fig. 4 to 14 are schematic structural diagrams illustrating a manufacturing process of a metal gate device according to an embodiment of the invention
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In order to make the objects, technical solutions and advantages of the present invention more clear, the following further shows a schematic structural diagram of a manufacturing process of a metal gate device according to an embodiment of the present invention with reference to fig. 4 to 14.
Referring to fig. 4, a substrate is provided, the substrate including a first region and a second region adjacent to the first region.
In the present embodiment, a substrate 100 is provided, and the substrate 100 includes a first region I and a second region II adjacent to the first region I. The substrate 100 is one of a silicon substrate, a silicon-on-insulator substrate, and a silicon germanium substrate, and the first region I and the second region II are adjacent to each other. In the following processes, an NMOS transistor is formed in the first region I, a PMOS transistor is formed in the second region II, in other embodiments, a PMOS transistor is formed in the first region I, and an NMOS transistor is formed in the second region II, and the number and the position of the first region I and the second region II should not limit the scope of the present invention excessively. In this embodiment, taking the MOS device structure using the silicon substrate and the forming method as an example, the cross-sectional view of the process flow only describes the process related to the present invention, and the conventional process flows related to the remaining devices, such as well implantation, source-drain implantation, and sidewall etching, are not shown in the flow chart.
Referring to fig. 5, a shallow trench isolation structure 120 is formed in the substrate 100.
In the present embodiment, the shallow trench isolation structure 120 includes a first trench isolation region located in the first region I and a second trench isolation region located in the second region II and adjacent to the first trench isolation region. In one embodiment, the shallow trench isolation structure 120 is used to electrically isolate the polysilicon resistor, which is subsequently formed on the surface thereof, from the substrate 100 and other devices. In other embodiments, the shallow trench isolation structure 120 is further formed around the substrate of the first region i for electrically isolating different MOS transistors.
Referring to fig. 6, a gate dielectric layer 130 covering the shallow trench isolation structure 120 is formed on the substrate 100.
In this embodiment, the gate dielectric layer 130 is a composite layer, the composite layer includes a gate oxide layer (not shown) and a barrier layer (not shown) on the gate oxide layer, and the material of the gate oxide layer includes silicon dioxide and oxynitrideOne or more of silicon oxide, hafnium oxide and aluminum oxide. In an embodiment, the substrate 100 is a silicon substrate, the gate oxide layer is made of silicon dioxide, and the gate oxide layer is formed on the surface of the silicon substrate by using a thermal oxidation process. In another embodiment, the gate dielectric layer 130 is a high-K gate dielectric material, and the high-K gate dielectric material includes hafnium oxide (HfO)2) One or more of hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and the like. The forming process of the gate dielectric layer 130 includes one or two of an atomic layer deposition process and magnetron sputtering.
Referring to fig. 7, a dummy gate layer 140 is formed on the gate dielectric layer 130.
In this embodiment, the material of the dummy gate layer 140 includes polysilicon. The forming process of the dummy gate layer 140 includes one of a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, or an epitaxial growth process. The process steps for forming the dummy gate layer 140 include: a polysilicon layer is formed on the substrate 100 and then etched, leaving only the dummy gate layer 140 above the first region i and the second region ii.
Referring to fig. 8, a first opening 101 is formed in the dummy gate layer 140 of the second region II, and an extension line of a sidewall of the first opening 101 is aligned with an intersection line of the first region I and the second region II.
In this embodiment, a photoresist is coated on the dummy gate layer 140 in the second region II, then a pattern and a position of the first opening 101 are defined on the dummy gate layer 140 in the second region II through a photolithography process, then the first opening 101 is formed through a first etching process, and finally the photoresist is removed. The first etching process includes anisotropic dry etching. An extension line of a side wall of the first opening 101 is aligned with an intersection line of the first region I and the second region II, so that an extension line of a side wall of a second sacrificial layer subsequently filling the first opening 101 is aligned with an intersection line of the first region I and the second region II.
Referring to fig. 9, a first sacrificial layer 151 and a second sacrificial layer 152 filling the first opening 101 (not shown) are formed on the dummy gate layer 140.
The material of the first sacrificial layer 151 includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride. The material of the second sacrificial layer 152 includes one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride. In this embodiment, the second sacrificial layer 152 is formed at the boundary between the PMOS region and the NMOS region, so that during the subsequent wet etching process to remove the dummy gate layer 140, the etching angle defect caused by isotropic etching is avoided, and the damage of the etching process to the gate dielectric layer 130 is also avoided.
In this embodiment, the first sacrificial layer 151 and the second sacrificial layer 152 are simultaneously formed by a deposition process, and the materials of the first sacrificial layer 151 and the second sacrificial layer 152 are the same. In another embodiment, the second sacrificial layer 152 filling the first opening is formed first, then the surface of the dummy gate layer 140 is exposed by a grinding process, and then the first sacrificial layer 151 is formed on the dummy gate layer 140, so that on one hand, the filling rate of the first opening 101 is ensured, no void or other defects are ensured, and simultaneously, the flatness of the first sacrificial layer 151 is ensured, and the difficulty of the subsequent etching process is reduced.
Referring to fig. 10, the first sacrificial layer 151 and the dummy gate layer 140 in the first region I are etched to form a second opening (not shown), and a sidewall of the second opening exposes the second sacrificial layer 152.
And etching the first sacrificial layer 151 of the first region I by using a second etching process, wherein the second etching process comprises one or two of dry etching and wet etching. And etching the pseudo gate layer 140 of the first region I by adopting a third etching process, wherein the third etching process comprises wet etching. The second sacrificial layer 152 forms a sidewall barrier layer of the dummy gate layer 140 in the second region II, so that when the first gate structure is formed in the subsequent second opening, the first electrode layer in the first region is prevented from invading the second region, and the continuity of the sidewall of the subsequently deposited first diffusion barrier layer is ensured.
Referring to fig. 11, a first gate structure (not shown) is formed in the second opening, and a top surface of the first gate structure is flush with a surface of the first sacrificial layer 151.
The first gate structure includes a first diffusion barrier layer 170 on the sidewall and bottom of the second opening, a first work function layer 171 on the first diffusion barrier layer 170, and a first electrode layer 172 on the first work function layer 171. In the present embodiment, the material of the first diffusion barrier layer 170 includes hafnium oxide (HfO)2) One or more combinations of hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and the like, the material of the first work function layer 171 is one or more combinations of Ti, Ta, TiN, TaN, TiAl, TaC, and TaSiN, and the material of the first electrode layer 172 is one or more combinations of Al, Cu, Ag, Au, Pt, and Ni. The first diffusion barrier layer 170 is used to block diffusion of the material of the first electrode layer 172. By adjusting the material and thickness of the first work function layer 171, the work function of the first gate structure may be changed.
Referring to fig. 12, the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II are removed.
And removing the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II by using a fourth etching process, wherein the fourth etching process comprises one or a combination of wet etching and dry etching. In the embodiment of the present invention, the materials of the first sacrificial layer 151 and the second sacrificial layer 152 are the same, so that the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II can be removed simultaneously by using the fourth etching process, and in order to avoid etching residues in the actual process, the second sacrificial layer 152 and the first sacrificial layer 151 of the second region II are removed by wet etching first, and then further etching is performed, so that the second sacrificial layer 152 and the first sacrificial layer 151 can be completely removed. In another embodiment, the second sacrificial layer 152 is removed by wet etching, and then the first sacrificial layer 151 in the second region II is removed by wet etching.
Referring to fig. 13, the dummy gate layer 140 in the second region II is etched to form a third opening (not shown), and a sidewall of the third opening exposes a sidewall of the first gate structure 161.
The process for etching the dummy gate layer 140 in the second region II includes one or a combination of a dry etching process and a wet etching process. In this embodiment, the dummy gate layer 140 in the second region II is wet etched by using a tetramethylammonium hydroxide (TMAH) solution to form a third opening.
Referring to fig. 14, a second gate structure is formed in the third opening, the second gate structure is adjacent to the first gate structure, and a top surface of the second gate structure is flush with a top surface of the first gate structure.
The second gate structure includes a second diffusion barrier layer 180 on sidewalls and a bottom of the third opening, a second work function layer 181 on the second diffusion barrier layer 180, and a second electrode layer 182 on the second work function layer 181. In the present embodiment, the material of the second diffusion barrier layer 180 includes hafnium oxide (HfO)2) One or more combinations of hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and the like, the material of the first work function layer 181 is one or more combinations of Ti, Ta, TiN, TaN, TiAl, TaC, and TaSiN, and the material of the second electrode layer 182 is one or more combinations of Al, Cu, Ag, Au, Pt, and Ni. The second diffusion barrier layer 180 serves to block diffusion of the material of the first electrode layer 182. By adjusting the material and thickness of the second work function layer 181, the work function of the first gate structure may be changed.
Compared with the prior art, the invention provides a preparation method of a metal gate device, which is characterized in that a first opening is formed in a pseudo gate layer of a second area, and an extension line of one side wall of the first opening is aligned with an intersection line of the first area and the second area; forming a first sacrificial layer and a second sacrificial layer filling the first opening on the dummy gate layer; etching the first sacrificial layer and the pseudo gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer; forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer; removing the second sacrificial layer and the first sacrificial layer of the second region; etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening is exposed out of the side wall of the first gate structure; and forming a second grid structure in the third opening, wherein the second grid structure is adjacent to the first grid structure, and the top surface of the second grid structure is flush with the top surface of the first grid structure.
According to the invention, the second sacrificial layer is formed at the junction of the first region and the second region and is used as the side wall barrier layer, so that the etching defect of the side wall of the pseudo gate layer of the second region caused by isotropic etching is avoided in the process of removing the pseudo gate layer of the first region by adopting a wet etching process, and meanwhile, the damage of the dry etching process to the gate dielectric layer is also avoided because the wet etching process is adopted. In addition, after the second sacrificial layer is removed, the side wall of the pseudo gate layer of the second region is steep, so that the first electrode layer of the first region is prevented from invading the second region, the continuity of the side wall of the first diffusion barrier layer deposited subsequently is ensured, the purpose of improving the performance and the reliability of the device is achieved, and the method has obvious significance.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a metal gate device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area adjacent to the first area;
forming a shallow trench isolation structure in the substrate;
forming a gate dielectric layer covering the shallow trench isolation structure on the substrate;
forming a pseudo gate layer on the gate dielectric layer;
forming a first opening in the dummy gate layer of the second region, wherein an extension line of a side wall of the first opening is aligned with a cross-over line of the first region and the second region;
forming a first sacrificial layer and a second sacrificial layer filling the first opening on the dummy gate layer;
etching the first sacrificial layer and the pseudo gate layer of the first region to form a second opening, wherein the side wall of the second opening exposes the second sacrificial layer;
forming a first gate structure in the second opening, wherein the top surface of the first gate structure is flush with the surface of the first sacrificial layer;
removing the second sacrificial layer and the first sacrificial layer of the second region;
etching the pseudo gate layer of the second region to form a third opening, wherein the side wall of the third opening is exposed out of the side wall of the first gate structure;
and forming a second grid structure in the third opening, wherein the second grid structure is adjacent to the first grid structure, and the top surface of the second grid structure is flush with the top surface of the first grid structure.
2. The method of claim 1, wherein the material of the dummy gate layer comprises polysilicon, and the material of the first sacrificial layer comprises one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride.
3. The method of claim 1, wherein the material of the second sacrificial layer comprises one or more of silicon nitride, silicon oxynitride, titanium nitride, and tantalum nitride.
4. The method of claim 1, wherein the gate dielectric layer comprises a gate oxide layer and a barrier layer on the gate oxide layer, and the gate oxide layer is made of a material comprising one or more of silicon dioxide, silicon oxynitride, hafnium oxide, and aluminum oxide.
5. The method of claim 1, wherein the first opening is formed using a first etching process, the first etching process comprising anisotropic dry etching.
6. The method of claim 1, wherein the first sacrificial layer of the first region is etched using a second etching process, wherein the second etching process comprises one or a combination of dry etching and wet etching.
7. The method of claim 1, wherein the dummy gate layer of the first region is etched using a third etching process, the third etching process comprising a wet etch.
8. The method of claim 1, wherein the first gate structure comprises a first diffusion barrier layer on sidewalls and a bottom of the second opening, a first work function layer on the first diffusion barrier layer, and a first electrode layer on the first work function layer.
9. The method of claim 1, wherein the second sacrificial layer and the first sacrificial layer of the second region are removed by a fourth etching process, and the fourth etching process comprises wet etching.
10. The method of claim 1, wherein the first region is an NMOS region and the second region is a PMOS region; or, the first region is a PMOS region, and the second region is an NMOS region.
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