CN112563128A - Technological method for improving routing success rate of chip Al electrode - Google Patents
Technological method for improving routing success rate of chip Al electrode Download PDFInfo
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- CN112563128A CN112563128A CN202011432721.1A CN202011432721A CN112563128A CN 112563128 A CN112563128 A CN 112563128A CN 202011432721 A CN202011432721 A CN 202011432721A CN 112563128 A CN112563128 A CN 112563128A
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- tin
- layer
- chip
- electrode
- depositing
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- 238000000034 method Methods 0.000 title claims abstract description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 44
- 238000000151 deposition Methods 0.000 claims abstract description 25
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 6
- 239000000956 alloy Substances 0.000 abstract description 6
- 238000001953 recrystallisation Methods 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 239000013077 target material Substances 0.000 abstract description 3
- 229910052718 tin Inorganic materials 0.000 description 65
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
Abstract
The invention relates to a process method for improving the routing success rate of a chip Al electrode, which comprises the following steps: starting magnetron sputtering equipment to deposit TiN, wherein nitrogen for forming TiN is reserved in a second cavity for depositing Ti and TiN, and a TiN film is remained on the surface of the Ti target material; the method comprises the steps of depositing an Al layer, a Ti layer and a TiN layer on a chip in sequence, annealing, depositing a passivation layer, and etching to obtain the chip with the pockmarked Al electrode, wherein a layer of TiN is formed between the Al layer and the Ti layer, so that when annealing is avoided, Al and Ti are contacted to form alloy to obstruct stress release and recrystallization of Al, the obtained Al electrode has pockmarks, and the wire bonding is not easy to fall off due to the fact that the pockmarks are of rugged structures, thereby being beneficial to the success rate of subsequent wire bonding.
Description
Technical Field
The invention relates to a process method for improving the routing success rate of a chip Al electrode, belonging to the technical field of semiconductors.
Background
In the MEMS process, an Al electrode is used as a medium for connecting a multilayer film circuit in a chip, when metal Al is annealed, stress is released, grain boundaries are diffused to enable grains to grow, and grains are extruded to form pits. The pits are uneven structures, so that the success rate of subsequent routing is facilitated, but in the Al/Ti/TiN film layer structure, Ti and Al can form alloy during annealing, stress release and recrystallization of Al are hindered, so that no pits exist on the surface of Al, the surface of the formed TiAl alloy is smooth, subsequent routing is not facilitated, and the routed wire is easy to fall off. When the chip product is produced in a mass production mode, due to the existence of the Al/Ti/TiN film layer structure, a pockmark-free Al electrode can appear, so that metal Al routing is abnormal, and the time and the cost are wasted.
Disclosure of Invention
The invention aims to provide a process method for improving the routing success rate of a chip Al electrode, wherein the prepared Al electrode has pits on the surface, the routing success rate is high, the product yield is high, and the cost is saved.
In order to achieve the purpose, the invention provides the following technical scheme: a process method for improving routing success rate of chip Al electrodes comprises the following steps:
s1, providing magnetron sputtering equipment, wherein the magnetron sputtering equipment comprises a first cavity for depositing Al and a second cavity for depositing Ti and TiN, starting the magnetron sputtering equipment to deposit TiN, and retaining nitrogen for forming TiN in the second cavity and leaving a TiN film on the surface of the Ti target;
s2, providing a chip, and depositing an Al layer, a Ti layer and a TiN layer on the chip in sequence by using the magnetron sputtering equipment to obtain an Al/TiN/Ti/TiN layer on the chip by deposition;
s3, annealing the chip on which the Al/TiN/Ti/TiN layer is deposited;
s4, depositing a passivation layer on the Al/TiN/Ti/TiN layer;
s5, etching the passivation layer and the TiN/Ti/TiN layer to obtain a chip with a pocked Al electrode;
and S6, repeating the steps S2 to S5, and producing the chips with the pocked Al electrodes in batches.
And further, routing and packaging the Al electrode to obtain the device.
Further, the passivation layer is made of any one of silicon nitride, silicon oxynitride or silicon oxide.
The invention has the beneficial effects that: the invention discloses a process method for improving the routing success rate of a chip Al electrode, which is characterized in that when Al/Ti/TiN is deposited on a chip, a layer of TiN is formed between an Al layer and a Ti layer, and the problem that alloy is formed by the contact of Al and Ti during annealing to obstruct the stress release and recrystallization of Al is avoided, so that the obtained Al electrode has pits, and the routing is not easy to fall off due to the fact that the pits are of uneven structures, thereby being beneficial to the success rate of subsequent routing.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a schematic structural view of an Al/TiN/Ti/TiN layer;
FIG. 2 is an optical microscope photograph of an Al electrode obtained with an Al/Ti/TiN layer;
FIG. 3 is an optical microscopic view of an Al electrode obtained from the Al/TiN/Ti/TiN layer.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention discloses a process method for improving the routing success rate of a chip Al electrode, which comprises the following steps:
s1, providing magnetron sputtering equipment, wherein the magnetron sputtering equipment comprises a first cavity for depositing Al and a second cavity for depositing Ti and TiN, starting the magnetron sputtering equipment to deposit TiN, and reserving nitrogen for forming TiN in the second cavity and reserving a TiN film on the surface of the Ti target;
s2, providing a chip, and depositing an Al layer, a Ti layer and a TiN layer on the chip in sequence by using magnetron sputtering equipment to obtain an Al/TiN/Ti/TiN layer on the chip by deposition;
s3, annealing the chip deposited with the Al/TiN/Ti/TiN layer;
s4, depositing a passivation layer on the Al/TiN/Ti/TiN layer;
s5, etching the passivation layer and the TiN/Ti/TiN layer to obtain a chip with a pockmarked Al electrode;
and S6, repeating the steps S2 to S5, and producing the chips with the pocked Al electrodes in batches.
And (5) routing and packaging the Al electrode to obtain the device. The passivation layer is made of any one of silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto, and the passivation layer may also be made of other materials, which are not listed here. A method for depositing Al, Ti and TiN by magnetron sputtering and annealing conditions. The deposition of the passivation layer, the etching of the passivation layer and the TiN/Ti/TiN layer are prior art and will not be described herein.
Referring to fig. 1, the Al/TiN/Ti/TiN layer has a four-layer structure, and the Al layer 1, the TiN layer 2, the Ti layer 3, and the TiN layer 4 are sequentially stacked. When Al, Ti and TiN are deposited by magnetron sputtering, the magnetron sputtering equipment is started to deposit TiN firstly, so that nitrogen for forming TiN is reserved in the second cavity for depositing Ti and TiN, and a TiN film is remained on the surface of the Ti target. When preparing an electrode on a chip, firstly depositing an Al layer on the chip in a first cavity, then transferring the chip deposited with the Al layer to a second cavity, firstly depositing Ti, but forming a thin TiN layer on the Al layer because some nitrogen for forming TiN is reserved in the second cavity and a TiN film is remained on the surface of a Ti target material, only depositing a Ti layer after the nitrogen and the TiN film remained on the surface of the Ti target material are consumed, and then continuously depositing TiN to obtain the Al/TiN/Ti/TiN layer structure.
It should be noted that, when preparing the first chip electrode, the magnetron sputtering equipment needs to be operated firstly, the second cavity retains nitrogen and a layer of TiN film is remained on the surface of the Ti target, and the second, third and other subsequent chips can directly and sequentially deposit Al, Ti and TiN, because the last chip sputters the deposited TiN and the second cavity retains nitrogen and a layer of TiN film is remained on the surface of the Ti target, an Al/TiN/Ti/TiN layer is obtained on the chip.
Referring to fig. 2, when Al/Ti/TiN is deposited on a chip, after annealing and etching, a TiAl alloy is formed during annealing due to direct contact between Al and Ti, which hinders recrystallization and stress release of Al, and the obtained Al electrode has a smooth surface without pits. Referring to fig. 3, when Al/TiN/Ti/TiN is deposited on the chip, after annealing and etching, since Al is not in contact with Ti, Ti has no influence on Al, and the obtained Al electrode has pits on the surface, is not easy to fall off first, and has high success rate.
The invention discloses a process method for improving the routing success rate of a chip Al electrode, which is characterized in that when Al/Ti/TiN is deposited on a chip, a layer of TiN is formed between an Al layer and a Ti layer, and the problem that alloy is formed by the contact of Al and Ti during annealing to obstruct the stress release and recrystallization of Al is avoided, so that the obtained Al electrode has pits, and the routing is not easy to fall off due to the fact that the pits are of uneven structures, thereby being beneficial to the success rate of subsequent routing.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (3)
1. A technological method for improving chip Al electrode routing success rate is characterized by comprising the following steps:
s1, providing magnetron sputtering equipment, wherein the magnetron sputtering equipment comprises a first cavity for depositing Al and a second cavity for depositing Ti and TiN, starting the magnetron sputtering equipment to deposit TiN, and retaining nitrogen for forming TiN in the second cavity and leaving a TiN film on the surface of the Ti target;
s2, providing a chip, and depositing an Al layer, a Ti layer and a TiN layer on the chip in sequence by using the magnetron sputtering equipment to obtain an Al/TiN/Ti/TiN layer on the chip by deposition;
s3, annealing the chip on which the Al/TiN/Ti/TiN layer is deposited;
s4, depositing a passivation layer on the Al/TiN/Ti/TiN layer;
s5, etching the passivation layer and the TiN/Ti/TiN layer to obtain a chip with a pocked Al electrode;
and S6, repeating the steps S2 to S5, and producing the chips with the pocked Al electrodes in batches.
2. The process method for improving the wire bonding success rate of the chip Al electrode according to claim 1, wherein a device is obtained after wire bonding packaging is carried out on the Al electrode.
3. The process method for improving the wire bonding success rate of the chip Al electrode according to claim 1, wherein the passivation layer is made of any one of silicon nitride, silicon oxynitride or silicon oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011432721.1A CN112563128B (en) | 2020-12-10 | 2020-12-10 | Technological method for improving wire bonding success rate of chip Al electrode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011432721.1A CN112563128B (en) | 2020-12-10 | 2020-12-10 | Technological method for improving wire bonding success rate of chip Al electrode |
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| Publication Number | Publication Date |
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| CN112563128A true CN112563128A (en) | 2021-03-26 |
| CN112563128B CN112563128B (en) | 2023-12-12 |
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| CN202011432721.1A Active CN112563128B (en) | 2020-12-10 | 2020-12-10 | Technological method for improving wire bonding success rate of chip Al electrode |
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Citations (8)
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|---|---|---|---|---|
| US3428493A (en) * | 1966-01-03 | 1969-02-18 | Standard Oil Co | Electrical energy storage device comprising aluminum-lithium electrode and mechanical screen surrounding the electrode |
| US5830540A (en) * | 1994-09-15 | 1998-11-03 | Eltron Research, Inc. | Method and apparatus for reactive plasma surfacing |
| JP2003253437A (en) * | 2002-02-26 | 2003-09-10 | Kobe Steel Ltd | SEMICONDUCTOR DEVICE ELECTRODE/WIRING, ELECTRODE FILM/ WIRING FILM FOR SEMICONDUCTOR DEVICE, AND SPUTTERING TARGET FOR DEPOSITION OF Al-ALLOY THIN FILM |
| JP2005235852A (en) * | 2004-02-17 | 2005-09-02 | Seiko Epson Corp | Process for forming multilayer film and process for fabricating device |
| CN1945860A (en) * | 2005-10-06 | 2007-04-11 | 大连路美芯片科技有限公司 | Method for preparing LED electrode |
| CN106241729A (en) * | 2015-06-12 | 2016-12-21 | 因文森斯公司 | CMOS-MEMS integrating device and manufacture method including contact layer |
| CN209150141U (en) * | 2018-09-25 | 2019-07-23 | 厦门市三安光电科技有限公司 | A kind of light emitting diode construction |
| CN110265307A (en) * | 2019-06-06 | 2019-09-20 | 深圳市芯茂微电子有限公司上海携英微电子分公司 | Manufacture method for packaging semiconductor and its encapsulating structure |
-
2020
- 2020-12-10 CN CN202011432721.1A patent/CN112563128B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3428493A (en) * | 1966-01-03 | 1969-02-18 | Standard Oil Co | Electrical energy storage device comprising aluminum-lithium electrode and mechanical screen surrounding the electrode |
| US5830540A (en) * | 1994-09-15 | 1998-11-03 | Eltron Research, Inc. | Method and apparatus for reactive plasma surfacing |
| JP2003253437A (en) * | 2002-02-26 | 2003-09-10 | Kobe Steel Ltd | SEMICONDUCTOR DEVICE ELECTRODE/WIRING, ELECTRODE FILM/ WIRING FILM FOR SEMICONDUCTOR DEVICE, AND SPUTTERING TARGET FOR DEPOSITION OF Al-ALLOY THIN FILM |
| JP2005235852A (en) * | 2004-02-17 | 2005-09-02 | Seiko Epson Corp | Process for forming multilayer film and process for fabricating device |
| CN1945860A (en) * | 2005-10-06 | 2007-04-11 | 大连路美芯片科技有限公司 | Method for preparing LED electrode |
| CN106241729A (en) * | 2015-06-12 | 2016-12-21 | 因文森斯公司 | CMOS-MEMS integrating device and manufacture method including contact layer |
| CN209150141U (en) * | 2018-09-25 | 2019-07-23 | 厦门市三安光电科技有限公司 | A kind of light emitting diode construction |
| CN110265307A (en) * | 2019-06-06 | 2019-09-20 | 深圳市芯茂微电子有限公司上海携英微电子分公司 | Manufacture method for packaging semiconductor and its encapsulating structure |
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| CN112563128B (en) | 2023-12-12 |
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