CN112562766A

CN112562766A - Rereading management method, solid state disk controller and solid state disk

Info

Publication number: CN112562766A
Application number: CN202011539962.6A
Authority: CN
Inventors: 方浩俊; 黄运新
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2021-03-26

Abstract

The embodiment of the invention relates to the field of solid state disk application, and discloses a reread management method, a solid state disk controller and a solid state disk, wherein the method comprises the following steps: determining the offset direction of each threshold voltage according to the first unit quantity and the second unit quantity; determining the offset degree of each threshold voltage according to the first record value and the second record value; and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing re-reading operation based on the adjusted threshold voltage. By recording each voltage distribution state in the writing stage and the reading stage, adjusting the offset direction and the offset degree of the threshold voltage and determining the adjusted threshold voltage, the embodiment of the invention can improve the re-reading efficiency of the solid state disk, thereby improving the overall reading performance.

Description

Rereading management method, solid state disk controller and solid state disk

Technical Field

The invention relates to the field of solid state disk application, in particular to a reread management method, a solid state disk controller and a solid state disk.

Background

Solid State Drives (SSD), which are hard disks made of Solid State electronic memory chip arrays, include a control unit and a memory unit (FLASH memory chip or DRAM memory chip). At present, a considerable part of solid state disk systems are Dynamic Random Access Memories (DRAMs), so that SSDs have a large data cache space for caching data.

Flash memory (NAND Flash) is the main storage medium for solid state disks. Flash memory has now evolved to 3D TLC with an IO interface speed of 1600 MT; the development of the method also brings some problems, such as that the original bit error rate (UBER) is higher and higher, and in order to reduce the original bit error rate, re-reading (Read Retry) is required after adjusting the threshold voltage. However, since it is difficult to observe the voltage distribution shift direction from the outside of the Flash memory (NAND Flash), the re-reading operation for adjusting the threshold voltage often requires a large number of times. The number of times of re-reading affects the reading performance of the solid state disk, and particularly, performance Consistency (Consistency) performance in the qos (quality of service) of the reading performance.

The main control or the firmware of the existing solid state disk is usually performed by sequentially increasing the rereading level. The threshold voltage setting in the corresponding single re-reading process is often performed in a mode of traversing one by one according to a list given by a manufacturer, so that the re-reading success rate is insufficient, and the re-reading times are excessive.

Based on this, there is a need for improvement in the art.

Disclosure of Invention

The embodiment of the invention aims to provide a rereading management method, a solid state disk controller and a solid state disk, which solve the technical problem that the conventional solid state disk rereading success rate is insufficient, and improve the rereading efficiency of the solid state disk so as to improve the overall reading performance.

In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:

in a first aspect, an embodiment of the present invention provides a rereading management method, where the method includes:

acquiring the number of first units in each voltage distribution state in a writing-in stage, and determining a first record value corresponding to each voltage distribution state;

acquiring the number of second units in each voltage distribution state during the reading stage of the previous re-reading, and determining a second record value corresponding to each voltage distribution state;

determining the offset direction of each threshold voltage according to the first unit quantity and the second unit quantity;

determining the offset degree of each threshold voltage according to the first recording value and the second recording value;

and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing re-reading operation based on the adjusted threshold voltage.

In some embodiments, the determining the degree of shift of each threshold voltage from the first recorded value and the second recorded value comprises:

calculating a difference between the first state value and the second state value;

determining a stepping amount according to the difference value;

and determining the offset degree of the threshold voltage according to the stepping amount.

In some embodiments, the determining the shift direction of each threshold voltage according to the first number of cells and the second number of cells includes:

determining the offset direction of the threshold voltage corresponding to the previous voltage distribution state according to the first unit quantity and the second unit quantity corresponding to the previous voltage distribution state;

and determining the offset direction of the threshold voltage corresponding to the next voltage distribution state by combining the first unit quantity and the second unit quantity corresponding to the next voltage distribution state according to the offset direction of the threshold voltage corresponding to the previous voltage distribution state.

In some embodiments, the determining, according to the shift direction of the threshold voltage corresponding to the previous voltage distribution state and by combining the first cell number and the second cell number corresponding to the subsequent voltage distribution state, the shift direction of the threshold voltage corresponding to the subsequent voltage distribution state includes:

according to the type of flash memory particles, the voltage distribution states of the flash memory particles are M (M is more than or equal to 2 and M is the power of 2), and are arranged from low to high, namely the 1 st, 2 nd, 3 th, … th, M-1 th and M-th voltage distribution states;

determining the offset of the (N +1) th voltage state according to the offset of the Nth voltage state, wherein N is a positive integer and is sequentially increased from 1 to M-1 until the offset of the Mth voltage state is determined;

and determining the offset direction of the threshold voltage corresponding to the previous voltage distribution state according to the offset of the previous voltage distribution state so as to determine the offset direction of the threshold voltage corresponding to the next voltage distribution state until determining the offset direction of the threshold voltage corresponding to the last voltage distribution state.

In some embodiments, before performing the reread operation, the method further comprises:

judging whether a rereading grade record table exists or not during normal reading operation;

if so, inquiring the rereading grade record table when an uncorrectable error exists, determining a rereading grade, and performing a first rereading operation based on the rereading grade;

if not, selecting an initial rereading level to carry out the first rereading operation.

In some embodiments, the method further comprises:

and pre-establishing a rereading grade recording table, wherein the rereading grade recording table comprises at least two rereading grades.

In some embodiments, the method further comprises:

after the first re-reading operation is finished, if an uncorrectable error still exists, further judging whether the re-reading times reach the maximum;

if so, recording the current reading failure and resetting the rereading grade record table;

if not, acquiring the number of first units in each voltage distribution state in the writing stage, and determining a first record value corresponding to each voltage distribution state;

and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing second re-reading operation based on the adjusted threshold voltage.

In some embodiments, the method further comprises:

and after the second re-reading operation is completed, circularly judging whether an uncorrectable error exists or not until the re-reading times reach the maximum or no uncorrectable error exists.

In some embodiments, the method further comprises:

if the uncorrectable error does not exist, the current reading success is recorded, and the rereading level record table is updated.

In a second aspect, an embodiment of the present invention provides a solid state disk controller, which is applied to a solid state disk, where the solid state disk includes at least one flash memory medium, and the solid state disk controller includes a data path processing module, and is in communication connection with the at least one flash memory medium of the solid state disk;

wherein the data path processing module comprises:

the interface module is used for exchanging data with the flash memory medium;

the cache management module is used for caching data;

and the rereading information management module is used for counting the number of the units in each voltage distribution state and determining a number record value corresponding to each voltage distribution state.

In some embodiments, the reread information management module includes:

the data distribution statistical module is used for counting the number of the units in each voltage distribution state;

the information processing logic module is connected with the data distribution statistical module and used for determining the quantity record value corresponding to each voltage distribution state;

and the record value protection module is connected with the data distribution statistical module and the information processing logic module and is used for protecting the quantity record values.

In a third aspect, an embodiment of the present invention provides a solid state disk, including:

the solid state hard disk controller as described above, wherein the solid state hard disk controller is configured to perform the reread management method as described above;

and the flash memory medium is in communication connection with the solid state hard disk controller.

In a fourth aspect, the embodiment of the present invention further provides a non-volatile computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are configured to enable a solid state disk to perform the rereading management method described above.

The embodiment of the invention has the beneficial effects that: in contrast to the prior art, an embodiment of the present invention provides a reread management method, where the method includes: acquiring the number of first units in each voltage distribution state in a writing-in stage, and determining a first record value corresponding to each voltage distribution state; acquiring the number of second units in each voltage distribution state during the reading stage of the previous re-reading, and determining a second record value corresponding to each voltage distribution state; determining the offset direction of each threshold voltage according to the first unit quantity and the second unit quantity; determining the offset degree of each threshold voltage according to the first recording value and the second recording value; and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing re-reading operation based on the adjusted threshold voltage. The embodiment of the invention is beneficial to hitting the required optimal voltage, improving the re-reading efficiency and improving the overall reading performance of the solid state disk by recording each voltage distribution state in the writing stage and the reading stage, adjusting the offset direction and the offset degree of the threshold voltage and determining the adjusted threshold voltage.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

FIG. 1 is a schematic diagram of a TLC NAND Flash voltage distribution provided by an embodiment of the invention;

FIG. 2 is a diagram illustrating representative values of different pages at different voltage levels according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating threshold voltage distributions for different pages according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an ideal voltage profile provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of an offset voltage profile provided by an embodiment of the present invention;

FIG. 6 is a flow chart of a prior art reread operation;

fig. 7 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;

FIG. 8 is a diagram of a solid state hard disk controller according to an embodiment of the present invention;

FIG. 9 is a block diagram of a data path module according to an embodiment of the present invention;

FIG. 10 is a block diagram of another data path module according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of the structure of the reread information management module in FIG. 10;

FIG. 12 is a flowchart of a method for rereading management according to an embodiment of the present invention;

FIG. 13 is a detailed flowchart of step S40 in FIG. 12;

FIG. 14 is a schematic diagram of a voltage profile provided by an embodiment of the present invention;

FIG. 15 is a diagram illustrating a data writing process according to an embodiment of the present invention;

FIG. 16 is a diagram illustrating a data read process according to an embodiment of the present invention;

fig. 17 is a schematic overall flowchart of a rereading management method according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

A typical Solid State Drive (SSD) usually includes a Solid State disk controller (host controller), a flash memory array, a cache unit, and other peripheral units.

The solid state hard disk controller is used as a control operation unit for managing an SSD internal system; flash memory arrays (NAND Flash), as memory cells for storing data, including user data and system data, typically present multiple channels (channels, abbreviated CH), one Channel being independently connected to a set of NAND Flash, e.g. CH0/CH1 … … CHx. The characteristic of the Flash memory (NAND Flash) is that before writing, erasing must be carried out, and the erasing times of each Flash memory are limited; the cache unit is used for caching the mapping table, and the cache unit is generally a Dynamic Random Access Memory (DRAM). Other peripheral units may include sensors, registers, and the like.

A Flash memory (NAND Flash) is a nonvolatile storage medium, and is characterized in that electrons can be stored in one cell, the number of the stored electrons can be represented as a voltage value, and the voltage value can be divided into a plurality of areas. If the two regions are divided, only one bit is stored (such Flash is called SLC), if the two regions are divided, 2 bits are stored (such Flash is called MLC), if the two regions are divided, 3 bits are stored (such Flash is called TLC), and the power of 2 is taken as the number of the stored bits to determine the number of the distribution regions.

After data is written, the number of stored electrons can be represented as a voltage value, and the determination of the read value depends on the comparison between the voltage value of the cell and a reference voltage (or threshold voltage).

Referring to fig. 1, fig. 1 is a schematic diagram of a TLC NAND Flash voltage distribution according to an embodiment of the present invention;

as shown in FIG. 1, a typical TLC NAND Flash has 3 bits stored in one cell, 8 voltage distribution areas, and generally 3 bits distributed in one cell are coded and distributed into 3 pages, and since binary coding is used, the voltage distribution of all cells of each Page appears as shown in FIG. 1, and the vertical axis direction represents the number of cells at a certain voltage value. In the same region, the values represented by the same Page have different distributions, for example, the voltage distribution is between V1 and V2, and the number of cells in the voltage range presents a waveform.

Referring to fig. 2 again, fig. 2 is a schematic diagram of representative values of different pages at different voltage values according to an embodiment of the present invention;

as shown in FIG. 2, the binary value of a cell in the region between V1 and V2 is 0 for the LSB Page and 1 for the CSB and MSB Page. This is due to the rules set by the manufacturer of the particles, for the LSB, the regions less than V1 and greater than V5 are set to values of 1, and between V1 and V5 are set to values of 0. By analogy, the values of the various regions on different pages, as shown in FIG. 2, still exhibit 8 binary values (000-111) from the column perspective.

Referring to FIG. 3, FIG. 3 is a schematic diagram of a threshold voltage distribution of different pages according to an embodiment of the present invention;

as shown in FIG. 3, the decision point distribution of the threshold voltages is different for different pages (LSB/CSB/MSB). From another perspective, it is understood that the stored data Pattern determines the voltage distribution of the flash Cell.

Referring to fig. 4 and 5, fig. 4 is a schematic diagram of an ideal voltage distribution according to an embodiment of the invention; FIG. 5 is a schematic diagram of an offset voltage profile provided by an embodiment of the present invention;

as shown in fig. 4, an ideal voltage distribution, the threshold voltage is at the intersection of the two waveforms, so that the number of misjudged bits is minimized.

In practice, as shown in fig. 5, due to many factors, after the writing is completed, the distribution is as shown in fig. 6. it can be seen that 2 waveforms have an overlap, such as between ER and a, and at the threshold voltage V1, the Cell in these overlaps is misinterpreted, i.e. its value is an erroneous bit for reading. These bits need to be corrected by error correction techniques. When the error correction capability is fixed, the threshold voltage should be set to minimize the bit that is erroneously determined.

It will be appreciated that if the threshold voltage is at the intersection of the two waveforms, its false bit will be the smallest. However, due to more factors, when reading, the distribution waveforms may further shift, as shown in fig. 5, so that the threshold voltage is not located at the intersection of the two waveforms, and when the shift is too large, the corresponding misjudgment bit increases, so that the error correction technique cannot complete the correction.

The re-reading technique is to re-set the threshold voltage and then read again, as shown in V1 in fig. 5, if V1 is shifted right to the crossing point V1' of the two waveforms, the misjudged bit will be reduced, and the error correction technique can complete the correction, so that the reading is successful. In analogy, the so-called re-reading technique is to adjust the threshold voltage (or the reference voltage) to be at the optimal boundary point of the adjacent related voltage distribution domains, so as to minimize the bit with erroneous judgment, so that the number of erroneous bits is within the error-correctable range, and thus the reading is successful.

Typically, a Flash memory (NAND Flash) vendor will provide a range of re-read levels (i.e., corresponding to different adjusted threshold voltages) for threshold voltage adjustment for the re-read process.

Referring to FIG. 6, FIG. 6 is a flowchart illustrating a reread operation according to the prior art;

as shown in fig. 6, the flow of the rereading operation includes:

step S601: normal read operation;

step S602: whether there is an uncorrectable error;

step S603: if so, selecting an initial re-reading level;

step S604: carrying out rereading operation;

step S605: whether there is an uncorrectable error;

step S606: if yes, further judging whether the re-reading grade is the maximum;

step S607: if the re-reading grade is not maximum, increasing the re-reading grade;

step S608: if the judgment result in the step S602 or the step S605 is negative, recording that the current reading is successful;

step S609: if the re-reading grade is the maximum, recording the current reading failure;

it can be seen that, in the existing master control or firmware of the solid state disk, re-reading is not specifically managed, and each re-reading is performed by sequentially incrementing the re-reading from an initial re-reading level until the re-reading is successful (no uncorrectable error occurs), or the re-reading operation is ended until the re-reading level is highest and still unsuccessful.

The rereading grades are more and more, so that the rereading grades are sequentially increased. The threshold voltage setting in the corresponding single re-reading process is often subjected to individual traversal attempts according to a list given by a manufacturer, so that the re-reading success rate is insufficient.

In view of this, embodiments of the present invention provide a rereading management method, a solid state disk controller, and a solid state disk, so as to solve the technical problem that the conventional solid state disk has a poor rereading success rate, and improve the overall reading performance of the solid state disk.

The technical scheme of the invention is specifically explained in the following by combining the drawings in the specification.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention.

As shown in fig. 7, the solid state disk 100 includes a flash memory medium 110 and a solid state disk controller 120 connected to the flash memory medium 110. The solid state disk 100 is in communication connection with the host 200 in a wired or wireless manner, so as to implement data interaction.

The Flash memory medium 110, which is a storage medium of the solid state disk 100 and is also called a Flash memory, a Flash memory or a Flash granule, belongs to one of storage devices, and is a nonvolatile memory, which can store data for a long time without current supply, and the storage characteristics of the Flash memory medium 110 are equivalent to those of a hard disk, so that the Flash memory medium 110 can become a basis of storage media of various portable digital devices.

The FLASH memory medium 110 may be Nand FLASH, which uses a single transistor as a storage unit of binary signals, and has a structure very similar to that of a common semiconductor transistor, except that a floating gate and a control gate are added to the single transistor of the Nand FLASH, the floating gate is used for storing electrons, the surface of the floating gate is covered by a layer of silicon oxide insulator and is coupled with the control gate through a capacitor, when a negative electron is injected into the floating gate under the action of the control gate, the storage state of the single crystal of the Nand FLASH is changed from "1" to "0", and when the negative electron is removed from the floating gate, the storage state is changed from "0" to "1", and the insulator covered on the surface of the floating gate is used for trapping the negative electron in the floating gate, so as to realize data storage. That is, the Nand FLASH memory cell is a floating gate transistor, and data is stored in the form of electric charge using the floating gate transistor. The amount of charge stored is related to the magnitude of the voltage applied to the floating gate transistor.

A Nand FLASH comprises at least one Chip, each Chip is composed of a plurality of Block physical blocks, and each Block physical Block comprises a plurality of Page pages. The Block physical Block is the minimum unit of Nand FLASH for executing the erasing operation, the Page is the minimum unit of Nand FLASH for executing the reading and writing operation, and the capacity of one Nand FLASH is equal to the number of the Block physical blocks and the number of the Page pages contained in one Block physical Block. Specifically, the flash memory medium 10 may be classified into SLC, MLC, TLC and QLC according to different levels of the voltages of the memory cells.

The solid state hard disk controller 120 includes a data converter 121, a processor 122, a buffer 123, a flash memory controller 124, and an interface 125.

And a data converter 121 respectively connected to the processor 122 and the flash controller 124, wherein the data converter 121 is configured to convert binary data into hexadecimal data and convert the hexadecimal data into binary data. Specifically, when the flash memory controller 124 writes data to the flash memory medium 110, the binary data to be written is converted into hexadecimal data by the data converter 121, and then written into the flash memory medium 110. When the flash controller 124 reads data from the flash medium 110, hexadecimal data stored in the flash medium 110 is converted into binary data by the data converter 121, and then the converted data is read from the binary data page register. The data converter 121 may include a binary data register and a hexadecimal data register. The binary data register may be used to store data converted from hexadecimal to binary, and the hexadecimal data register may be used to store data converted from binary to hexadecimal.

And a processor 122 connected to the data converter 121, the buffer 123, the flash controller 124 and the interface 125, respectively, wherein the processor 122, the data converter 121, the buffer 123, the flash controller 124 and the interface 125 may be connected by a bus or other methods, and the processor is configured to execute the nonvolatile software programs, instructions and modules stored in the buffer 123, so as to implement any method embodiment of the present invention.

The buffer 123 is mainly used for buffering read/write commands sent by the host 200 and read data or write data acquired from the flash memory 110 according to the read/write commands sent by the host 200. The buffer 123, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The buffer 123 may include a storage program area that may store an operating system, an application program required for at least one function. In addition, the buffer 123 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the buffer 123 may optionally include memory that is remotely located from the processor 124. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The buffer 123 may be a Static Random Access Memory (SRAM), a Coupled Memory (TCM), or a Double data rate Synchronous Dynamic Random Access Memory (DDR SRAM).

A flash memory controller 124 connected to the flash memory medium 110, the data converter 121, the processor 122 and the buffer 123, for accessing the flash memory medium 110 at the back end and managing various parameters and data I/O of the flash memory medium 110; or, an interface and a protocol for providing access, implementing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring an I/O instruction sent by the host 200, decoding, and generating an internal private data result to wait for execution; or, the core processing module is used for taking charge of the FTL (Flash translation layer).

The interface 125 is connected to the host 200, the data converter 121, the processor 122, and the buffer 123, and configured to receive data sent by the host 200, or receive data sent by the processor 122, so as to implement data transmission between the host 200 and the processor 122, where the interface 125 may be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, a NGFF interface, a CFast interface, a SFF-8639 interface, and a m.2nvme/SATA protocol.

Referring to fig. 8 again, fig. 8 is a schematic structural diagram of a solid state hard disk controller according to an embodiment of the present invention; the solid state disk controller belongs to the solid state disk.

As shown in fig. 8, the solid state hard disk controller includes: PCIe interface controller 126, DDR controller 127, NVMe interface controller 128, processor 122, peripheral module 129, datapath module 1210, and flash controller 124.

Specifically, the PCIe interface controller 126 is configured to control a PCIe communication protocol, the DDR controller 127 is configured to control a dynamic random access memory, the NVMe interface controller 128 is configured to control an NVMe communication protocol, the peripheral module 129 is configured to control other related communication protocols, and the data path module 1210 is configured to control a data path, for example: and managing a write cache, wherein the flash memory controller 124 is used for data processing of the flash memory.

The solid state disk controller 120 further includes a data converter 121, a buffer 123, an interface 125, and the like.

Specifically, the data converter 121 is connected to the processor and the flash memory controller, respectively, and is configured to convert binary data into hexadecimal data and convert the hexadecimal data into binary data. Specifically, when the flash memory controller writes data to the flash memory medium, the binary data to be written is converted into hexadecimal data by the data converter, and then the hexadecimal data is written to the flash memory medium. When the flash memory controller reads data from the flash memory medium, the hexadecimal data stored in the flash memory medium is converted into binary data through the data converter, and then the converted data is read from the binary data page register. Wherein the data converter may include a binary data register and a hexadecimal data register. The binary data register may be used to store data converted from hexadecimal to binary, and the hexadecimal data register may be used to store data converted from binary to hexadecimal.

Specifically, the processor 122 is connected to the data converter 121, the buffer 123, the flash controller 124 and the interface 125, respectively, wherein the processor and the data converter, the buffer, the flash controller and the interface may be connected through a bus or other means, and the processor is configured to run the nonvolatile software program, the instructions and the modules stored in the buffer, so as to implement any method embodiment of the present invention.

Specifically, the buffer is mainly used for buffering read/write commands sent by the host and read data or write data acquired from the flash memory medium according to the read/write commands sent by the host. The cache, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The buffer may include a storage program area that may store an operating system, an application program required for at least one function. In addition, the buffer may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the cache optionally includes memory that is remotely located from the processor. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The buffer may be a Static Random Access Memory (SRAM), a Coupled Memory (TCM), or a Double data rate Synchronous Dynamic Random Access Memory (DDR SRAM).

Specifically, the flash memory controller is connected to the flash memory medium, the data converter, the processor and the buffer, and is configured to access the flash memory medium at the back end and manage various parameters and data I/O of the flash memory medium; or, an interface and a protocol for providing access, implementing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring an I/O instruction sent by a host, decoding and generating an internal private data result to wait for execution; or, the core processing module is used for taking charge of the FTL (Flash translation layer).

Specifically, the interface is connected to the host, the data converter, the processor and the buffer, and configured to receive data sent by the host, or receive data sent by the processor, so as to implement data transmission between the host and the processor, where the interface may be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, a SFF-8639 interface, and a m.2nvme/SATA protocol.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a data path module according to an embodiment of the present invention;

as shown in fig. 9, the data path module 1210 includes: an interface module 1211, a buffer management module 1212, and a rereading information management module 1213, wherein the interface module 1211 is communicatively connected to the buffer management module 1212 and the rereading information management module 1213, and the buffer management module 1212 is communicatively connected to the rereading information management module 1213.

Specifically, the interface module 1211 includes: the flash memory comprises a processor interface (CPU IF), a flash memory interface and an NVMe interface (DMAC/NVMe IF), wherein the processor interface is used for exchanging data with the CPU, the flash memory interface is used for exchanging data with the flash memory, the flash memory in the embodiment of the invention comprises an SLC flash memory, an MLC flash memory and a TLC flash memory, and the NVMe interface is used for exchanging data with an NVMe hard disk;

referring to fig. 10 again, fig. 10 is a schematic structural diagram of another data path module according to an embodiment of the present invention;

as shown in fig. 10, the Data Path module (Data Path Processor) includes: the device comprises a processor interface, an NVMe interface, a cache management module, an ECC Engine (ECC Engine) and a flash memory interface, wherein the ECC Engine comprises a reread information management module;

the processor interface is in communication connection with the NVMe interface, the cache management module and an ECC Engine (ECC Engine) and is used for exchanging data with the processor;

the NVMe interface is in communication connection with the processor interface, the cache management module and the flash memory interface and is used for exchanging data with the NVMe hard disk;

the cache management module is communicatively connected to the processor interface, the reread information management module, and the flash memory interface, and is configured to cache data, specifically, the cache management module includes a cache, for example: the cache management module also comprises a logic circuit used for managing the Buffer;

the rereading information management module is in communication connection with the cache management module and is used for rereading information management;

the ECC Engine (ECC Engine) is in communication connection with the processor interface, the cache management module and the flash memory interface and is used for performing related operations of reread information management and ECC check;

the flash memory interface is in communication connection with the NVMe interface, the cache management module and an ECC Engine (ECC Engine) and is used for exchanging data with the flash memory;

referring to fig. 11 again, fig. 11 is a schematic structural diagram of the rereading information management module in fig. 10;

as shown in fig. 11, the rereading information management module 1213 includes: a data distribution statistics module 12131, an information processing logic module 12132, and a recorded value protection module 12133, wherein the data distribution statistics module 12131 is communicatively coupled to the information processing logic module 12132, and the information processing logic module 12132 is communicatively coupled to the recorded value protection module 12133;

the data distribution statistical module 12131 is configured to count the number of cells in each voltage distribution state;

the information processing logic module 12132 is connected to the data distribution statistics module 12131 and the recorded value protection module 12133, and is configured to determine a number of recorded values corresponding to each voltage distribution state; in an embodiment of the present invention, the number record includes a percentage value of the number of cells per voltage distribution state to the total number of cells.

The record value protection module 12133 is connected to the data distribution statistics module 12131 and the information processing logic module 12132, and is configured to protect the quantity record value, so that the quantity record value can be stored in a flash memory, and can be corrected when an error bit occurs.

Specifically, the record value protection module 12133 includes: an ECC logic unit 31 and a RAID XOR logic unit 32, where the ECC logic unit 31 is used for error correction, and the ECC logic unit includes a logic circuit for implementing a BCH algorithm and/or an RS algorithm for error correction.

In an embodiment of the present invention, the record value protection module further includes an encoding unit configured to Encode (Encode) when the number record value is written, and a decoding unit configured to Decode (Decode) when the number record value is read.

In the embodiment of the present invention, data distribution statistics is performed by the data distribution statistics module to obtain a specific cell number of each voltage distribution state, and then a number record value corresponding to each voltage distribution state is determined by the information processing logic module, for example: the quantity record values comprise percentage values, the result is obtained by calculation of the information processing logic module and is embodied as a group of values of 'occupation ratio of distribution state', and then ECC + RAID protection is needed to be carried out on the values, namely the values are used as input to obtain a group of output data to be stored on the flash memory.

In an embodiment of the present invention, a solid state disk controller is provided, which is applied to a solid state disk, where the solid state disk includes at least one flash memory medium, and the solid state disk controller includes a data path processing module communicatively connected to the at least one flash memory medium of the solid state disk; wherein the data path processing module comprises: the interface module is used for exchanging data with the flash memory medium; the cache management module is used for caching data; and the rereading information management module is used for counting the number of the units in each voltage distribution state and determining a number record value corresponding to each voltage distribution state. By adding the rereading information management module for counting the number of units in each voltage distribution state and determining the number record value corresponding to each voltage distribution state, the embodiment of the invention can improve the overall reading performance of the solid state disk.

It will be appreciated that the re-read technique essentially finds a suitable threshold voltage to reduce the number of false positives, and that it would be beneficial to set the correct threshold voltage if the threshold voltage bias could be inferred by analyzing the read data, as shown in figure 4 when the relevant waveform crossing (trough) is the optimum voltage point V1. However, due to the characteristics of the flash memory, the voltage distribution is shifted, that is, the originally set threshold voltage is not at the waveform crossing point, as shown in fig. 5, the original optimal voltage point V1 is not at the trough, and the actually expected optimal voltage is V1'. Therefore, how to infer the threshold voltage bias from analyzing the read data is a problem to be solved by the present invention, and based on this, the embodiment of the present invention provides a re-read management method.

Referring to fig. 12 again, fig. 12 is a flowchart of a rereading management method according to an embodiment of the present invention;

as shown in fig. 12, the rereading management method is applied to the solid state disk controller, and the method includes:

step S10: acquiring the number of first units in each voltage distribution state in a writing-in stage, and determining a first record value corresponding to each voltage distribution state;

specifically, in the embodiment of the present invention, the information of the previous rereading of the present rereading is considered, so as to provide a correct adjustment direction for the present rereading. By obtaining a first number of cells in each voltage distribution state during a write phase and determining a first recorded value corresponding to each voltage distribution state, wherein the first recorded value includes a first state value, wherein the first state value is represented by a group of values "duty of distribution state", for example: the first state value comprises at least one of a ratio, percentage of a first number of cells to a total number of cells for each voltage distribution state;

step S20: acquiring the number of second units in each voltage distribution state during the reading stage of the previous re-reading, and determining a second record value corresponding to each voltage distribution state;

it is understood that the read phase of the previous re-reading is after the write phase, by obtaining a second number of cells in each voltage distribution state during the read phase of the previous re-reading, and determining a second recorded value corresponding to each voltage distribution state, wherein the second recorded value includes a second state value, wherein the second state value is represented by a group of values of "duty ratio of distribution state", for example: the second state value comprises at least one of a ratio, percentage of the first number of cells to the total number of cells for each voltage distribution state;

step S30: determining the offset direction of each threshold voltage according to the first unit quantity and the second unit quantity;

specifically, the first cell number reflects the cell number of each voltage distribution state in the write phase of the previous rereading, the second cell number reflects the cell number of each voltage distribution state in the read phase of the previous rereading, and by comparing the first cell number and the second cell number, the variation trend of the cell number can be determined to determine the offset direction of each threshold voltage, for example: determining the shift direction of the threshold voltage V1 to be right-biased when the first number of cells in the ER state is less than the second number of cells, and determining the shift direction of the threshold voltage V1 to be left-biased when the first number of cells in the ER state is greater than the second number of cells;

by determining the first cell number and the second cell number of each voltage distribution state, so as to determine the offset direction of each threshold voltage, the embodiment of the invention can better adjust the threshold voltage.

In an embodiment of the present invention, the determining the shift direction of each threshold voltage according to the first number of cells and the second number of cells includes:

Specifically, the determining, according to the shift direction of the threshold voltage corresponding to the previous voltage distribution state and by combining the first unit number and the second unit number corresponding to the next voltage distribution state, the shift direction of the threshold voltage corresponding to the next voltage distribution state includes:

according to the type of flash memory particles, the voltage distribution states of the flash memory particles are M (M is more than or equal to 2, M is the power of 2), and are arranged from low to high, namely the 1 st, 2 nd, 3 th, … th, M-1 th and M voltage distribution states in sequence;

It is understood that, in particular, the flash memory granule type includes an MLC type, a TLC type, and a QLC type, and when the flash memory granule type is the MLC type, the number of voltage distribution states thereof is 4, that is, M is 4; when the flash memory particle type is the TLC type, the number of voltage distribution states thereof is 8, i.e., M is 8; when the flash memory granule type is the QLC type, the number of voltage distribution states is 16, that is, M is 16; the following description is given by way of example of a cell type of TLC type, i.e. voltage distribution state M ═ 8:

assuming that the voltage distribution states are arranged from low to high, the first voltage distribution state is a state ER, the second voltage distribution state is a state a, the third voltage distribution state is a state B, the fourth voltage distribution state is a state C, the fifth voltage distribution state is a state D, the sixth voltage distribution state is a state E, the seventh voltage distribution state is a state F, and the eighth voltage distribution state is a state G;

when the voltage distribution of the Nth voltage distribution state is shifted to the right, the calculation formula of the statistical value of the unit number is as the following formulas (1) and (2):

Ccnt(N’)＝Ccnt(N)-ΔX； (1)

Ccnt(N+1’)＝Ccnt(N+1)+ΔX±ΔN+1_N+2； (2)

when the voltage distribution of the Nth voltage distribution state shifts left, the calculation formula of the statistical value of the unit number is as the following formulas (3) and (4):

Ccnt(N’)＝Ccnt(N)+ΔM； (3)

Ccnt(N+1’)＝Ccnt(N+1)-ΔM±ΔN+1_N+2； (4)

wherein Ccnt (N) is the number of cells in the nth voltage state in the write phase, Ccnt (N ') is the number of cells in the nth voltage state in the read phase, Δ X is the offset of the right-hand offset of the nth voltage state, Ccnt (N +1) is the number of cells in the (N +1) th voltage state in the write phase, Ccnt (N + 1') is the number of cells in the (N +1) th voltage state in the read phase, and Δ N +1 — N +2 is the offset of the (N +1) th voltage state;

determining the offset of the (N +1) th voltage state according to the offset of the Nth voltage state, wherein N is a positive integer and is sequentially increased from 1 to 7 until the offset of the eighth voltage state is determined;

It will be appreciated that the first voltage distribution state, i.e. the voltage distribution state ER, is not influenced by the previous voltage distribution state, i.e. the direction of the shift of the corresponding threshold voltage V1 of the first voltage distribution state ER can be determined by means of a statistically derived shift amount, each voltage distribution state after the first voltage distribution state is influenced not only by the next voltage distribution state but also by the previous voltage distribution state, therefore, it is necessary to determine the offset of the previous voltage distribution state, so as to determine the offset of the next voltage distribution state, further determining the offset direction of the threshold voltage corresponding to the next voltage distribution state, and therefore determining the offset of the (N +1) th voltage state according to the offset of the nth voltage state, wherein N is sequentially increased from 1 to 7 until the offset of the eighth voltage state is determined; and determining the offset direction of the threshold voltage corresponding to the previous voltage distribution state according to the offset of the previous voltage distribution state so as to determine the offset direction of the threshold voltage corresponding to the next voltage distribution state until determining the offset direction of the threshold voltage corresponding to the last voltage distribution state.

It is understood that the threshold voltage corresponding to the first voltage distribution state ER is V1, the threshold voltage corresponding to the second voltage distribution state a is V2, the threshold voltage corresponding to the third voltage distribution state B is V3, the threshold voltage corresponding to the fourth voltage distribution state C is V4, the threshold voltage corresponding to the fifth voltage distribution state D is V5, the threshold voltage corresponding to the sixth voltage distribution state E is V6, the threshold voltage corresponding to the seventh voltage distribution state is V7, and the threshold voltage corresponding to the eighth voltage distribution state is V8.

In the embodiment of the present invention, by determining the offset amount of the threshold voltage corresponding to the previous voltage distribution state and determining the offset direction of the threshold voltage corresponding to the subsequent voltage distribution state, the embodiment of the present invention can better perform direction adjustment on the threshold voltage.

Step S40: determining the offset degree of each threshold voltage according to the first recording value and the second recording value;

specifically, the first record value includes a first state value, the second record value includes a second state value, preferably, the first state value is a first percentage value, and the second state value is a second percentage value, please refer to fig. 13, where fig. 13 is a schematic detailed flow chart of step S40 in fig. 12;

as shown in fig. 13, the step S40: determining the degree of deviation of each threshold voltage according to the first recorded value and the second recorded value, comprising:

step S41: calculating a difference between the first state value and the second state value;

assuming that the voltage distribution states are arranged from low to high, the first voltage distribution state is state ER, the second voltage distribution state is state a, … …, and so on, the eighth voltage distribution state is state G;

when the voltage distribution is shifted to the right, the calculation formula of the statistical value of the unit number is as the following formulas (1), (2):

Ccnt(N’)＝Ccnt(N)-ΔX； (1)

Ccnt(N+1’)＝Ccnt(N+1)+ΔX±ΔN+1_N+2； (2)

where Ccnt (N) is the number of cells in the nth voltage state in the write phase, Ccnt (N ') is the number of cells in the nth voltage state in the read phase, Δ X is the offset of the right-hand offset of the nth voltage state, Ccnt (N +1) is the number of cells in the N +1 th voltage state in the write phase, Ccnt (N + 1') is the number of cells in the N +1 th voltage state in the read phase, and Δ N +1 — N +2 is the offset of the N +1 th voltage state.

When the voltage distribution is shifted left, the calculation formula of the statistical value of the unit number is as the following formulas (3) and (4):

Ccnt(N’)＝Ccnt(N)+ΔM； (3)

Ccnt(N+1’)＝Ccnt(N+1)-ΔM±ΔN+1_N+2； (4)

where Ccnt (N) is the number of cells in the nth voltage state in the write phase, Ccnt (N ') is the number of cells in the nth voltage state in the read phase, Δ M is the offset of the left bias of the nth voltage state, Ccnt (N +1) is the number of cells in the N +1 th voltage state in the write phase, Ccnt (N + 1') is the number of cells in the N +1 th voltage state in the read phase, and Δ N +1 — N +2 is the offset of the N +1 th voltage state.

It is understood that the offset Δ N +1_ N +2 may be an offset of left offset or an offset of right offset, and when the offset Δ N +1_ N +2 is an offset of left offset, formula (2) is Ccnt (N +1 ') -Ccnt (N +1) + Δ X + Δ N +1_ N +2, and formula (4) is Ccnt (N + 1') -Ccnt (N +1) - Δ M + Δ N +1_ N + 2; when the offset amount Δ N +1_ N +2 is a right offset amount, formula (2) is Ccnt (N +1 ') -Ccnt (N +1) + Δ X- Δ N +1_ N +2, and formula (4) is Ccnt (N + 1') -Ccnt (N +1) - Δ M- Δ N +1_ N + 2;

specifically, referring to fig. 14 again, fig. 14 is a schematic diagram of a voltage distribution according to an embodiment of the invention;

as shown in the upper part of fig. 14, the state ER is taken as an example for explanation: when the read setting is still maintained at the threshold voltage V1, then in the voltage range of Δ a, it can be seen that the number of cells in state ER is decreased by Δ X, while when only the threshold voltage V1 is considered, the number of cells in state a is increased by Δ X, and if the threshold voltage V2 is considered, the position of the threshold voltage V2 with respect to the waveform needs to be considered, so that when the threshold voltage maintains the original value after the waveform shift occurs, the number of cells changes as follows:

Ccnt(ER’)＝Ccnt(ER)-ΔX

Ccnt(A’)＝Ccnt(A)+ΔX±ΔA_B

where Ccnt (ER') is in, Ccnt (ER) is the number of cells in state ER, Δ X is the offset to the right, and Δ A _ B is related to the offset of threshold voltage V2.

Conversely, if the voltage distribution shifts to the left, as shown in the lower half of fig. 14, the number of cells in state ER increases by Δ M, and the number of cells in state a decreases by Δ M.

Ccnt(ER’)＝Ccnt(ER)+ΔM

Ccnt(A’)＝Ccnt(A)–ΔM±ΔA_B

During writing and reading, the Cell number of all voltage distribution states is tracked and compared, for example, during writing, cnt (ER) is counted and recorded, and during reading, cnt (ER') is counted and the increase and decrease of Δ M can be known. The direction of the shift is estimated based on the tendency of the change in the Cell number in the corresponding state when the shift occurs, for example, when the number of cells in the ER state decreases as the data appears, the waveform is shifted to the right relative to V1, and when a new V1' is set, the adjustment should be reversed: adjusted to the left in order to obtain the optimum threshold voltage Vth. V2 can estimate the adjustment direction of V2 by determining the change in the Cell number in the ER state and then determining the trend of the increase and decrease in the Cell number in the a state. The other V3-V7 sequences can be deduced.

It is understood that the magnitude of the deviation amount (Δ X/Δ M), whether left-biased or right-biased, represents the degree of the deviation (which can be understood as the distance of V1' and V1 "from V1), and thus the magnitude of the deviation amount can be used as the step size for setting the new threshold voltage Vth.

Specifically, a difference between the first state value and the second state value is calculated, where the difference between the first state value and the second state value may be used to represent a deviation amount, so as to determine a step amount according to the difference between the first state value and the second state value.

Step S42: determining a stepping amount according to the difference value;

specifically, according to a preset corresponding relationship between a difference and a step amount, the step amount is determined based on the difference, for example: the corresponding relation between the difference and the stepping amount is as follows: and determining the step amount according to the difference value and the corresponding relation.

Step S43: and determining the offset degree of the threshold voltage according to the stepping amount.

Specifically, the step amount is determined as a shift degree of the threshold voltage, that is, the step amount is the shift degree, according to the step amount.

Step S50: and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing re-reading operation based on the adjusted threshold voltage.

Specifically, the adjusted threshold voltage corresponding to each voltage state is equal to the initial value ± the offset degree, where when the offset direction is left offset, the adjusted threshold voltage corresponding to each voltage state is equal to the initial value + the offset degree; when the offset direction is right offset, the adjusted threshold voltage corresponding to each voltage state is equal to the initial value-offset degree.

In the embodiment of the invention, the voltage distribution deviation direction is estimated by tracking the voltage distribution state information of the target data and calculating the Cell quantity change trend of the voltage distribution state during writing and reading, so that the threshold voltage is adjusted in the opposite direction during rereading to realize the direction adjustment of the threshold voltage, and the Cell quantity change degree of the voltage distribution state during writing and reading is calculated by tracking the voltage distribution state information of the target data and used as a reference for adjusting the stepping size of the threshold voltage to realize the threshold adjustment of the threshold voltage.

Referring to fig. 15 again, fig. 15 is a schematic diagram illustrating a data writing process according to an embodiment of the invention;

as shown in fig. 15, the user data external interface passes through the data processing module and then reaches the flash memory array, i.e., from step S1 to step S7. Wherein, the steps S1, S2, S5, S6, S7 are data transfer processes, and details are not described in the present invention, the step S3 is to perform coding of data error correction code (LDPCEnCode) to form Parity to be added to the data block, after completion, the step S4 performs re-reading information processing module, that is, completes statistics of voltage distribution state information, generates a number record value (for example, a percentage value of each state), and performs individual error correction code coding (ECC + RAID XOR) on the record, and then passes through the step S5 together with the user data, and after the step S6, passes through the step S7: writing to a flash memory array;

referring to fig. 16 again, fig. 16 is a schematic diagram of a data reading process according to an embodiment of the invention;

as shown in fig. 16, the data (including the number record value and the error correction code Parity) stored in the flash memory is read to the data processing module for processing and then output to the external interface, i.e., from steps S1 to S7. Wherein, the steps S1, S2, S3, S6 and S7 are data transmission processes, and are not described in detail in the present invention, wherein, the step S4 is to re-read the data read by the information processing module, also perform statistics on the voltage distribution state information, compare the statistics with the read quantity record value, and send the comparison result, the read and write quantity values (percentage value) to the external module together for further processing (generally to the CPU, i.e. to be processed by software, to generate the expected value of the threshold voltage); step S5 is decoding of data error correction code (LDPCDeCode), where it is known whether error correction is successful, and if error correction is failed, re-reading is required, i.e. steps S1-S5 may be repeated, and only if step S5 successfully completes error correction, the data is output to the external interface through steps S6, S7;

in this embodiment of the present invention, before performing the reread operation, the method further includes:

In an embodiment of the present invention, the method further comprises:

Specifically, please refer to fig. 17 again, fig. 17 is a schematic overall flowchart of a reread management method according to an embodiment of the present invention;

as shown in fig. 17, the rereading management method includes:

step S1701: normal read operation;

step 1702: whether there is an uncorrectable error;

specifically, if an uncorrectable error exists, step S1703 is performed; if there is no uncorrectable error, the process proceeds to step S1712: recording the current reading success, and updating a rereading grade record table;

step S1703: whether a rereading grade record table exists;

specifically, during normal read operation, it is determined whether a reread rank record table exists, and if yes, the process proceeds to step S1711: selecting the re-reading grade obtained by table lookup; if not, the process proceeds to step S1704: selecting an initial rereading level;

step S1704: selecting an initial rereading level;

step S1705: carrying out rereading operation;

step S1706: whether there is an uncorrectable error;

specifically, if an uncorrectable error exists, the process proceeds to step S1707; if there is no uncorrectable error, the process proceeds to step S1712: recording the current reading success, and updating a rereading grade record table;

step S1707: whether the number of rereading times is maximum or not;

specifically, if the rereading time is equal to the preset rereading time threshold, determining that the rereading time is the maximum, then step S1713 is performed: recording current reading failure and resetting a rereading grade record table; if the rereading times are smaller than the preset rereading times threshold value, the step S1708 is entered;

step S1708: determining the offset direction according to the voltage distribution state;

specifically, a first cell number in each voltage distribution state in a write stage is obtained, a second cell number in each voltage distribution state in a read stage in a previous re-read is obtained, and an offset direction of each threshold voltage is determined according to the first cell number and the second cell number.

Step S1709: adjusting the step size according to the voltage distribution state;

specifically, a first recorded value corresponding to each voltage distribution state is determined, a second recorded value corresponding to each voltage distribution state is determined, and a difference value between the first state value and the second state value is calculated; determining a stepping amount according to the difference value;

step S1710: determining and setting a threshold voltage;

specifically, the threshold voltage corresponding to each voltage distribution state is determined.

Step S1711: selecting the re-reading grade obtained by table lookup;

specifically, when an uncorrectable error exists, the rereading grade recording table is inquired, the rereading grade is determined, and the first rereading operation is carried out based on the rereading grade;

step S1712: recording the current reading success, and updating a rereading grade record table;

specifically, the updating the rereading level record table includes modifying the initial rereading level of the rereading level record table to the current rereading level.

Step S1713: recording current reading failure and resetting a rereading grade record table;

according to the embodiment of the invention, by tracking the voltage distribution state change condition between the writing and reading of the target data, an effective voltage adjusting direction can be provided for the re-reading process, and the adjustment stepping size of the threshold voltage is provided, so that the re-reading success rate is improved, the re-reading times are integrally reduced, and the integral reading performance of the solid state disk, especially the index of the consistency of the reading performance, is improved.

In an embodiment of the present invention, a reread management method is provided, where the method includes: acquiring the number of first units in each voltage distribution state in a writing-in stage, and determining a first record value corresponding to each voltage distribution state; acquiring the number of second units in each voltage distribution state during the reading stage of the previous re-reading, and determining a second record value corresponding to each voltage distribution state; determining the offset direction of each threshold voltage according to the first unit quantity and the second unit quantity; determining the offset degree of each threshold voltage according to the first recording value and the second recording value; and determining the adjusted threshold voltage according to the offset direction and the offset degree of the threshold voltage, and performing re-reading operation based on the adjusted threshold voltage. By recording each voltage distribution state in the writing stage and the reading stage, adjusting the offset direction and the offset degree of the threshold voltage and determining the adjusted threshold voltage, the embodiment of the invention can improve the overall reading performance of the solid state disk.

Embodiments of the present invention also provide a non-volatile computer storage medium, where the computer storage medium stores computer-executable instructions, which are executed by one or more processors, for example, the one or more processors may execute the rereading management method in any of the above method embodiments, for example, execute the above described steps.

The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the technical solutions mentioned above may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the method according to each embodiment or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for rereading management, the method comprising:

2. The method of claim 1, wherein the first recorded value comprises a first state value and the second recorded value comprises a second state value, and wherein determining the degree of shift for each threshold voltage based on the first recorded value and the second recorded value comprises:

determining a stepping amount according to the difference value;

3. The method of claim 1, wherein determining the shift direction of each threshold voltage according to the first number of cells and the second number of cells comprises:

4. The method of claim 3, wherein determining the shift direction of the threshold voltage corresponding to the next voltage distribution state according to the shift direction of the threshold voltage corresponding to the previous voltage distribution state and by combining the first cell number and the second cell number corresponding to the next voltage distribution state comprises:

5. The method of claim 1, wherein prior to performing the reread operation, the method further comprises:

pre-establishing a rereading grade recording table, wherein the rereading grade recording table comprises at least two rereading grades;

6. The method of claim 5, further comprising:

7. The method of claim 6, further comprising:

after the second re-reading operation is finished, circularly judging whether an uncorrectable error exists or not until the re-reading times reach the maximum or no uncorrectable error exists;

8. A solid state hard disk controller is applied to a solid state hard disk, wherein the solid state hard disk comprises at least one flash memory medium, and the solid state hard disk controller is characterized by comprising a data path processing module which is in communication connection with the at least one flash memory medium of the solid state hard disk;

wherein the data path processing module comprises:

the interface module is used for exchanging data with the flash memory medium;

the cache management module is used for caching data;

9. The solid state hard disk controller of claim 1, wherein the reread information management module comprises:

10. A solid state disk, comprising:

the solid state hard disk controller of claim 8 or 9, wherein the solid state hard disk controller is to perform the reread management method of any of claims 1-7;