CN112560392B

CN112560392B - Method, apparatus and storage medium for processing a circuit layout

Info

Publication number: CN112560392B
Application number: CN202011492348.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Advanced Manufacturing EDA Co Ltd
Current assignee: Advanced Manufacturing EDA Co Ltd
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2021-08-10
Anticipated expiration: 2040-12-16
Also published as: CN112560392A

Abstract

According to example embodiments of the present disclosure, methods, apparatuses, devices and computer-readable storage media for processing a circuit layout are provided. A method for processing a circuit layout includes generating a plurality of sub-operations for performing optical proximity correction on the circuit layout. Each sub-job corresponds to one layout cell of the circuit layout, and specifies one or more operations for optical proximity correction to be performed on the layout cell. The method also includes assigning the plurality of sub-jobs to the plurality of processing devices based on configuration information of the plurality of processing devices and a complexity of the one or more operations. At least one processing device of the plurality of processing devices is configured with accelerated processing resources. The method further includes determining an optically proximity corrected circuit layout based on results of the processing of the plurality of sub-jobs by the plurality of processing devices. In this way, a fast and efficient OPC scheme can be advantageously implemented.

Description

Method, apparatus and storage medium for processing a circuit layout

Technical Field

Embodiments of the present disclosure relate generally to integrated circuits and, more particularly, relate to a method, apparatus, and computer-readable storage medium for processing a circuit layout.

Background

The circuit layout (also simply referred to as layout) is a series of geometric figures converted from a designed and simulated optimized circuit, and comprises physical information data related to devices such as the size of the integrated circuit, the topology definition of each layer and the like. The integrated circuit manufacturer manufactures the mask according to the data. The layout pattern on the mask determines the size of the devices or physical layer of connections on the chip.

As technology nodes of an integrated circuit manufacturing process decrease, distances between target patterns in the integrated circuit decrease, and the density of layout patterns on the mask corresponding to the target patterns increases. Since the light wave is diffracted at the layout pattern of the mask, the actually formed pattern is distorted compared to the layout pattern. When the distance between the target patterns is reduced to a certain level, such distortion causes adjacent target patterns, which should not be connected to each other, to be connected to each other, thereby causing the integrated circuit to fail. For this reason, Optical Proximity Correction (OPC) has been proposed to adjust the layout pattern of a mask in order to form a desired target pattern. However, the process of applying OPC to adjust the layout pattern of the mask consumes a lot of time.

Disclosure of Invention

According to an example embodiment of the present disclosure, a solution for processing a circuit layout is provided.

In a first aspect of the disclosure, a method for processing a circuit layout is provided. The method includes generating a plurality of sub-jobs for performing optical proximity correction on the circuit layout. Each sub-job corresponds to one layout cell of the circuit layout, and specifies one or more operations for optical proximity correction to be performed on the layout cell. The method also includes assigning the plurality of sub-jobs to the plurality of processing devices based on configuration information of the plurality of processing devices and a complexity of the one or more operations. At least one processing device of the plurality of processing devices is configured with accelerated processing resources. The method further includes determining an optically proximity corrected circuit layout based on results of the processing of the plurality of sub-jobs by the plurality of processing devices.

In a second aspect of the disclosure, an electronic device is provided that includes one or more processors; and a storage device for storing the one or more programs which, when executed by the one or more processors, cause the one or more processors to perform the actions. The actions include generating a plurality of sub-jobs for performing optical proximity correction on the circuit layout. Each sub-job corresponds to one layout cell of the circuit layout, and specifies one or more operations for optical proximity correction to be performed on the layout cell. The actions also include assigning the plurality of sub-jobs to the plurality of processing devices based on configuration information of the plurality of processing devices and a complexity of the one or more operations. At least one processing device of the plurality of processing devices is configured with accelerated processing resources. The acts further include determining an optically proximity corrected circuit layout based on results of the processing of the plurality of sub-jobs by the plurality of processing devices.

In some embodiments, assigning the plurality of sub-jobs to the plurality of processing devices based on configuration information of the plurality of processing devices and complexity of the one or more operations comprises: determining, based on configuration information of a plurality of processing devices, a plurality of pairs of processing devices from the plurality of processing devices, each pair of processing devices including a first processing device not configured with accelerated processing resources and a second processing device configured with accelerated processing resources; and if the one or more operations include a first operation and a second operation, wherein the first operation is an operation having a first complexity and the second operation is an operation having a second complexity, the second complexity being higher than the first complexity, assigning each sub-job to a respective pair of the plurality of pairs of processing devices such that the first operation is performed by the first processing device and the second operation is performed by the second processing device.

In some embodiments, assigning the plurality of sub-jobs to the plurality of processing devices based on configuration information of the plurality of processing devices and complexity of the one or more operations comprises: determining a first group of processing devices and a second group of processing devices from the plurality of processing devices based on configuration information of the plurality of processing devices, the first group of processing devices being a group of processing devices that are not configured with accelerated processing resources and the second group of processing devices being a group of processing devices that are configured with accelerated processing resources; assigning a first group of sub-jobs to a first group of processing devices if the first group of sub-jobs in the plurality of sub-jobs includes only a first operation and does not include a second operation, wherein the first operation is an operation having a first complexity and the second operation is an operation having a second complexity, the second complexity being higher than the first complexity; and assigning a second group of sub-jobs to the second group of processing devices if the second group of sub-jobs of the plurality of sub-jobs includes only the second operation and does not include the first operation.

In some embodiments, the method further comprises determining a first complexity based on an operation type and/or a computational load of the first operation; and determining the second complexity based on the operation type and/or the calculation amount of the second operation.

In some embodiments, generating a plurality of sub-jobs for performing optical proximity correction on a circuit layout comprises: acquiring geometric figure information of the layout unit aiming at each sub-operation in the plurality of sub-operations, wherein the geometric figure information indicates the dependency relationship between each geometric figure and the geometric figure combination included in the layout unit; determining a plurality of patterns from the combination of the geometric figures based on the geometric figure information, each pattern including at least one geometric figure belonging to the pattern according to the geometric figure information; and setting each sub-job to specify a predetermined operation for changing at least one geometric figure among the one or more operations to be performed on the plurality of patterns, respectively.

In some embodiments, setting each sub-job to specify that the predetermined operation is to be performed on the plurality of patterns, respectively, includes: determining a reference pattern from a group of patterns if it is determined that the plurality of patterns includes the group of patterns belonging to the same type; each sub-job is set to specify: performing a predetermined operation on the reference pattern to obtain a processing result on the reference pattern; applying the processing result to the remaining patterns of the set of patterns other than the reference pattern, and performing the predetermined operation on the remaining patterns.

In some embodiments, the one or more operations include at least one of: an operation for changing a geometric figure in a layout cell, an optical model simulation operation for the layout cell,

the method comprises the following steps of performing etching model simulation operation on the layout unit, performing chemical mechanical polishing simulation operation on the layout unit, performing convolution operation on the layout unit, or performing regression operation on the layout unit.

In some embodiments, the accelerated processing resources are removably configured to the at least one processing device.

In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements a method according to the first aspect of the present disclosure.

It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:

FIG. 1 shows a schematic diagram of performing OPC on a layout pattern;

FIG. 2 illustrates a schematic diagram of an example architecture in which various embodiments of the present disclosure can be implemented;

FIG. 3 illustrates a schematic diagram of a portion of the example architecture of FIG. 2, in accordance with some embodiments of the present disclosure;

FIG. 4 illustrates an example layout cell according to some embodiments of the present disclosure;

FIG. 5 illustrates an indexing structure for the example layout cell of FIG. 4, in accordance with some embodiments of the present disclosure;

FIG. 6 illustrates a block diagram of a process of allocating sub-jobs, according to some embodiments of the present disclosure;

FIG. 7 illustrates a block diagram of a process of allocating sub-jobs, according to some embodiments of the present disclosure;

FIG. 8 illustrates a flow diagram of an example method for processing a circuit layout, according to some embodiments of the present disclosure; and

FIG. 9 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As mentioned previously, OPC has been proposed to adjust the layout pattern of a mask. In existing OPC computing environments, the computing units used to perform OPC typically utilize or are based on conventional processing resources, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), Field Programmable Gate Arrays (FPGAs), CELL bandwidth engine architecture (CELL BE) processors. In a distributed processing architecture, these computing units are typically implemented as a distributed plurality of clients. These clients typically have the same configuration and are configured with one or more of the conventional processing resources of a CPU, GPU, FPGA, etc.

However, in the prior art solutions, the run time for OPC is still long, which is not conducive to obtaining a large number of results quickly. Therefore, a faster and efficient solution is desired to perform OPC operations for a circuit layout of a mask.

According to an embodiment of the present disclosure, a scheme for processing a circuit layout is provided. In this scheme, a management apparatus generates a plurality of sub-jobs for performing optical proximity correction on a circuit layout. Each sub-job corresponds to one layout cell of the circuit layout, and specifies one or more operations for optical proximity correction to be performed on the layout cell. Then, the management apparatus allocates the plurality of sub-jobs to the plurality of processing apparatuses based on the configuration information of the plurality of processing apparatuses and the complexity of the one or more operations. At least one processing device of the plurality of processing devices is configured with accelerated processing resources. Next, the management apparatus determines the circuit layout subjected to the optical proximity correction based on results of the processing of the plurality of sub-jobs by the plurality of processing apparatuses.

As used herein, the term "accelerated processing resources" or similar terms refer to hardware or software that is capable of fast processing relative to conventional processing resources such as CPUs, GPUs, FPGAs, and the like. The Accelerated Processing Resources (APR) may include, but are not limited to, an Accelerated Processor (APU), an Artificial Intelligence (AI) chip. The AI chip may include, for example, a Tensor Processing Unit (TPU), a neural Network Processing Unit (NPU), and other existing or future developed AI chips. It will be appreciated that such accelerated processing resources are primarily used to increase the computational speed of AI-related applications.

According to the solution presented herein for processing a circuit layout, sub-jobs may be assigned to appropriate processing devices according to the configuration of the processing devices and the characteristics of the plurality of sub-jobs. In this way, the processing resources of the processing device can be better utilized and the processing of the sub-jobs is accelerated. Accordingly, the scheme of the present disclosure can advantageously implement a fast and efficient OPC scheme.

For a better understanding of the solution proposed herein for processing a circuit layout, the principle of OPC is described with reference to fig. 1. Fig. 1 shows a schematic diagram 100 of performing OPC on a layout pattern. It should be understood that fig. 1 only schematically shows a part of the pattern of the circuit layout of the mask (also referred to as "mask layout") to describe the principle of OPC. The layout pattern 110 is an initial pattern of the input mask layout; the target pattern 120 is a pattern desired to be formed on a wafer; the layout pattern 130 is an output pattern subjected to optical proximity correction, which may also be referred to as a "post-OPC pattern".

In the OPC operation, it is necessary to calculate a wafer image W (x, y) according to equation (1):

W(x,y)＝f(m(x,y)) (1)

where f is a physical model describing various phenomena in the lithographic process, which is a function of the mask layout; m (x, y) is a pattern of the input mask layout, such as layout pattern 110 shown in FIG. 1; (x, y) represents coordinates.

One way to compute the wafer image is to use a kernel convolution formula as shown in equation (2):

wherein phi_i(x, y) denotes the ith convolution kernel, i ═ 1,2, …, K, and K is the number of convolution kernels.

The OPC operation is a process as in equation (3), i.e., the mask layout is optimized such that the obtained wafer image W is as close as possible to the target pattern T, e.g., target pattern 120.

Wherein min_mRepresents optimizing m (x, y) so that

At a minimum, N denotes dividing the wafer image W and the target pattern T into N lattices, (x)_j,y_j) Denotes the coordinates of the first lattice and j ═ 1,2, …, N, | | … | | survival_LRefers to the mathematical L-norm.

Since there is no inverse function of f in analytic form, a general OPC method is to find a suitable m (x, y) for equation (3) by an optimization or regression process. The resulting m (x, y) is referred to as the post-OPC pattern, such as the pattern 130 shown in fig. 1.

Meanwhile, the target pattern is derived from the original design layout. In general, OPC optimizes the mask layout to obtain the wafer pattern best suited for the target pattern.

The inventors of the present application have realized that the convolution operation in equation (2) and the regression operation involved in the optimization process in equation (3) are complex operations that require a large amount of computational resources. Both of these operations are particularly well suited to be handled with accelerated processing resources. Therefore, the efficiency of OPC can be improved by performing complex operations such as convolution, regression, and the like using accelerated processing resources.

Moreover, applicants' inventors have also recognized that OPC involves relatively simple operations such as applying geometric rules, logic conditions, and the like, in addition to convolution and regression operations. Thus, in some embodiments, a hybrid architecture may be employed that utilizes accelerated processing resources to perform complex operations while utilizing conventional processing resources to perform simple operations. In this way, a balance of efficiency and cost may be achieved.

Example architecture

Fig. 2 illustrates a schematic diagram of an example architecture 200 in which various embodiments of the present disclosure can be implemented. As shown in FIG. 2, the architecture 200 generally includes a management device 210 and a plurality of processing devices 220-1 through 220-6. For example, the management device 210 may be a server, and the plurality of processing devices 220-1 to 220-6 may be a plurality of clients.

The management device 210 in the architecture 200 may be any device with computing capabilities. As non-limiting examples, the management device 210 may be any type of fixed, mobile, or portable computing device, including but not limited to a desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, multimedia computer, mobile phone, and the like. In some embodiments, all or a portion of the components of the management device 210 may be distributed in the cloud.

The plurality of processing devices 220-1 through 220-6 may also be collectively referred to hereinafter as the plurality of processing devices 220, or individually as the processing devices 220. The processing device 220 and the management device 210 may communicate with each other and transmit data. Data transfer between the management device 210 and the processing device 220 may be based on any suitable form of communication connection, including but not limited to a wide area network (e.g., the internet), a local area network, a private network, a public network, a packet network, a wired network, or a wireless network, such as a connection established via bluetooth, Near Field Communication (NFC), wireless fidelity (Wi-Fi), Worldwide Interoperability for Microwave Access (WiMAX), infrared, 2G/3G/4G/5G, and other future developed technologies, among others.

At least one processing device of the plurality of processing devices 220 may be configured with accelerated processing resources. As an example, processing devices 220-1, 220-2, and 220-3 shown in FIG. 2 are configured with accelerated processing resources. A processing device configured with accelerated processing resources is also referred to as an "accelerated processing device. In addition to accelerated processing resources, accelerated processing devices, such as processing devices 220-1, 220-2, and 220-3, may also be configured with conventional processing resources. Thus, accelerated processing devices may include, but are not limited to: APR, a combination of CPU and APR, a combination of CPU, APR and GPU, a combination of CPU, APR and FPGA, a combination of CPU, APR, GPU and FPGA, and the like.

In some embodiments, the accelerated processing resources may be configured to the processing device in a persistent manner or in a non-removable manner. An accelerated processing resource configured in this manner may be referred to as a non-removable accelerated processing resource. For example, one or more of processing devices 220-1, 220-2, and 220-3 may be configured with accelerated processing resources, e.g., with a TPU, NPU, or APU built in, at factory.

In some embodiments, the accelerated processing resources may be removably configured to the processing device. An accelerated processing resource configured in this manner may be referred to as a removable accelerated processing resource. For example, the accelerated processing resources may be configured to the processing device in the form of an external plug-in. In this way, a processing device that would otherwise have only conventional processing resources can be provided with accelerated processing capabilities when needed. In such embodiments, the architecture 100 may have greater flexibility to configure the processing device 220 according to the throughput of OPC.

The example architecture 200 shown in fig. 2 is a hybrid architecture. Such a hybrid architecture may include processing devices 220-4, 220-5, and 220-6 that are not configured with accelerated processing resources in addition to processing devices 220-1, 220-2, and 220-3 that are configured with accelerated processing resources. Processing devices that are not configured with accelerated processing resources are also referred to as "regular processing devices". Conventional processing equipment may be configured with any suitable conventional processing resources. Thus, a conventional processing device may include, but is not limited to, a combination of a CPU and a GPU, a combination of a CPU and an FPGA, a CPU, a GPU, an FPGA, and the like. It will be appreciated that in some embodiments, a conventional processing device may be configured with accelerated processing resources in a removable manner, thereby becoming an accelerated processing device.

In such a hybrid architecture, an accelerated processing device and a conventional processing device may be used separately for the different complexity operations involved in OPC. In this way, a balance of efficiency and cost may be achieved. Such an embodiment will be described below with reference to fig. 6 and 7.

In the example architecture 200 shown in fig. 2, the number of management devices and processing devices is merely exemplary and is not intended to limit the scope of the present disclosure. For example, in embodiments consistent with the present disclosure, there may be more or fewer processing devices. Further, the number of processing devices configured with and without accelerated processing resources is merely exemplary. For example, in some embodiments, multiple processing devices 220 may each be configured with accelerated processing resources.

The foregoing describes an example architecture 200 in which embodiments according to the present disclosure can be implemented. Fig. 3 illustrates a schematic diagram of a portion 300 of the example architecture 200 of fig. 2, in accordance with some embodiments of the present disclosure. Fig. 3 illustrates data transmission between the management device 210 and the processing device by taking the processing device 220-1 as an example.

The management device 210 is configured to control job assignment and execution of OPC. As shown in fig. 3, the management apparatus 210 may include an execution unit 311 (such as a CPU), an OPC just-in-time compiler 312, and a storage device 313. The management device 210 may receive or locally store OPC data for a mask layout as well as initial mask data. The OPC data may include files, recipes (recipes), models, etc. related to OPC. The initial mask data may include a mask layout.

Management device 210 may divide the mask layout into a plurality of layout cells, each of which may refer to a pattern composed of one or more geometric figures. The management apparatus 210 generates a plurality of sub-jobs for performing OPC on the mask layout. Each sub-job corresponds to a layout cell and specifies one or more operations for OPC to be performed on the layout cell. For example, a runtime compiler may be implemented at management device 210, which may generate execution code for processing device 220 to execute the corresponding sub-job.

The one or more operations specified by the sub-operation may include a convolution operation for the layout cell (e.g., shown in equation (2)), a regression operation for the layout cell (e.g., shown in equation (3)), an operation for changing a geometric figure in the layout cell, an optical model simulation operation for the layout cell, an etching model simulation operation for the layout cell, or a chemical mechanical polishing simulation operation for the layout cell. The operation for changing the geometry in a layout cell may also be referred to as a "geometry operation," which may include various geometric rules or logical operations for changing the size, shape, or distance between different geometries of an individual geometry. Geometric operations may be performed on a set of geometries in a layout cell. An example embodiment of generating a sub-job will be described below with reference to fig. 4 and 5.

To allocate the plurality of sub-jobs to the plurality of processing devices 220, the management device 210 may determine a configuration of each of the plurality of processing devices 220 to determine whether the respective processing device is configured with accelerated processing resources. For example, the management device 210 may query the plurality of processing devices 220 for their configurations, respectively. As another example, the processing device 220 may send a message to the management device 210 to notify of the configuration change when its configuration changes. For example, the processing device 220 may notify the management device 210 when configured with removable accelerated processing resources.

The management device 210 may also determine the complexity of one or more operations specified by each sub-job. The complexity described herein may be related to: the type of operation, the amount of computation involved in the operation or the amount of processing resources required to perform the operation. In some embodiments, the complexity of one or more operations may be determined based on the respective operation type. Among the various operations involved in OPC, a convolution operation, a regression operation, an optical model simulation operation, an etch model simulation operation, or a chemical mechanical polishing simulation operation may be considered a high complexity operation, while a geometry operation may be considered a low complexity operation. Alternatively, in other embodiments, management device 210 may generate sub-jobs depending on the type of operation. For example, the plurality of sub-jobs may include a first group of sub-jobs and a second group of sub-jobs. The first set of sub-operations may specify performing less complex geometric operations on the corresponding layout element, and the second sub-operation may specify performing more complex operations on the corresponding layout element, such as convolution operations, regression operations, optical model simulation operations, etch model simulation operations, or chemical mechanical polishing simulation operations.

Although primarily described herein with reference to complexity determined based on operation type as an example, it should be understood that complexity may also be determined in other ways. For example, the management device 210 may determine the complexity based on the computational amount of the respective operation or by estimating the amount of processing resources required for the operation.

Next, the management apparatus 210 may allocate a plurality of sub-jobs to the plurality of processing apparatuses 220 based on the complexity of the configuration and operation of the plurality of processing apparatuses 220. An example embodiment of allocating a sub-job will be described below with reference to fig. 6 and 7.

As shown in fig. 3, if it is determined that a certain sub-job is assigned to the processing device 220-1, the management device 210 may transmit data related to the sub-job to the processing device 220-1. The data related to the sub-jobs may include: the data of the pattern unit corresponding to the sub-job, the kernel to be used, the function and its parameters, etc.

Memory 322 of processing device 220-1 may send data related to the sub-job to execution unit 321. As shown in fig. 2, the processing device 220-1 is configured with accelerated processing resources so the execution unit 321 can process data using one or more of the vector pattern 331, the matrix pattern 332, and the tensor pattern 333.

Taking the convolution operation as an example, the convolution operation may be converted to a vector matrix multiplication using a Toeplitz matrix. Multiple convolution operations for the same layout cell may be converted to a matrix-matrix multiplication. Accelerated processing resources, such as AI chips, have advantages in employing the topliez matrix over conventional processing resources, such as GPUs or FPGAs. The AI chip may use matrix multi-cells (Multiple Units) to accelerate matrix operations. For example, the TPU has a matrix of multiple units, each cycle of which can perform a 64K Multiply Accumulate (MAC) operation (256x 256x 8b), wherein the MAC operation is a special operation in a digital signal processor or some microprocessor, and the hardware circuit unit performing the operation is called a multiplier accumulator.

The processing device 220-1 transmits the result of the sub-job processing to the management device 210 after processing the sub-job. Although only processing device 220-1 is shown, it should be understood that multiple sub-jobs may be processed in parallel at multiple processing devices 220.

The managing device 210 receives the results of the processing of the plurality of sub-jobs from the plurality of processing devices 220, respectively, and generates an OPC-passed mask layout, which may also be referred to as a post-OPC mask layout, based on these results. As shown in fig. 3, the management device 210 may output data relating to the post-OPC mask layout.

Example of generating a sub-job

In order to generate or arrange a plurality of sub-jobs, the management apparatus 210 needs to perform pattern analysis on the mask layout or layout unit. For example, a pattern analyzer may be implemented at the management device 210.

In pattern analysis, it may be desirable to obtain geometric information for layout cells. Such geometry information may indicate dependencies between the individual geometries and combinations of geometries comprised by the layout cells. One fast and efficient way to obtain geometry information is to index each geometry in a layout cell. In this way, pattern analysis can be performed quickly.

As an example, an R-tree or binary tree may be used to construct an index structure for a layout cell (or the entire mask layout as well) as the geometry information. The R-tree or binary tree may form a single tree or may form a forest while maintaining the hierarchy of the layout. The R-tree described herein refers to a tree-like data structure built for a circuit layout to index the geometry in the layout. The R-tree may include a root node, intermediate nodes, and leaf nodes, with indexes established between the root node and a plurality of intermediate nodes, and indexes established between each intermediate node and a plurality of leaf nodes.

FIG. 4 illustrates an example layout cell 400 according to some embodiments of the present disclosure. The example layout cell 400 shown in FIG. 4 may be considered as one example of a layout cell in a mask layout. The geometries indexed R8-R19 and the pattern comprising a plurality of geometries indexed R1-R7 are shown in fig. 4, which may be considered a combination of geometries. It should be understood that the number and relative positions of the geometries shown in fig. 4 are merely exemplary and are not intended to limit the scope of the present disclosure. FIG. 5 illustrates an indexing structure 500 for the example layout cell of FIG. 4, according to some embodiments of the present disclosure.

The geometries R8-R19 correspond to a single geometry and may constitute leaf nodes in the index structure 500. By analyzing the geometries R8-R19 as leaf nodes, a pattern comprising a plurality of geometries, i.e., forming other nodes in the index structure 500, may be determined. By way of example, by calculating the distances between the geometries R8-R19, it may be determined that the geometries R8-R10 are close to each other (e.g., less than a threshold distance apart) but do not overlap each other. Thus, the geometries R8-R10 may be grouped into a pattern R3. As another example, the geometry R11 overlaps the geometry R12 so they may be grouped into the pattern R4.

Similarly, the geometries R13-R14 may be grouped into a pattern R5; the geometries R15-R16 may be grouped into a pattern R6; the geometries R17-R19 may be grouped into a pattern R7. Unlike the geometries R8-R19, the patterns R3-R7 include a plurality of geometries. As shown in FIG. 5, patterns R3-R7 may constitute intermediate nodes in index structure 500.

The patterns R6 and R7 were grouped into the pattern R1 by analysis of the patterns R3-R7; the patterns R3, R4, and R5 are grouped into R2. As shown in FIG. 5, patterns R1 and R2 may form the root nodes of indexing structure 500.

As can be seen from the above description, by constructing the index structure 500, it can be determined that the layout cell 400 includes a plurality of patterns of geometry, such as the patterns R3-R7 or the patterns R1-R2. As mentioned above, geometric operations such as geometric rules or logical conditions may be performed on a set of geometric figures. Thus, the management apparatus 210 can determine a plurality of patterns, for example, the patterns R3 to R7, on which geometric operations are to be performed, from among the patterns R3 to R7 or the patterns R1 to R2 as geometric combinations. The management apparatus 210 may set sub-jobs corresponding to the layout cell 400 to specify the execution of the geometric operations on the plurality of patterns R3-R7, respectively. As used herein, the term "setting a sub-job to specify an operation" and variations thereof may refer to generating executable instructions for the sub-job in generating the sub-job such that the corresponding operation is performed when the sub-job is processed by a processing device.

The management apparatus 220 may transmit the data of the index structure 500 to the corresponding processing apparatus 220 as a part of the data related to the sub-job shown in fig. 3. Thus, the use of an indexing structure for a mask layout may be parallel across multiple processing devices 220. In this way, the geometric operations involved in the sub-job may be accelerated, thereby facilitating an increase in the processing efficiency of the entire OPC job.

In some embodiments, if the mask layout to be processed is too large, management device 210 may divide the task of building an index structure (e.g., R-tree) into a plurality of subtasks, each subtask being used to build an index structure for a region (e.g., layout cell). These subtasks may be distributed to multiple processing devices 220, so that the index structure for the entire mask layout is built in parallel across multiple processing devices 220.

In some embodiments, the management device 210 (e.g., pattern analyzer) may also classify a plurality of patterns in a layout cell to determine a set of patterns belonging to the same type. For example, the same pattern may be classified into the same type. As another example, scaled patterns may be classified as the same type. If it is determined that a group of patterns belonging to the same type is included in the plurality of patterns, the management apparatus 210 may determine a reference pattern from the group of patterns. The management apparatus 210 in turn can set each sub-job to specify: geometric operations are performed on the reference pattern to obtain a processing result for the reference pattern, and the processing result for the reference pattern is applied to patterns other than the reference pattern in the set of patterns.

In this way, for each type of pattern, a reference pattern can be determined therefrom as a seed. In executing the sub-job, the processing device 220 may perform a geometric operation on each type of reference pattern, and the processing result on the reference pattern may be applied to other patterns of the type. In this way, repeated geometric operations may be reduced, e.g., repeated application of geometric rules to the same pattern may be avoided. Additionally, in some embodiments, the process of performing geometric operations on different types of patterns may be parallel.

Example of allocating a sub-job

After generating the plurality of sub-jobs, the management apparatus 210 allocates the sub-jobs to the processing apparatuses 220 based on the configurations of the plurality of processing apparatuses 220 and the complexity of the operations specified by the sub-jobs. In some embodiments, multiple processing devices 220 may each be configured with accelerated processing resources. In such an embodiment, the management apparatus 210 may assign each sub-job to a corresponding one of the processing apparatuses.

In some embodiments, some processing devices of plurality of processing devices 220 may be configured with accelerated processing resources, while other processing devices may not be configured with accelerated processing resources. In such embodiments, the management device 210 may pair or group the plurality of processing devices 220.

In some embodiments, the management device 210 may pair an accelerated processing device with a conventional processing device. Each pair of processing devices may be used to process a respective one or more sub-jobs. The accelerated processing device and the regular processing device of each pair of processing devices may cooperatively perform one or more operations in the assigned sub-job.

FIG. 6 illustrates a block diagram of a process 600 for allocating sub-jobs, according to some embodiments of the present disclosure. As shown in FIG. 6, the management device 210 may organize the plurality of processing devices 220 shown in FIG. 2 into pairs of processing devices, where a first pair 611 of the processing devices may include a processing device 220-1 configured with accelerated processing resources and a processing device 220-4 not configured with accelerated processing resources; the second pair 612 of processing devices may include a processing device 220-2 configured with accelerated processing resources and a processing device 220-5 not configured with accelerated processing resources; the third pair 613 of processing devices may include a processing device 220-3 configured with accelerated processing resources and a processing device 220-6 not configured with accelerated processing resources.

If each sub-job includes operations of different complexity, the management device 210 may assign each sub-job to a pair of processing devices such that operations of high complexity are performed by an accelerated processing device thereof and operations of low complexity are performed by a regular processing device thereof. For example, the management device 210 may specify, in a file or an instruction for job assignment, that an operation with high complexity is performed by an accelerated processing device, and an operation with low complexity is performed by a conventional processing device.

As shown in FIG. 6, sub-job 601 may be assigned to a first pair 611 of processing devices, sub-job 602 may be assigned to a second pair 612 of processing devices, and sub-job 603 may be assigned to a third pair 613 of processing devices. By way of example, if the sub-job 601 includes a convolution operation, a regression operation, an optical model simulation operation, an etch model simulation operation, or a chemical mechanical polishing simulation operation and a geometry operation, the convolution operation, the regression operation, the optical model simulation operation, the etch model simulation operation, or the chemical mechanical polishing simulation operation may be performed by the processing tool 220-1, and the geometry operation may be performed by the processing tool 220-4. For example, management device 210 may specify, in a file or instructions for job assignment, that convolution and regression operations be performed by processing device 220-1, and that geometry operations be performed by processing device 220-4.

It should be noted that both the optical model simulation and the etching model simulation operation may be implemented by using MATLAB, for example, the chemical mechanical polishing simulation operation is implemented by using monte carlo simulation, which may be implemented by using the existing simulation model, and details are not described in the embodiments of the present invention.

The results of each pair of processing devices processing the corresponding sub-job may be sent back to the management device 210. The management device 210 may determine an OPC-subjected mask layout based on the results from each pair of processing devices.

Although speeding up processing resources can lead to a great optimization of processing speed, it is expensive compared to conventional processing resources. In such embodiments, the flexibility of the hybrid architecture may be exploited by pairing an accelerated processing device with a conventional processing device. In this way, a balance of efficiency and cost may be achieved.

In other embodiments, the management device 210 may group the accelerated processing device with a conventional processing device. Accordingly, a plurality of sub-jobs for performing OPC on a mask layout may also be grouped. Each group of sub-jobs may include operations of the same complexity and are assigned to a respective group of processing devices.

FIG. 7 illustrates a block diagram of a process 700 for allocating sub-jobs, according to some embodiments of the present disclosure. As shown in FIG. 7, the management device 210 may organize the plurality of processing devices 220 shown in FIG. 2 into multiple groups of processing devices, where a first group 730 of processing devices may include processing devices 220-4, 220-5, and 220-6 that are not configured with accelerated processing resources and a second group 740 of processing devices may include processing devices 220-1, 220-2, and 220-3 that are configured with accelerated processing resources.

The first group 710 of sub-jobs generated by management device 210 may include sub-jobs 711, 712, and 713. Each sub-job in the first group 710 of sub-jobs may comprise only low complexity operations, e.g. only geometric operations. The management device 210 may assign the first group 710 of sub-jobs to the first group 730 of processing devices, i.e., processing devices that are not configured with accelerated processing resources. For example, as shown in FIG. 7, sub-jobs 711, 712, and 713 are assigned to processing devices 220-4, 220-5, and 220-6, respectively.

The management device 210 may receive the processing results of the first group 710 of sub-jobs from the first group 730 of processing devices. The management device 210 may also reconstruct or organize the data for subsequent OPC steps based on the processing results.

Management device 210 may generate a second set 720 of sub-jobs that includes sub-jobs 721, 722, and 723. Each sub-job of the second set 720 of sub-jobs may include only highly complex operations, such as only one or more of convolution operations, regression operations, optical model simulation operations, etch model simulation operations, or chemical mechanical polishing simulation operations. Management device 210 may assign second group 720 of sub-jobs to second group 740 of processing devices, i.e., processing devices configured with accelerated processing resources. For example, as shown in FIG. 7, sub-jobs 721, 722, and 723 may be allocated to processing devices 220-1, 220-2, and 220-3, respectively.

The management device 210 may in turn receive the processing results of the second group 720 of sub-jobs from the second group 740 of processing devices. The management device 210 may determine the OPC-passed mask layout based on these processing results and the previously received processing results of the first group 710 of sub-jobs.

The number of processing devices and sub-jobs shown in fig. 7 is merely illustrative and not intended to be limiting. In some embodiments, the number of sub-jobs of the first group 710 may be the same as the number of sub-jobs of the second group 720. In some embodiments, the number of sub-jobs of the first group 710 may be different from the number of sub-jobs of the second group 720.

Additionally, the area of the layout cell corresponding to each of the first group 710 of sub-jobs may be different from the area of the layout cell corresponding to each of the second group 720 of sub-jobs. For example, the management device 210 may optimize the area of the layout cell corresponding to each group of sub-jobs based on the computing power of the corresponding processing device.

The example process 700 described above constitutes a sub-job loop. In the sub job loop shown in fig. 7, the management apparatus 210 allocates the sub job having a low complexity first and reallocates the sub job having a high complexity, but it should be understood that this is merely exemplary. In some embodiments, for one sub-job cycle, the management apparatus 210 may allocate the sub-job with high complexity first and allocate the sub-job with low complexity again. In other embodiments, the management device 210 may simultaneously allocate a sub-job with high complexity and a sub-job with low complexity.

It will be appreciated that in such embodiments, the less complex sub-jobs (e.g., first set 710 of sub-jobs) and the more complex sub-jobs (e.g., second set 720 of sub-jobs) form a batch of sub-jobs. The management device 210 may cause different groups of processing devices to always be running by allocating different batches of sub-jobs. For example, after the first group 730 of processing devices has completed processing the first group 710 of sub-jobs, the management device 210 may assign the next batch of sub-jobs with low complexity to the first group 710 of sub-jobs.

By grouping processing devices according to accelerated processing devices and conventional processing devices, and grouping sub-jobs according to complexity, the flexibility of the hybrid architecture can be leveraged. In this way, the processing device can continuously process the sub-job for OPC. Therefore, in such an embodiment, the processing efficiency of OPC can be further improved.

Example methods and example embodiments

FIG. 8 illustrates a flow diagram of an example method 800 for processing a circuit layout, according to some embodiments of the present disclosure. The method 800 may be implemented by the management device 210 shown in fig. 2. For ease of discussion, the method 800 will be described in conjunction with FIG. 2.

At block 810, management device 210 generates a plurality of sub-jobs for performing optical proximity correction on a circuit layout (e.g., a mask layout). Each sub-job corresponds to one layout cell of the circuit layout, and specifies one or more operations for optical proximity correction to be performed on the layout cell. For example, the one or more operations may include the convolution operation, regression operation, optical model simulation operation, etch model simulation operation, chemical mechanical polishing simulation operation, or geometric operation described above.

In some embodiments, the management device 210 may obtain the geometry information of the layout cells for each sub-job. Such geometry information may indicate dependencies between the individual geometries and combinations of geometries comprised by the layout cells. For example, the index structure 500 may be obtained as the geometry information by indexing each geometry included in the layout cell. The management apparatus 210 may determine a plurality of patterns of layout cells, such as the patterns R3 through R7 shown in fig. 5, from the geometry combinations based on the geometry information. Each pattern comprises at least one geometry belonging to the pattern according to the geometry information. The management apparatus 210 may set each sub-job to specify a predetermined operation for changing at least one geometric figure among one or more operations to be performed on the plurality of patterns, respectively. In some embodiments, if it is determined that a group of patterns belonging to the same type is included in the plurality of patterns, the management apparatus 210 may determine a reference pattern from the group of patterns. The management device 210 may set each sub-job configuration to specify: performing a predetermined operation on the reference pattern to obtain a processing result on the reference pattern; and performing a predetermined operation on the remaining patterns except the reference pattern in the group of patterns by applying the processing result to the remaining patterns.

At block 820, the management device 210 assigns a plurality of sub-jobs to the plurality of processing devices 220 based on the configuration information of the plurality of processing devices 220 and the complexity of the one or more operations. At least one processing device of the plurality of processing devices 220 is configured with accelerated processing resources. For example, processing devices 220-1, 220-2, and 220-3 shown in FIG. 2 are configured with accelerated processing resources. The accelerated processing resources may include, but are not limited to, APUs, AI chips, and the like. The AI chips may include, for example, TPU, NPU, and other existing or future developed AI chips.

In some embodiments, the accelerated processing resources are removably configured to the at least one processing device. For example, a TPU, NPU, or APU is configured in the form of an external plug-in to one or more of processing devices 220-1, 220-2, and 220-3.

In some embodiments, the accelerated processing resources are non-removably configured to the at least one processing device. For example, one or more of processing devices 220-1, 220-2, and 220-3 have an accelerated processing resource, such as a TPU, NPU, or APU, built in.

In some embodiments, the management device 210 may determine a plurality of pairs of processing devices from the plurality of processing devices 220 based on configuration information of the plurality of processing devices 220. Each pair of processing devices includes a first processing device that is not configured with accelerated processing resources and a second processing device that is configured with accelerated processing resources. For example, the management device 210 may determine a plurality of pairs of processing devices shown in fig. 6.

If the one or more operations include a first operation having a first complexity and a second operation having a second complexity, the second complexity being higher than the first complexity, the management device 210 may assign each sub-job to a respective pair of the plurality of pairs of processing devices such that the first operation is performed by the first processing device and the second operation is performed by the second processing device. For example, each of the sub-jobs 601, 602, and 603 shown in fig. 6 includes convolution and regression operations of high complexity and geometric operations of low complexity. The sub-jobs 601, 602, and 603 may be respectively assigned to a plurality of pairs of processing devices.

In some embodiments, the management device 210 may determine the first group of processing devices and the second group of processing devices from the plurality of processing devices 220 based on configuration information of the plurality of processing devices 220. The first set of processing devices may be a set of processing devices that are not configured with accelerated processing resources and the second set of processing devices may be a set of processing devices that are configured with accelerated processing resources. If a first group of sub-jobs in the plurality of sub-jobs includes only first operations having a first complexity and does not include second operations having a second complexity, the second complexity being higher than the first complexity, the management device 210 may assign the first group of sub-jobs to a first group of processing devices. If a second group of sub-jobs of the plurality of sub-jobs includes only the second operation and does not include the first operation, the management apparatus 210 may assign the second group of sub-jobs to a second group of processing apparatuses.

As an example, the management device 210 may determine a first group 730 of processing devices and a second group 740 of processing devices. The plurality of sub-jobs may include a first group 710 of sub-jobs and a second group 720 of sub-jobs. The first set 710 of sub-jobs may include only geometric operations and the second set 720 of sub-jobs may include only one or more of convolution operations, optical model simulation operations, etch model simulation operations, chemical mechanical polishing simulation operations, and regression operations. The management device 210 may assign a first group 710 of sub-jobs to a first group 730 of processing devices and a second group 720 of sub-jobs to a second group 740 of processing devices. In some embodiments, the second set of sub-jobs is generated after the first set of sub-jobs is executed. For example, the second set 720 of sub-jobs illustrated in FIG. 7 that include one or more of convolution operations, optical model simulation operations, etch model simulation operations, or chemical mechanical polishing simulation operations and regression operations are generated after the first set 710 of sub-jobs that include geometry operations are performed.

In some embodiments, the management device 210 may determine the first complexity based on an operation type and/or a computational load of the first operation; and determining the second complexity based on the operation type and/or the calculation amount of the second operation. In some embodiments, the first complexity and the second complexity may be determined based on respective operation types. For example, the geometric operations may be low complexity operations, while the convolution operations, optical model simulation operations, etch model simulation operations, chemical mechanical polishing simulation operations, and regression operations may be high complexity operations.

At block 830, the management device 210 determines the circuit layout that is subject to optical proximity correction based on the results of the processing of the plurality of sub-jobs by the plurality of processing devices 220. For example, the management device 210 may generate post-OPC mask data as shown in FIG. 3.

In another aspect of the present disclosure, a method for performing OPC is also provided. The method may be implemented by processing device 220 and may include the actions described above with respect to processing device 220.

Example apparatus

Fig. 9 illustrates a schematic block diagram of an example device 900 that may be used to implement embodiments of the present disclosure. The device 900 may be used to implement the management device 210 or the processing device 220 of fig. 1. As shown, device 900 includes a Central Processing Unit (CPU)901 that can perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)902 or loaded from a storage unit 908 into a Random Access Memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The CPU 901, ROM 902, and RAM 903 are connected to each other via a bus 904. An input/output (I/O) interface 905 is also connected to bus 904.

A number of components in the device 900 are connected to the I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, and the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, optical disk, or the like; and a communication unit 909 such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The processing unit 901 performs the various methods and processes described above, such as the method 800. For example, in some embodiments, method 800 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 900 via ROM 902 and/or communications unit 909. When the computer program is loaded into RAM 903 and executed by CPU 901, one or more steps of method 800 described above may be performed. Alternatively, in other embodiments, CPU 901 may be configured to perform method 800 by any other suitable means (e.g., by way of firmware).

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), and the like.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method of processing a circuit layout, comprising: generating a plurality of sub-jobs for performing optical proximity correction on the circuit layout, each sub-job corresponding to one layout cell of the circuit layout, and specifying one or more operations for optical proximity correction to be performed on the layout cell; allocating the plurality of sub-jobs to a plurality of processing devices based on configuration information of the plurality of processing devices and a complexity of the one or more operations, at least one of the plurality of processing devices configured with accelerated processing resources; and determining an optically proximity corrected circuit layout based on results of the processing of the plurality of sub-jobs by the plurality of processing devices;

wherein assigning the plurality of sub-jobs to a plurality of processing devices based on the configuration information of the plurality of processing devices and the complexity of the one or more operations comprises: determining, based on the configuration information for the plurality of processing devices, a plurality of pairs of processing devices from the plurality of processing devices, each pair of processing devices comprising a first processing device not configured with the accelerated processing resources and a second processing device configured with the accelerated processing resources; and the one or more operations include a first operation and a second operation, wherein the first operation is an operation having a first complexity, the second operation is an operation having a second complexity, the second complexity being higher than the first complexity, then the each sub-job is assigned to a respective pair of the plurality of pairs of processing devices such that the first operation is performed by the first processing device and the second operation is performed by the second processing device.

2. The method of claim 1, wherein assigning the plurality of sub-jobs to a plurality of processing devices based on the configuration information of the plurality of processing devices and a complexity of the one or more operations comprises: determining, based on the configuration information for the plurality of processing devices, a first set of processing devices and a second set of processing devices from the plurality of processing devices, the first set of processing devices being a set of processing devices that are not configured with the accelerated processing resources and the second set of processing devices being a set of processing devices that are configured with the accelerated processing resources; a first group of sub-jobs in the plurality of sub-jobs comprises only a first operation and does not comprise a second operation, wherein the first operation is an operation with a first complexity, the second operation is an operation with a second complexity, and the second complexity is higher than the first complexity, and the first group of sub-jobs is allocated to the first group of processing devices; and a second group of sub-jobs of the plurality of sub-jobs including only the second operation and not the first operation, then assigning the second group of sub-jobs to the second group of processing devices.

3. The method of claim 1 or 2, further comprising: determining the first complexity based on an operation type and/or a calculation amount of the first operation; and determining the second complexity based on an operation type and/or a calculation amount of the second operation.

4. The method of claim 1, wherein generating the plurality of sub-jobs for performing optical proximity correction on the circuit layout comprises: acquiring geometric figure information of the layout unit aiming at each sub-operation in the plurality of sub-operations, wherein the geometric figure information indicates the dependency relationship between each geometric figure and each geometric figure combination included in the layout unit; determining a plurality of patterns from the combination of geometries based on the geometry information, each pattern comprising at least one geometry belonging to the pattern according to the geometry information; and setting each sub-job to specify a predetermined operation for changing the at least one geometric figure among the one or more operations to be performed on the plurality of patterns, respectively.

5. The method of claim 4, wherein setting the each sub-job to specify that the predetermined operation is to be performed on the plurality of patterns, respectively, comprises: determining that a group of patterns belonging to the same type is included in the plurality of patterns, and determining a reference pattern from the group of patterns; setting the each sub-job to specify: performing the predetermined operation on the reference pattern to obtain a processing result of the reference pattern; and performing the predetermined operation on the remaining patterns of the group of patterns other than the reference pattern by applying the processing result to the remaining patterns.

6. The method of claim 1, wherein the one or more operations comprise at least one of: an operation for changing the geometric figure in the layout unit, an optical model simulation operation for the layout unit, an etching model simulation operation for the layout unit, a chemical mechanical polishing simulation operation for the layout unit, a convolution operation for the layout unit, or a regression operation for the layout unit.

7. The method of claim 1, wherein the accelerated processing resources are removably configured to the at least one processing device.

8. An electronic device, the device comprising: one or more processors; and storage for storing one or more programs that, when executed by the one or more processors, perform actions comprising: generating a plurality of sub-jobs for performing optical proximity correction on a circuit layout, each sub-job corresponding to one layout cell of the circuit layout, and specifying one or more operations for optical proximity correction to be performed on the layout cell; allocating the plurality of sub-jobs to a plurality of processing devices based on configuration information of the plurality of processing devices and a complexity of the one or more operations, at least one of the plurality of processing devices configured with accelerated processing resources; and determining an optically proximity corrected circuit layout based on results of the processing of the plurality of sub-jobs by the plurality of processing devices;

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-7.