CN112560369A - Memory design method, device, terminal and storage medium - Google Patents
Memory design method, device, terminal and storage medium Download PDFInfo
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Abstract
The embodiment of the invention relates to the technical field of communication, and discloses a memory design method and device. In the invention, the memory design method comprises the following steps: determining attribute information of a memory to be designed according to the memory creating instruction; displaying a preset memory unit module in the first area according to the screening instruction; selecting the memory unit modules displayed in the first area according to the attribute information, generating one or more memory design schemes and displaying the memory design schemes in the second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form; and splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed. By the technical means, the graphical memory chip design is realized, the design process of the memory chip is concise and clear, and the memory design efficiency and the later maintenance efficiency are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a memory design method, a memory design device, a terminal and a storage medium.
Background
With the development of technology, miniaturization of various terminals is an important part for improving user experience. However, the miniaturization and miniaturization of the terminal and the integration of the electronic circuit cannot be separated, and people's life increasingly depends on the electronic products due to the endless evolution of various electronic products, so that the demand for chips is also increasing. The improvement of chip design and production efficiency is an urgent problem to be solved by various chip manufacturers.
The inventors have found that in the related art, engineers need to manually write chip code, such as Verilog code, using a computer to design the memory portion of the chip. The design mode has the disadvantages of low design efficiency, high requirement on designers and the like. Meanwhile, the maintenance of the compiled code document in the later production process is difficult.
Disclosure of Invention
The embodiment of the invention aims to provide a memory design method, which realizes the design of a graphical memory chip, so that the design process of the chip becomes simple and clear, and the design efficiency and the later maintenance efficiency of the chip are improved.
To solve the foregoing technical problem, an embodiment of the present invention provides a memory design method, including: determining attribute information of a memory to be designed according to the memory creating instruction; displaying a preset memory unit module in the first area according to the screening instruction; selecting the memory unit modules displayed in the first area according to the attribute information, generating a plurality of memory design schemes and displaying the memory design schemes in the second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form; and splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed.
An embodiment of the present invention further provides a memory design apparatus, including: the attribute determining module is used for determining the attribute information of the memory to be designed according to the memory creating instruction; the first display module is used for displaying a preset memory unit module in the first area according to the screening instruction; the second display module is used for selecting the memory unit modules displayed in the first area according to the attribute information, generating a plurality of memory design schemes and displaying the memory design schemes in the second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form; and the code processing module is used for splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate the design codes of the memory to be designed.
An embodiment of the present invention further provides a terminal, including: a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the memory design method.
The embodiment of the invention also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the memory design method.
Compared with the prior art, the size of the memory to be designed is displayed in a visual mode, a user can visually select the existing memory unit modules for splicing, the background automatically generates the design codes of the memory to be designed according to the spliced scheme, and the efficiency of memory design is improved.
In addition, in this embodiment, splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate the design code of the memory to be designed includes: determining the width and the address depth of a main chip of a memory to be designed according to a memory creating instruction; splicing the widths of the memory unit modules in the second area according to the width of the main chip; and splicing the address depth of the memory unit module in the second area according to the address depth of the main chip. By the technical means, the width and the address depth of the memory are automatically spliced, and the efficiency of designing the memory by a user is further improved.
In addition, in this embodiment, displaying the preset memory unit module in the first area according to the filtering instruction includes: the selectable memory cell modules that generate the memory design are marked according to the first screening instruction. Through the technical means, the required memory unit module is automatically provided for the user according to the rule selected by the user, and the efficiency of designing the memory by the user is further improved.
In addition, in this embodiment, after selecting the memory cell module displayed in the first area according to the memory creation instruction, generating a plurality of memory design schemes and displaying the memory design schemes in the second area, the method further includes: determining a replaced memory unit module according to the template selection instruction and displaying the memory unit module to be selected; wherein the memory cell module to be selected is smaller than or equal to the size of the replaced memory cell module. Through the technical means, a user can adjust the automatically generated memory scheme according to the requirement, so that the memory design can be more flexible and the user requirement can be better met.
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One or more embodiments are illustrated by the corresponding figures in the drawings, which are not meant to be limiting.
FIG. 1 is a flow chart of a memory design method according to a first embodiment of the invention;
FIG. 2 is a flow chart of a memory design method according to a second embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a memory layout apparatus according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a terminal according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be mutually incorporated and referred to without contradiction.
A first embodiment of the present invention relates to a memory design method. The specific process is shown in fig. 1, and comprises the following steps: determining attribute information of a memory to be designed according to the memory creating instruction; displaying a preset memory unit module in the first area according to the screening instruction; selecting the memory unit modules displayed in the first area according to the attribute information, generating a plurality of memory design schemes and displaying the memory design schemes in the second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form; and splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed.
The implementation details of the memory design method of this embodiment are specifically described below, and the following description is only provided for facilitating understanding of the implementation details, and is not necessary for implementing this embodiment, and the execution subject of this embodiment is a terminal device interacting with a user.
The memory design method in this embodiment is shown in fig. 1, and specifically includes:
Specifically, when a user starts to create a memory to be designed, a memory creation instruction is first input, and parameters carried in the memory creation instruction include: memory type, address depth, port width and direction, etc. For different application scenarios, the requirements for memory width and depth or the requirements for power consumption and area often vary greatly.
In one example, a parameter list of a memory to be designed may be displayed in an interactive interface according to a memory creation instruction, port information of the memory may be displayed in a form, and customizable contents may be displayed in a form of a selectable menu, for example, attributes such as functions and polarities of ports.
In a specific implementation, the memory creation instruction may determine the attribute information of the memory to be designed through the memory creation instruction by uploading a file. The file carries attribute information of a memory to be designed, and the attribute information comprises: memory name, depth, width type, port information, etc.
And 102, displaying a preset memory unit module in the first area according to the screening instruction.
Specifically, since the types of the memories are limited, in some cases, a single memory cannot satisfy the requirements of the main chip. Therefore, it is necessary to combine a plurality of memories to obtain the memory required by the main chip. The preset parameters of the memory unit module are consistent with the parameters of the memory which can be produced by a manufacturer, and the design codes of the memory corresponding to the manufactured memory unit module are stored in a database of the terminal in advance. And the terminal equipment displays the currently available memory unit modules in a list form in a first area on the interactive interface. And a process library option is displayed in the first area and used for selecting a process library required to be used by the current design memory from a pre-uploaded memory process library. Different process libraries contain different types of memory cell modules. Further, a user may select a memory cell module for use in automatically generating a memory design.
In one example, after the user inputs an instruction to select a process library, all memory cell modules in the process library are displayed in the list in the first area, and the memory cell modules used for memory design can be further marked in the table through a screening instruction.
In a specific implementation, in addition, in the table, the memory unit modules displayed in the first area may be further filtered and displayed by inputting a keyword. For example, if an instruction of inputting 64 and 48 in the width input window and the depth input window of the table is received, the memory unit modules with the width of 64 and 48 in the process library are filtered out and displayed in the list of the first area according to the instruction.
Specifically, the size of the memory to be designed, i.e., the link width and the address depth, is determined according to the attribute information. And then, splicing the memory unit modules displayed in the first area, namely selecting a certain number of memory unit modules, and splicing the sizes of the memory unit modules to ensure that the widths and the depths of the spliced memory unit modules are consistent with the size of the memory to be designed. Meanwhile, the memory unit modules selected for splicing also need to meet the attribute requirements of the memory to be designed.
In practical application, one or more memory design schemes are generated and displayed respectively, the number of the generated schemes can be preset by a user, the external outline of the memory design scheme is determined by the dimension outline determined by the dimension of the memory to be designed, the external outline of the memory to be designed and the external outline of the memory unit module are displayed in the second area in a rectangular frame mode according to the dimension, and the width and the depth of the memory unit module in the design scheme are spliced and combined to obtain a rectangular outline with the same dimension as the external outline.
In one example, for the automatically generated memory design scheme, the user may further perform customized modification, receive a replacement instruction of the user on the graphically displayed memory design scheme, determine a replaced memory unit module, screen out, according to the size of the current memory unit module, from the memory unit modules displayed in the first region, other memory unit modules that meet the attribute in the memory creation instruction and have the same size or a smaller size, and display the memory unit modules in the second region in the form of a selectable menu, then receive a selection instruction input by the user again, and display the memory unit modules determined by the user in the second region after replacing the memory unit modules in the automatically generated memory design scheme.
In another example, if a user inputs a power consumption-first or area-first instruction before creating a memory design, a memory design with less power consumption or area is preferentially displayed when displaying a generated memory design.
And 104, splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed.
Specifically, after a memory design scheme is determined, codes of a memory to be designed are generated according to the spliced memory unit modules in the scheme after the memory design scheme is determined.
In one example, during the splicing, two parameters of the size of the memory to be designed are determined according to the width and the address depth of the main chip of the memory to be designed, and then the address depth is analyzed to determine the address corresponding to the width of each memory unit module. When each memory unit module has more than one port, the address corresponding to each port needs to be determined.
In practical applications, it is assumed that the current memory to be designed, i.e. the bit width of the target chip is 32 bits, and the depth is 5 bits, i.e. 2^5 ^ 32 addresses can be addressed. The user selects two bits with width of 16, and the memory unit modules with the depth of 4 bits, namely 2^4 ^ 16 addresses can be addressed to splice to obtain the memory to be designed. In the splicing process, the address depth of the main chip needs to be decoded, which means that after partial high-order addresses of the main chip participate in decoding, the partial high-order addresses are respectively connected to the chip selection ends of the memory unit modules, so that the spliced memory is selected. In this example, 4-0 bits of the target chip address port are mapped to 4-0 bits of the two memory cell modules, respectively. The decoding is performed by the 5 th bit of the target chip address port, and when the 5 th bit is 0, the first block memory unit module is valid, and when the 5 th bit is 1, the second block memory unit module is valid.
Compared with the prior art, the embodiment displays the outline of the memory to be designed and the memory unit module selected during design in the graphical interactive interface, visually displays the size of the memory to a user, and automatically generates the design code of the memory to be designed according to the spliced scheme at the background, so that the efficiency of memory design is improved.
A second embodiment of the present invention relates to a memory design method. The second embodiment is different from the first embodiment in that: in a second embodiment of the present invention, after displaying the preset memory unit module in the first area according to the filtering instruction, the method further includes: when the memory creating instruction indicates that the memory to be designed is generated in the user-defined mode, displaying the size outline of the memory to be designed in the third area according to the memory creating instruction; displaying the selected memory unit module in the size outline of the memory to be designed according to the template selection instruction; the size of the memory unit module displayed in the dimension outline of the memory to be designed is determined according to the connecting line width and the address depth of the memory unit module; and after the areas in the size outline of the memory to be designed are completely distributed, splicing the memory unit modules displayed in the first area and generating a design code of the memory to be designed.
The implementation details of the memory design method of this embodiment are specifically described below, and as shown in fig. 2, the implementation details include:
Step 201 and step 202 are the same as step 101 and step 102 in the first embodiment of the present invention, and details of implementation have been specifically described in the first embodiment and are not described herein again.
In step 203, the dimension profile of the memory to be designed is displayed in the third area according to the memory creation instruction.
Specifically, the memory design scheme in this embodiment is created manually by the user, and the terminal displays only the memory design scheme created by the user in a graphical manner. And determining the size of the memory to be designed, namely the width of the connecting line and the depth of the address according to the attribute information in the memory creating instruction.
In step 204, the selected memory unit module is displayed in the size profile of the memory to be designed according to the template selection instruction.
Specifically, after the memory design is started, an instruction of a user for selecting an unallocated area in a size outline of a memory to be designed is received, then a currently selectable memory unit module is displayed in a third area in a menu form, and after the selection instruction input by the user is received, the outline of the selected memory unit module is displayed in the size outline of the memory to be designed.
In step 205, after the regions in the size profile of the memory to be designed are allocated, the memory unit modules displayed in the first region are spliced to generate the design code of the memory to be designed.
Specifically, each time a user selects a new memory cell module, the new memory cell module occupies a region in a portion of the dimension outline, the occupied region indicates that the dimension is already allocated, when all regions are allocated, the memory design scheme is complete, and the user can determine the memory design scheme and input an instruction for generating the memory to be designed after all regions are allocated. And after the memory design scheme is determined, generating codes of the memory to be designed according to the memory unit modules in the splicing scheme.
Compared with the prior art, in the embodiment, the outline of the memory to be designed and the memory unit module selected during design are displayed in the graphical interactive interface, so that the size of the memory is visually displayed to a user, meanwhile, the memory unit module with the parameters meeting the preset rule can be automatically selected according to the specific requirements of the user, the design code of the memory to be designed is generated after the memory unit modules are spliced automatically at the background, and the efficiency of memory design is further improved.
A third embodiment of the present invention relates to a memory design apparatus, as shown in fig. 3, including:
an attribute determining module 301, configured to determine attribute information of a memory to be designed according to a memory creation instruction.
The first display module 302 is configured to display a preset memory unit module in the first area according to the filtering instruction.
A second display module 303, configured to select a memory cell module displayed in the first region according to the attribute information, generate a plurality of memory design schemes, and display the memory design schemes in the second region; the second area comprises a memory display area used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame mode.
And the code processing module 304 is configured to splice memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed.
In an example, the code processing module 304 is specifically configured to determine, according to the memory creation instruction, a connection width and an address depth of a main chip of the memory to be designed; splicing the connection line width of the memory unit module in the second area according to the connection line width of the main chip; and splicing the address depth of the memory unit module in the second area according to the address depth of the main chip.
In an example, the first display module 302 is specifically configured to preferentially display the memory unit modules with lower power consumption or the memory unit modules with smaller size in the first area according to the first filtering instruction; and marking the selectable memory unit modules generating the memory design scheme according to the second screening instruction.
In one example, the second display module 303 is further configured to determine a replaced memory cell module according to the template selection instruction and display the memory cell module to be selected; the memory unit module to be selected and the replaced memory unit module have the same size.
It should be understood that the present embodiment is a virtual device embodiment corresponding to the first embodiment and the second embodiment, and the present embodiment can be implemented in cooperation with the first embodiment or the second embodiment. The related technical details mentioned in the first embodiment or the second embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment or the second embodiment.
It should be noted that, all the modules involved in this embodiment are logic modules, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, a unit which is not so closely related to solve the technical problem proposed by the present invention is not introduced in the present embodiment, but this does not indicate that there is no other unit in the present embodiment.
Since the first and second embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the first and second embodiments. The related technical details mentioned in the first embodiment and the second embodiment are still valid in this embodiment, and the technical effects achieved in the first embodiment and the second embodiment can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the first embodiment and the second embodiment.
A fourth embodiment of the invention relates to a server, as shown in fig. 4, comprising at least one processor 401; and a memory 402 communicatively coupled to the at least one processor 401; the memory 402 stores instructions executable by the at least one processor 401, and the instructions are executed by the at least one processor 401, so that the at least one processor 401 can execute the memory design method in the first or second embodiment.
Where the memory 402 and the processor 401 are coupled by a bus, which may include any number of interconnected buses and bridges that couple one or more of the various circuits of the processor 401 and the memory 402 together. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 401 may be transmitted over a wireless medium via an antenna, which may receive the data and transmit the data to the processor 401. The processor 401 is responsible for managing the bus and general processing and may provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory 402 may be used to store data used by processor 401 in performing operations.
A fifth embodiment of the present invention relates to a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.
That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for practicing the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A memory design method, comprising:
determining attribute information of a memory to be designed according to the memory creating instruction;
displaying a preset memory unit module in the first area according to the screening instruction;
selecting memory unit modules displayed in the first area according to the attribute information, generating one or more memory design schemes and displaying the memory design schemes in a second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form;
and splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate a design code of the memory to be designed.
2. The memory design method according to claim 1, wherein the attribute information at least comprises: memory type, address depth, port width, and direction.
3. The memory design method according to claim 2, wherein the generating a design code of the memory to be designed by splicing the memory unit modules in the memory design scheme according to the memory generation instruction comprises:
determining the connection width and the address depth of a main chip of the memory to be designed according to the memory creating instruction;
splicing the connection line width of the memory unit module in the second area according to the connection line width of the main chip;
and splicing the address depth of the memory unit module in the second area according to the address depth of the main chip.
4. The memory design method according to claim 1, wherein displaying the predetermined memory cell modules in the first area according to the filtering instruction comprises:
and marking the selectable memory unit module generating the memory design scheme according to the first screening instruction.
5. The memory design method according to claim 1, further comprising, after selecting the memory cell module displayed in the first area according to the attribute information, generating one or more memory design solutions and displaying the one or more memory design solutions in a second area:
determining a replaced memory unit module according to the template selection instruction and displaying the memory unit module to be selected; wherein the memory cell module to be selected is smaller than or equal to the size of the replaced memory cell module.
6. The memory design method according to claim 2, further comprising, after displaying the predetermined memory cell modules in the first area according to the filtering instruction:
when the memory creating instruction indicates that a to-be-designed memory is generated in a custom mode, displaying the size outline of the to-be-designed memory in a third area according to the memory creating instruction;
displaying the selected memory unit module in the size outline of the memory to be designed according to a template selection instruction; the size of the memory unit module displayed in the size outline of the memory to be designed is determined according to the width and the depth of the memory unit module;
and after the area in the size outline of the memory to be designed is completely distributed, splicing the memory unit modules displayed in the first area to generate a design code of the memory to be designed.
7. The method as claimed in claim 6, wherein the displaying the selected memory cell module in the size outline of the memory to be designed according to the template selecting instruction comprises:
determining the size of a selected area in the size outline of the memory to be designed according to the template selection instruction;
and determining the memory unit module to be selected according to the size of the selected area.
8. A memory design apparatus, comprising:
the attribute determining module is used for determining the attribute information of the memory to be designed according to the memory creating instruction;
the first display module is used for displaying a preset memory unit module in the first area according to the screening instruction;
the second display module is used for selecting the memory unit modules displayed in the first area according to the attribute information, generating a plurality of memory design schemes and displaying the memory design schemes in a second area; the second area comprises a memory display area, and the memory display area is used for splicing the memory unit modules according to the size of each memory unit module in the memory design scheme and displaying the memory unit modules in a rectangular frame form;
and the code processing module is used for splicing the memory unit modules in the memory design scheme according to the memory generation instruction to generate the design codes of the memory to be designed.
9. A terminal, comprising:
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the memory design method of any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the memory design method of any one of claims 1 to 7.
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