CN112559429B

CN112559429B - System and method for monitoring data based on USB

Info

Publication number: CN112559429B
Application number: CN202011537834.8A
Authority: CN
Inventors: 李彬华; 苗旺; 金建辉; 何春
Original assignee: Kunming University of Science and Technology
Current assignee: Kunming University of Science and Technology
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2023-10-03
Anticipated expiration: 2040-12-23
Also published as: CN112559429A

Abstract

The invention relates to a system and a method for monitoring data based on USB, belonging to the technical field of electronics and communication. Under the condition of not interfering the data flow between the original USB master and slave devices, the invention extracts the signal on the USB data differential line directly from the middle lead of the USB bus connected with the master and slave devices; the differential signal is received through a special USB2.0 PHY chip, restored into a level signal, further converted into parallel data and sent to an FPGA; and the specially designed FPGA internal logic circuit analyzes and processes the data packet, and the master-slave equipment after unpacking and integrating transmits data and outputs the data through an 8-bit parallel bus. According to the invention, the USB PHY is used for non-invasively intercepting signals and the FPGA is used for processing data packets, so that data transmitted between the USB master device and the USB slave device can be directly output through the parallel IO port without other special equipment (such as a PC).

Description

System and method for monitoring data based on USB

Technical Field

The invention relates to a system and a method for monitoring data based on USB, belongs to the technical field of electronics and communication, and particularly provides a system and a method for processing monitored image data in real time by a base plate based on a singlechip, a CPLD or an FPGA.

Background

With the continuous development and popularization of digital products, data communication between devices has become more high-frequency and high-speed, and USB has become one of the mainstream protocols for data transmission between various devices. Devices supporting the USB protocol are not only common in our daily lives, but are also very popular in scientific research, for example: all kinds of external detection devices, instruments, telescopes, all kinds of signal analyzers and the like are provided with interfaces conforming to the USB standard. USB bus is one of the common external bus standards for data exchange and communication between hosts and devices in the USB bus model. The USB interface is one of the mainstream trends of modern data transmission because of the advantages of high-speed stability, plug and play, unified interface specification, and convenient use. There are three USB interface standards: USB 1.1, USB2.0 and USB 3.0. Although there are many devices with USB3.0 interfaces, the current market share of USB2.0 devices is higher than 3.0.

USB is a convenient, point-to-point data transmission, but the protocol does not support data transmission between three devices. If the function of monitoring and collecting data on the USB2.0 bus in real time is required to be realized, a specific device or system needs to be developed to complete the task. The USB protocol analyzer sold in the market at present can realize the data monitoring and analyzing function based on a computer. In a few documents, the data to be heard is finally uploaded to the PC. The monitoring and collection of the real-time receiving and transmitting data of the USB interface are realized on the computer through software, the portability and the universality are not good, and different computers need to be configured and debugged for many times; and the auxiliary of the upper computer software is removed, so that the device cannot work normally. At present, no system is available for monitoring and collecting data in two directions on a USB2.0 bus in real time, processing and combining the data into a USB transaction, and sending the USB transaction to a base plate circuit for the base plate circuit to use.

Disclosure of Invention

The invention aims to solve the technical problems that: the invention provides a system and a method for monitoring data based on USB, wherein the system monitors bus bidirectional data by using a USB interface chip, and combines the data into USB transactions by using an FPGA (field programmable gate array) to send the USB transactions to a bottom plate circuit.

The technical scheme of the invention is as follows: a system for monitoring data based on USB comprises an FPGA module 1, a USB interface chip module 2, an IO expansion port module 3, a USB interface A11 and a USB interface B12;

the USB interface chip module 2 is connected with the master device 9 and the slave device 10 in a non-invasive way through USB buses of the USB interface A11 and the USB interface B12; the USB interface chip module 2 is also connected with the FPGA module 1, and the FPGA module 1 comprises an ULPI interface module 4, a packet decomposition module 5, a transaction combination module 6, a transmission module 7 and a clock module 8; the clock module 8 is respectively connected with the USB interface chip module 2, the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the IO expansion port module 3 is connected with a transmission module 7 of the FPGA module 1; the IO expansion port module 3 is in butt joint with the bottom plate circuit.

As a further scheme of the present invention, the ULPI interface module 4 is an ULPI PHY interface module, establishes a connection with the USB interface chip module 2 in a protocol layer, and outputs data to the packet decomposition module 5 completely; the packet decomposition module 5 is used for caching the USB data packet into the RAM and storing packet information into the FIFO for caching; the transaction combination module 6 is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module 8 is input by the USB interface chip module 2 and controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the transmission module 7 is configured to combine the combined USB transaction, the synchronization clock provided to the backplane circuit, and the EN signal, and output the combined USB transaction, the synchronization clock provided to the backplane circuit, and the EN signal is high, and one byte in the USB transaction is output every synchronization clock cycle.

A USB-based data listening method, the method comprising:

the USB interface chip module 2 intercepts signals between the master device 9 and the slave device 10 through USB buses of the USB interface A11 and the USB interface B12 in a non-invasive way and sends the signals to the FPGA module 1 for processing, and the FPGA module 1 combines the processed data into a USB transaction and outputs the USB transaction from the IO expansion port module 3 to the bottom plate circuit; the backplane circuit screens the required data for use based on the header file of the transaction.

As a further scheme of the invention, when each USB transaction is output, the first 4 bytes are transaction information heads, and the format of the transaction information heads of the 4 bytes is as follows:

byte 1: tid [7:0] represents the type of the transaction;

byte 2: addr [6:0] represents the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] representing the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by 0-1024 bytes of transaction data.

The working principle of the invention is as follows:

the USB-based data interception system and method uses a backplane 5V to supply power. Because the voltage used by each module is different, the 2-path AMS1117 low-voltage-drop linear power supply chip is used for respectively generating 3.3V and 1.2V for integral use.

The USB interface a11 is used for connecting with a master device 9 for USB communication, and the USB interface B12 is used for connecting with a slave device 10 for USB communication. DM and DP of two USB interfaces are directly connected with USB interface chip module 2, and add 1kΩ's protection resistance and link with FPGA; the VBUS plus 100k omega resistor is connected with the FPGA module 1 and plus 100k omega pull-down resistor.

The chip used by the USB interface chip module 2 is a USB3300 which is packaged based on UTMI+level 3 to form an interface as an ULPI interface; ULPI uses 12 pins to connect a complete OTG host/device PHY to a system on chip. An 8-bit bi-directional data bus, clocked at 60MHz, allows FPGA module 1 to access this internal register array and transfer USB packets to the physical layer. The remaining 3 pins are used for control data flow and arbitration data bus. The direction of the 8-bit data bus is controlled by the DIR output of ULPI interface module 4. The other output NXT is used to control the data stream to and from the device. Finally, the STP input to ULPI interface module 4 terminates the transmission and is used for startup and recovery from the suspended state.

USB3300 provides a noise-free, stable 480MHz reference clock using internal crystal drivers and phase-locked loop subsystems, which the PHY uses during transmission and reception. USB3300 requires a stable, noiseless 24MHz crystal or clock as a frequency reference. USB3300 may use a crystal or external clock oscillator as a 24MHz reference. The crystal is connected to the USB3300 pin. Once the 480MHz phase locked loop is locked to the correct frequency, it will drive the CLKOUT pin with a 60MHz clock. The chip ULPI interface signal level is 3.3V. Operate in a high speed 480Mbps speed mode.

DIR is Direction for controlling transmission Direction of data bus; when the USB interface chip transmits data to the FPGA, the DIR is driven to be high; when no data is transmitted, driving to be low and monitoring a control signal of the FPGA end; meanwhile, the USB interface chip drives the DIR high when the data cannot be received. NXT is Next, and the USB interface chip controls the signal when transmitting data; when the FPGA sends data to the USB interface chip, the USB interface chip immediately pulls up NXT when receiving the data; the FPGA will then put the next byte on the data bus at the next clock cycle; correspondingly, when the USB interface chip is sending data to the FPGA, NXT represents that new byte data is to be sent to the FPGA. STP is Stop, when FPGA is effective, stopping the current data flow on the bus in one clock period; if the FPGA is transmitting data to the USB interface chip, the STP will remain the last bit of data for each packet.

The ULPI interface supports two basic modes of operation: a synchronous mode and a low power consumption mode. In synchronous mode, all signals change with respect to a 60MHz clock. In the low power mode, the clock is turned off in the suspended state, and the next two bits of the data bus contain the line state [1:0] signals. ULPI increases the low power mode, which is an interrupt output that allows the link to receive asynchronous interrupts when the OTG comparator or ID pin changes state. In the synchronous mode, data is transmitted on the rising edge of CLKOUT. The direction of the data bus is determined by the state of the DIR. When DIR is high, PHY is driving data [7:0]. When DIR is low, the link is driving data [7:0]. Because USB uses bit stuffing coding, some method is needed that allows the PHY to restrict USB from transmitting data. ULPI signal NXT is used to request the link layer to place the next byte on the data bus. When the PHY is link addressed, a single ULPI protocol block decodes the ULPI 8-bit bidirectional bus. The link must use the DIR output to determine the direction of the ULPI data bus. USB3300 is a "bus arbiter". The ULPI protocol block routes data/commands to a sender or ULPI register array.

The USB interface chip module 2 restores the data differential signal to a level signal and needs to decode the NRZI bitstream, and then recognizes the padding bits. The data are converted into data with the bit width of 8 bits, and the data are sent to the FPGA module 1 through D0-D7 of the USB interface chip module 2.

The core chip used by the FPGA module 1 is XC6SLX9-2TQG144C chips of the Spartan6 series of the Xilinx company, and is connected to the FPGA chip by matching with an FPGA peripheral circuit. For example, a configuration chip SPI-Flash of the FPGA is used for storing configuration bit stream of the FPGA; the power supply circuit mainly provides required +5V, +3.3V and +1.2V voltages for the FPGA chip and the SPI-Flash; the clock uses the 60MHz clock output by the USB interface chip module 2 as the system clock for the module. And two indicator lamps are configured, and the LED_1 power supply lights up a red indicator lamp to remind the power supply after being turned on. The led_2 transaction indicator lights illuminate once per active USB transaction output. One end of the FPGA module 1 is connected with the IO expansion port module 3, and the other end is connected with the USB interface chip module 2. The device is connected to the bottom plate, and after the bottom plate is electrified, 5V voltage and a reset signal are provided by the bottom plate. The ULPI interface module 4 in the FPGA module 1 writes an initial control command TX CMD to a register of the USB interface chip module 2. The USB interface A11 is connected with the master device 9 for USB communication, and the USB interface B12 is used for connecting with the slave device 10 for USB communication. The USB interface chip module 2 starts to monitor the differential circuit on the bus, and restores the differential signal to a level signal and transmits the level signal to the FPGA module 1. The ULPI interface module 4 is an ULPI PHY interface module, establishes a connection with the USB interface chip module 2 in a protocol layer, and outputs data to the packet decomposition module 5 completely. The packet decomposition module 5 buffers the USB packets into RAM and stores the packet information into FIFO. The transaction combination module 6 is used for USB transaction processing, combines several associated token packets, data packets and handshake packets into one USB transaction and provides EN signals; the clock module 8 is input by the USB interface chip module 2, uses the close combination of a basic clock management module (DCM) and a global clock distribution network in the FPGA, can be used for frequency division and frequency multiplication, eliminates clock delay difference, controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7, outputs clock signals, and can adjust the phase of the output clock signals so as to ensure that the signal time sequence output to a bottom plate is optimal. The transmission module 7 is configured to combine the combined USB transaction, the synchronization clock provided to the backplane, and the EN signal to output to the backplane through the IO expansion port module 3, and when the EN signal is high, there is one byte of USB transaction output per synchronization clock cycle.

The working process of the invention is as follows:

the device is connected to the bottom plate, and after the bottom plate is electrified, 5V voltage and a reset signal are provided by the bottom plate. A2-way LDO low-dropout linear power supply chip is used for respectively generating 3.3V and 1.2V voltages for devices. After reset, ULPI interface module 4 in FPGA module 1 writes initial control command TX CMD to registers of USB interface chip module 2. To write a register, ULPI interface module 4 in FPGA module 1 must wait until DIR is low, driving TXD CMD on the data bus in the first clock cycle. In the third clock cycle, the USB interface chip module 2 will drive NXT high. On the next rising clock edge ULPI interface module 4 will write the register data. In the fifth clock cycle, USB interface chip module 2 will accept the register data and ULPI interface module 4 will drive idle on the bus and drive STP high to signal the end of the packet. Finally, in the sixth clock cycle, the USB interface chip module 2 will latch the data into the register and drive NXT low. ULPI interface module 4 will pull STP low. NXT is used to control when ULPI interface module 4 drives register data on the bus. Since USB interface chip module 2 receives data from ULPI interface module 4, the DIR is low throughout the transaction. STP is used to end the transaction, with data being registered after STP low. After the write operation is completed, ULPI interface module 4 must drive ULPI idle for 00h on the data bus, otherwise USB interface chip module 2 may decode the bus value into an ULPI command.

The USB interface A11 is connected with the master device 9 for USB communication, and the USB interface B12 is connected with the slave device 10 for USB communication. The USB interface chip module 2 starts to monitor the differential circuit on the bus, and restores the differential signal to a level signal and transmits the level signal to the FPGA. During transmission, the USB interface chip module 2 will use NXT to control the data flow rate into the USB interface chip module 2. If the USB interface chip module 2 pipe is full or bit stuffing results in data pipe overfilling, then NXT is inactive (low), and ULPI interface module 4 will hold the value on the data until NXT is active (high). When STP is active and NXT is inactive in ULPI interface module 4, USB transfer ends. Since USB interface chip module 2 expects to take another byte from ULPI interface module 4 in this state, ULPI interface module 4 cannot have an NXT null STP valid signal,

once the USB interface chip module 2 completes the transmission, the DP/DM line returns to the idle state and RXD CMD returns to the link so that the internal packet timing can be updated by the line state.

At full or low speed, once STP is active, each FS/LS bit transition will generate one RXD CMD because the bit time is relatively slow.

The USB interface chip module 2 enables the DIR to enable the USB interface chip module 2 to control the data bus from the ULPI interface module 4. The DIR and NXT validity in the same period contain additional information that the Rxactive is valid. RXD CMD data is transmitted to the FPGA module 1 when NXT is inactive and DIR is active. After the last byte of the USB reception packet is transmitted to the USB interface chip module 2, the line state will return to the idle state.

The ULPI full-speed receiver operates according to UTMI/ULPI specifications. In the full speed case, the NXT signal will only be active when the data bus has valid received data bytes. The RXD command is driven on the data bus when NXT is low and DIR is high.

At full speed, the USB interface chip module 2 does not signal Rxactive invalid in RXD CMD before the DP/DM line state transitions to the idle state. This prevents FPGA module 1 from violating the minimum change time of two full-speed bit times.

When ULPI interface module 4 passes the packet start signal to packet decomposition module 5, 8-bit parallel data is stored in 8-bit wide RAM, and the length of the packet can be obtained by counting one byte each time. The first three groups of 8-bit data are stored in three registers with the width of 8, and when the transmission of a complete packet is finished, the information of each packet is combined into one data to be stored in the FIFO for caching. If the packet is three in length and the first set of data is the PID (packet identification field) of the token packet, and this packet is judged to be the token packet, the first three sets of 8-bit data stored in the register are stored in the first 24-bit buffer in the 64-bit FIFO in width. Wherein the first 1-8 bits are the PID of this packet, 9-15 bits are the address of the device, 16-19 bits are the endpoint data of the device, and the remaining 5 bits are the CRC check bits. If the packet length is greater than 3 and the first set of data is the PID of the data packet, then the packet is determined to be the data packet. Saving a first set of data (PID) to 1-8 bits in a 64-bit FIFO; the length of this packet is reduced by three (except for one byte of PID and two bytes of CRC check bits, which are the length of this packet data) to 25-36 bits in a 64-bit FIFO; the first address of the packet in RAM is incremented by one (the first byte is PID, the second byte is the packet data, and the last two bytes are the packet CRC) to the 37-48 bits in a 64-bit FIFO. If the packet is one in length and the first set of data is the PID of the handshake packet, the packet is determined to be the handshake packet, and the first set of data (PID) is stored in the first bit of the 64-bit FIFO. These data are buffered in a data-holding FIFO for ease of subsequent processing by the transaction assembly module 6.

In the transaction combination module 6, after the data of the last transaction is processed and transmitted to the backplane, if there is data in the FIFO, the first 8 bits of the 64 bits of data in the FIFO are determined, and the first 8 bits are PID (packet identification code). If the PID is the PID of the token packet, the PID data is put into the token packet PID register, the address in the 64-bit data is put into the address register, and the endpoint data is put into the endpoint register. If the PID is the PID of the data packet, the PID data is put into the PID register of the data packet, the data length of the 64-bit data is put into the data length register, and the address of the data in the RAM is put into the address register of the data RAM. If it is the PID of the handshake packet, the PID data is put into the handshake packet PID register. From the three PID registers, it is possible to determine what transaction is being transferred this time, and name this time as a corresponding 8-bit Transaction Identifier (TID) code, and combine the address, endpoint, length of this time into a transaction header. The transmission module 7 is configured to combine the combined USB transaction, the synchronization clock provided to the backplane, and the EN signal, and output the combined USB transaction to the backplane through the IO expansion port module 3, where when the EN signal is high, each synchronization clock cycle outputs one byte in the USB transaction, the first 4 bytes are transaction information headers, and the format of the transaction information headers of the 4 bytes is:

byte 1: tid [7:0] represents the type of the transaction;

followed by transaction data of a corresponding length read out through the data RAM address register. And clears the registers of address, endpoint, PID, etc.

After the data is output to the bottom plate, the bottom plate can screen the required information according to the head information, and the design is specially used for screening the image information.

The beneficial effects of the invention are as follows:

1. when image data is communicated from a USB master-slave device, if the data is required to be analyzed, processed or temporarily stored in real time by a singlechip, CPLD or FPGA base plate, the system can be connected with the base plate system for use. The circuit which is transmitted into the bottom plate from the PC end is omitted, the speed is improved, and the manpower waste is reduced.

2. The invention can monitor the data on the USB bus in real time without passing through the PC machine after accessing the USB transmission line, and transmit the data to the bottom plate for use.

3. The invention has the advantages of simple and easy use, low cost, small area, convenient carrying and strong practicability.

4. The invention can also listen to other data, only needing to make a little modification in the code.

5. The invention integrates several packets into a transaction, discards useless data, classifies all the transactions, and the bottom board circuit can clearly obtain the type of the transaction, the equipment address corresponding to the transaction, the endpoint number corresponding to the transaction and the data length corresponding to the transaction. The base plate circuit can acquire the data wanted by the user according to the conditions, and the result wanted by the user can be conveniently obtained.

Drawings

FIG. 1 is a functional block diagram of the present invention;

FIG. 2 is a circuit diagram of the bidirectional conduction of DATA DATA in a USB interface chip to an FPGA chip of the present invention;

FIG. 3 is a flow chart of the data transfer of the packet decomposition module and transaction combination module of the present invention;

fig. 4 is a backplane receive state machine of the present invention transmitting to a backplane.

The reference numerals in fig. 1: the system comprises a 1-FPGA module, a 2-USB interface chip module, a 3-IO expansion port module, a 4-ULPI interface module, a 5-packet decomposition module, a 6-transaction combination module, a 7-transmission module, an 8-clock module, a 9-master device, a 10-slave device, an 11-USB interface A and a 12-USB interface B.

Detailed Description

The invention will be further described with reference to the drawings and the specific examples.

Example 1: 1-4, a system based on USB data interception comprises an FPGA module 1, a USB interface chip module 2, an IO expansion port module 3, a USB interface A11 and a USB interface B12;

A USB-based data listening method, the method comprising:

byte 1: tid [7:0] represents the type of the transaction;

followed by 0-1024 bytes of transaction data.

Specifically, the FPGA module 1 is connected with the USB interface chip module 2 and the IO expansion port module 3 through different I/O ports. The data transmission between the FPGA module 1, the USB interface chip module 2 and the IO expansion port module 3 is realized by data lines D0-D7 with the bit width of 8 bits. DIR is Direction for controlling transmission Direction of data bus; when the USB interface chip module 2 transmits data to the FPGA module 1, the DIR is driven to be high; when no data is transmitted, driving to be low and monitoring a control signal at the 1 end of the FPGA module; meanwhile, the USB interface chip module 2 drives the DIR high when it cannot receive data. NXT is Next, and the USB interface chip module 2 controls the signal when transmitting data; when the FPGA module 1 sends data to the USB interface chip module 2, the NXT is immediately pulled up when the USB interface chip module 2 receives the data; the FPGA module 1 will then put the next byte on the data bus at the next clock cycle; accordingly, when the USB interface chip module 2 is transmitting data to the FPGA module 1, nxt represents that there is new byte data to be transmitted to the FPGA module 1.STP is Stop, when the FPGA module 1 sets STP to be effective, stopping the current data flow on the bus in one clock period; if FPGA module 1 is transmitting data to USB interface chip module 2, stp will remain the last bit of data for each packet.

As shown in fig. 1, the USB interface a11 is one USB port for connecting the master device 9, the USB interface B12 is another USB port for connecting the slave device 10, and the intermediate leads of the USB buses of the two interfaces are pulled out from the differential pair, so that signals can directly flow out, and the original connection can be restored, thereby achieving the purpose of not interfering with the original transmission line on the hardware level.

As shown in fig. 1, the USB interface chip module 2 intercepts signals between the master device 9 and the slave device 10 through USB buses of the USB interface a11 and the USB interface B12, and sends the signals to the FPGA module 1 for processing, and the FPGA module 1 combines the processed data into a USB transaction, and sends the USB transaction from the IO expansion port module 3 to the backplane circuit. The backplane circuitry may filter the required data for use based on the header file of the transaction.

The circuit diagram shown in fig. 2 solves the main difficulty, and realizes the bidirectional conduction of the DATA from the USB interface chip module 2 to the FPGA module 1. Where MUX is the data selector and BUFT is the tri-state output buffer. When the DIR is high, the tri-state output buffer is in a high-resistance state; the DATA selector turns on DATA and DATA_IN. When the USB interface chip module 2 transmits data to the FPGA module 1, the DIR is driven to be high, and the FPGA module 1 starts to receive the data transmitted by the USB interface chip module 2. The tri-state output buffer transfers data_out DATA to DATA when DIR is low. When there is no data transmission, the USB interface chip module 2 drives the DIR low and monitors the control signal of the FPGA module 1, so that the FPGA module 1 can write the command into the register of the USB interface chip module 2.

As shown in fig. 1, the FPGA module 1 includes: ULPI interface module 4, packet decomposition module 5, transaction combination module 6, transmission module 7, clock module 8; the ULPI interface module 4 is an ULPI PHY interface module, establishes a connection of a protocol layer with the USB interface chip module 2, and outputs data to the packet decomposition module 5 completely; the packet decomposition module 5 caches the USB data packet into the RAM, and stores the packet information into the FIFO for caching; the transaction combination module 6 is used for USB transaction processing, combines several associated token packets, data packets and handshake packets into one USB transaction and provides EN signals; the clock module 8 is input by the USB interface chip module 2 and controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the transmission module 7 is configured to combine the combined USB transaction, the synchronization clock provided to the backplane, and the EN signal, and output the combined USB transaction, the synchronization clock provided to the backplane, and the EN signal is high, and one byte in the USB transaction is output every synchronization clock cycle.

As shown in fig. 3, when the ULPI interface module 4 transmits a packet start signal to the packet decomposition module 5, 8-bit parallel data is stored in an 8-bit wide RAM, and when a complete packet transmission is completed, the PID, endpoint, device address information, packet length, and data with a position in the RAM that constitutes a bit width of 64 are stored in a 64-bit wide FIFO for buffering. When no data is transferred to the backplane, the data in the FIFO is processed. When a transaction transmission is complete, the PIDs of several packets are integrated into the TID of a transaction, the CRC is discarded, and then the information of several packets is integrated into a transaction packet information header.

As shown in fig. 1, the USB interface chip module 2 needs to write a USB protocol into the USB3300 chip, so that the USB3300 chip can restore the differential signal to a level signal, translate the level signal into a signal conforming to the ULPI protocol, and convert the data into data with a bit width of 8 bits by the ULPI protocol and transmit the data to the FPGA for processing. And passes the CLK signal into the FPGA.

As shown in fig. 1, the IO expansion port module 3 is connected with a transmission module 7 of the FPGA module 1; the IO expansion port module 3 outputs a clock signal to the bottom plate so as to synchronize the clock of the bottom plate; transaction valid signal EN and USB transaction are output to the backplane.

As shown in fig. 4, is a backplane receiving state machine of the present invention transmitting to a backplane. When each USB transaction is output, when EN is valid, the transaction packet is output in sequence, the first 4 bytes are transaction information heads, and the format of the transaction information heads of the 4 bytes is as follows:

byte 1: tid [7:0] represents the type of the transaction;

followed by 0-1024 bytes of transaction data.

After the base plate is powered on, the base plate enters an initial state (IDLE), and when an enable signal EN is 1 and a previous clock EN is 0, namely when a USB transaction is transmitted to the base plate by the system, the information head of the first eight-bit data is received and enters a HEADER_1 state. The header_1 state EN is 1 to receive the HEADER of the second octet of data and enter the header_2 state. The header_2 state EN is 1 to receive the HEADER of the third octet of data and enters the header_3 state. The HEADER_3 state EN is a1 to receive the HEADER of the fourth octet of DATA and enter the DATA state. The DATA state continues with DATA going down as long as EN is 1 until EN is 0, returning to the initial state machine (IDLE). The backplane may filter the desired data based on the state machine plus header constraints.

The specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.

Claims

1. A system for listening based on USB data, characterized in that: the device comprises an FPGA module (1), a USB interface chip module (2), an IO expansion port module (3), a USB interface A (11) and a USB interface B (12);

the USB interface chip module (2) is connected with the master device (9) and the slave device (10) through USB buses of the USB interface A (11) and the USB interface B (12) in a non-invasive way; the USB interface chip module (2) is also connected with the FPGA module (1), and the FPGA module (1) comprises an ULPI interface module (4), a packet decomposition module (5), a transaction combination module (6), a transmission module (7) and a clock module (8); the clock module (8) is respectively connected with the USB interface chip module (2), the ULPI interface module (4), the packet decomposition module (5), the transaction combination module (6) and the transmission module (7); the IO expansion port module (3) is connected with a transmission module (7) of the FPGA module (1); the IO expansion port module (3) is in butt joint with the bottom plate circuit;

the ULPI interface module (4) is an ULPI PHY interface module, establishes a connection of a protocol layer with the USB interface chip module (2), and completely outputs data to the packet decomposition module (5); the packet decomposition module (5) is used for caching the USB data packet into the RAM and storing packet information into the FIFO for caching; the transaction combination module (6) is used for USB transaction processing, and combines a plurality of associated token packets, data packets and handshake packets into one USB transaction and provides an EN signal; the clock module (8) is input by the USB interface chip module (2) and controls clocks of the ULPI interface module (4), the packet decomposition module (5), the transaction combination module (6) and the transmission module (7); the transmission module (7) is used for combining the combined USB transaction, the synchronous clock provided for the bottom plate circuit and the EN signal and outputting the combined USB transaction, the synchronous clock and the EN signal to the bottom plate circuit through the IO expansion port module (3), and when the EN signal is high, one byte in the USB transaction is output every synchronous clock period.

2. A method for listening based on USB data, the method comprising:

the USB interface chip module (2) is used for non-invasively intercepting signals between the master device (9) and the slave device (10) through USB buses of the USB interface A (11) and the USB interface B (12) and sending the signals to the FPGA module (1) for processing, and the FPGA module (1) is used for combining the processed data into a USB transaction and outputting the USB transaction to the bottom plate circuit from the IO expansion port module (3); the base plate circuit screens the needed data for use according to the header file of the transaction;

when each USB transaction is output, the first 4 bytes are transaction information heads, and the format of the transaction information heads of the 4 bytes is as follows:

byte 1: tid [7:0] represents the type of the transaction;

followed by 0-1024 bytes of transaction data.