CN112559040B - Instruction execution method and device, electronic equipment and storage medium - Google Patents
Instruction execution method and device, electronic equipment and storage medium Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The application discloses an instruction execution method, an instruction execution device, electronic equipment and a storage medium, and relates to the technical field of voice, natural language processing and deep learning. The specific implementation scheme is as follows: the instruction classifier identifies the category of the current input instruction; if the type is a parameter configuration instruction, the instruction classifier writes the corresponding parameter into a corresponding first parameter register in the instruction cache according to the parameter configuration instruction; if the category is a calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in an instruction cache; and when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. The instruction execution method, the instruction execution device, the electronic equipment and the storage medium improve operation execution efficiency.
Description
Technical Field
The present application relates to the technical field of speech, natural language processing, and deep learning in the field of computer technologies, and in particular, to an instruction execution method, apparatus, electronic device, and storage medium.
Background
Complex operation instructions often exist in an operation processor chip, for example, a large number of operations such as convolution and full-connection activation exist in Long Short-Term Memory Network (LSTM) and Wave-based Recurrent Neural Network (WaveRNN) algorithms in voice processing, and the instructions are generally completed by a special operation unit.
At present, an operation program is put into an interrupt to remove the correlation between an operation function and a main program during operation execution, or an out-of-order execution architecture is adopted to remove part of instruction correlation, but the problem of waiting between parameter configuration and complex operation exists, so the operation execution efficiency is high.
Disclosure of Invention
Provided are an instruction execution method, an instruction execution apparatus, an electronic device, and a storage medium.
According to a first aspect, there is provided an instruction execution method comprising: the instruction classifier identifies the category of the current input instruction; if the category is a parameter configuration instruction, the instruction classifier writes the corresponding parameter into a corresponding first parameter register in an instruction cache according to the parameter configuration instruction; if the category is a calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in the instruction cache; and when the arithmetic unit detects that the instruction register is not empty, taking out the next calculation instruction from the instruction register, taking out the written parameter from the corresponding first parameter register according to the taken out calculation instruction, and updating the taken parameter into a second parameter register in the arithmetic unit for calculation.
According to a second aspect, there is provided an instruction execution apparatus comprising: an instruction cache comprising a first parameter register and an instruction register; the instruction classifier is used for identifying the category of the current input instruction; if the type is a parameter configuration instruction, writing corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction; if the category is a calculation instruction, writing the calculation instruction into the instruction register in the instruction cache; and the arithmetic unit is used for taking out the next calculation instruction from the instruction register when detecting that the instruction register is not empty, taking out the written parameter from the corresponding first parameter register according to the taken out calculation instruction, and updating the taken parameter into a second parameter register in the arithmetic unit for calculation.
According to a third aspect, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executable by the at least one processor to enable the at least one processor to perform the instruction execution method of the first aspect of the application.
According to a fourth aspect, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the instruction execution method of the first aspect of the present application.
According to a fifth aspect, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the instruction execution method of the first aspect of the application.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present application, nor do they limit the scope of the present application. Other features of the present application will become apparent from the following description.
Drawings
The drawings are included to provide a better understanding of the present solution and are not intended to limit the present application. Wherein:
FIG. 1 is a flow chart diagram of an instruction execution method according to a first embodiment of the present application;
FIG. 2 is a flowchart illustrating an instruction execution method according to a second embodiment of the present application;
FIG. 3 is a flowchart illustrating an instruction execution method according to a third embodiment of the present application;
FIG. 4 is a system architecture diagram of an instruction execution method according to an embodiment of the present application;
FIG. 5 is a flowchart illustrating an instruction execution method according to a fourth embodiment of the present application;
FIG. 6 is a block diagram of an instruction execution apparatus according to a first embodiment of the present application;
FIG. 7 is a block diagram of an instruction execution apparatus according to a second embodiment of the present application;
FIG. 8 is a block diagram of an electronic device that may be used to implement the instruction execution method of an embodiment of the application.
Detailed Description
The following description of the exemplary embodiments of the present application, taken in conjunction with the accompanying drawings, includes various details of the embodiments of the application for the understanding of the same, which are to be considered exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
The speech can include the technical fields of speech recognition, speech interaction and the like, and is an important direction in the field of artificial intelligence.
Voice Recognition (Voice Recognition) is a technology for a machine to convert Voice signals into corresponding texts or commands through a Recognition and understanding process, and mainly comprises three aspects of a feature extraction technology, a pattern matching criterion and a model training technology.
Voice Interaction (Voice Interaction) is a technology for Interaction, communication, information exchange and the like between a machine and a user by taking Voice as an information carrier, and has the advantages of convenience, rapidness and high user comfort compared with the traditional man-machine Interaction.
Natural Language Processing (NLU) is a science for researching computer systems, especially software systems, which can effectively realize Natural Language communication, and is an important direction in the fields of computer science and artificial intelligence.
Deep Learning (DL) is a new research direction in the field of Machine Learning (ML), and is an internal rule and an expression level of Learning sample data, so that a Machine can have the ability of analyzing and Learning like a human, can recognize data such as characters, images and sounds, and is widely applied to voice and image recognition.
An instruction execution method, an apparatus, an electronic device, and a storage medium according to embodiments of the present application are described below with reference to the accompanying drawings.
FIG. 1 is a flowchart illustrating an instruction execution method according to a first embodiment of the present application.
As shown in fig. 1, the instruction execution method according to the embodiment of the present application may specifically include the following steps:
s101, the instruction classifier identifies the category of the current input instruction.
Specifically, the execution main body of the instruction execution method according to the embodiment of the present application may be the instruction execution device provided in the embodiment of the present application, and the instruction execution device may be a hardware device having a data information processing capability and/or necessary software for driving the hardware device to operate.
The instruction execution device comprises an instruction classifier used for identifying the category of the current input instruction. The category may specifically include, but is not limited to, parameter configuration instructions, computation instructions, hardware synchronization instructions, and general Central Processing Unit (CPU) instructions.
The command recognition method may be any of various conventional command recognition methods, and the present application is not limited to this.
And S102, if the type is a parameter configuration instruction, the instruction classifier writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction.
Specifically, if the instruction classifier identifies that the type of the current input instruction is a parameter configuration instruction, the parameter corresponding to the instruction is written into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction. Wherein, the parameter corresponding to the instruction can be carried in the instruction.
The instruction cache may specifically be a macro instruction cache. The instruction cache comprises a plurality of entries, and each entry comprises a first parameter register group (the first parameter register group comprises n first parameter registers) and an instruction register. The first parameter register is used for storing written parameters, and the instruction register is used for storing written instructions.
S103, if the category is the calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in the instruction cache.
Specifically, if the instruction classifier identifies that the type of the current input instruction is a calculation instruction, the calculation instruction is written into an instruction register in the instruction cache.
As will be appreciated by those skilled in the art, software requires that parameters be configured first and then instructions for computation be sent in the configuration of macro instructions.
S104, when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameter is taken out from the corresponding first parameter register according to the taken out calculation instruction, and the taken out parameter is updated to a second parameter register in the arithmetic unit for calculation.
Specifically, when the arithmetic unit detects that the instruction register is not empty, that is, there is a to-be-executed calculation instruction in the instruction register, the arithmetic unit fetches a next to-be-executed calculation instruction from the instruction register, fetches the written parameter from the first parameter register corresponding to the calculation instruction according to the fetched calculation instruction, updates the fetched parameter to the second parameter register in the arithmetic unit, and performs calculation by using the second parameter register.
To sum up, in the instruction execution method according to the embodiment of the present application, the instruction classifier identifies the category of the currently input instruction, if the category is the parameter configuration instruction, the corresponding parameter is written into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, the instruction classifier writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved.
FIG. 2 is a flowchart illustrating an instruction execution method according to a second embodiment of the present application.
As shown in fig. 2, the instruction execution method according to the embodiment of the present application may specifically include the following steps:
s201, the instruction classifier identifies the category of the current input instruction.
S202, if the type is a parameter configuration instruction, the instruction classifier writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction.
S203, if the category is the calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in the instruction cache.
S204, when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameter is taken out from the corresponding first parameter register according to the taken out calculation instruction, and the taken out parameter is updated to a second parameter register in the arithmetic unit for calculation.
Specifically, steps S201 to S204 are the same as steps S101 to S104 in the above embodiment, and the detailed process is not described here again.
The instruction execution method of the embodiment of the application may further include the following steps S205 to S210.
S205, if the category is the hardware synchronization instruction, the instruction classifier sends the first read status instruction to the status detection unit.
Specifically, when the software needs to wait for the calculation result of the arithmetic unit, a hardware synchronization instruction is input to the instruction classifier. And if the instruction classifier identifies that the type of the current input instruction is a hardware synchronization instruction, sending the first read state instruction to the state detection unit.
S206, the state detection unit detects the state of the instruction register and the state of the operation unit according to the first read state instruction.
Specifically, the state detection unit is used for synchronizing the states of the software and the hardware. And after receiving the first state reading instruction, the state detection unit detects the state of the instruction register and the state of the operation unit. The state of the instruction register includes empty and not empty. The states of the arithmetic unit include busy (busy) and idle (idle). When the second parameter register in the operation unit is in a calculation state, the state of the operation unit is busy, and when the second parameter register in the operation unit is in a non-calculation state, the state of the operation unit is idle.
In one possible embodiment, the busy bit of the operation unit is pulled high when the second parameter register in the operation unit starts to calculate, and pulled low when the operation is finished. The state detection unit can determine whether the state of the operation unit is busy or idle according to the height of the busy bit of the operation unit.
S207, the state detection unit detects that the instruction register is not empty or the arithmetic unit is in a busy state, and sends the first waiting notification information to the instruction classifier.
Specifically, if the state detection unit detects that the instruction register is not empty or the arithmetic unit is in a busy state, that is, at least one of the instruction register is not empty and the arithmetic unit is in the busy state is detected to be satisfied, the first wait notification information is sent to the instruction classifier.
S208, the instruction classifier stops executing the step of identifying the category of the current input instruction according to the first waiting notice information.
Specifically, after receiving the first waiting notification message, the instruction classifier stops executing the step of identifying the category of the current input instruction, and waits for the operation of the operation unit to end.
S209, the state detection unit detects that the instruction register is empty and the arithmetic unit is in an idle state, and sends the first stop waiting notification message to the instruction classifier.
Specifically, if the state detection unit detects that the instruction register is empty and the operation unit is in an idle state, that is, when the instruction register is empty and the operation unit is in the idle state and satisfied at the same time, it indicates that all operations are completed, and sends the first stop-and-wait notification message to the instruction classifier.
S210, the instruction classifier continues to execute the step of identifying the category of the current input instruction according to the first stop-and-wait notification information.
Specifically, after receiving the first stop-and-wait notification message, the instruction classifier continues to perform the step of identifying the category of the current input instruction.
Further, the instruction execution method of the embodiment of the application may further include the following steps S211 to S212.
S211, if the type is the CPU instruction, the instruction classifier sends the CPU instruction to the CPU arithmetic unit.
Specifically, if the instruction classifier identifies that the type of the current input instruction is a Central Processing Unit (CPU) instruction, the CPU instruction is sent to a CPU arithmetic unit, namely a CPU arithmetic unit.
S212, the central processing arithmetic unit executes the central processing unit instruction.
Specifically, the CPU operator receives the CPU instruction and then executes the CPU instruction.
Further, after the "instruction classifier writes the calculation instruction into the instruction register in the instruction cache" in step S203, the instruction execution method according to the embodiment of the present application may further include the following steps: the instruction cache updates the write address of the instruction register, i.e., write address + 1.
Further, after the "operation unit fetches the next computation instruction from the instruction register" in step S204, the instruction execution method according to the embodiment of the present application may further include the following steps: the instruction cache updates the read address of the instruction register, i.e., read address + 1.
Further, after the step S202 that the instruction classifier writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, the instruction execution method according to the embodiment of the present application may further include: the instruction cache sets a parameter state indication position corresponding to a first parameter register written with the parameter to be a first numerical value. Correspondingly, the step S204 of "the arithmetic unit fetches the written parameter from the corresponding first parameter register according to the fetched calculation instruction" includes: the arithmetic unit fetches the parameter with the parameter state indicating bit being the first numerical value from the corresponding first parameter register according to the fetched calculation instruction. Correspondingly, the instruction execution method of the embodiment of the application may further include: the instruction cache sets the parameter state indication position corresponding to the first parameter register of the parameter to be taken out as a second numerical value.
Specifically, since not all parameters need to be configured for a certain computation instruction, a parameter status register is set in the instruction cache, so that only the parameters that need to be changed need to be updated. Each entry in the instruction cache includes an n-bit (bit) parameter status register. Each bit in the parameter state register corresponds to a parameter state indication bit, and each parameter state indication bit corresponds to a first parameter register. When a parameter is written into the first parameter register, the instruction cache sets the corresponding parameter status indication position to a first value, for example, state is 1. The arithmetic unit fetches a parameter with a parameter state indication bit of a first value, for example, a state of 1, from a corresponding first parameter register according to the fetched calculation instruction. The instruction cache sets the parameter status indication position corresponding to the fetched parameter to a second value, for example, state is 0.
To sum up, in the instruction execution method according to the embodiment of the present application, the instruction classifier identifies the category of the currently input instruction, if the category is the parameter configuration instruction, the corresponding parameter is written into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, the instruction classifier writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved. The state detection unit is adopted to synchronize software and hardware, so that extra power consumption overhead caused by the software in a query or interrupt mode can be avoided, and the design of the instruction execution device is simplified.
Further, as shown in fig. 3, before the step S202 in which the instruction classifier writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, "the instruction execution method according to the embodiment of the present application may further include the following steps:
s301, the instruction classifier sends the second read state instruction to the state detection unit.
Specifically, if the instruction classifier identifies that the type of the current input instruction is the parameter configuration instruction, the second read state instruction is sent to the state detection unit.
S302, the state detection unit detects the state of the first parameter register according to the second read state instruction.
Specifically, the state detection unit detects the state of the first parameter register after receiving the second read state instruction. The status of the first parameter register includes full and not full.
S303, the state detection unit detects that the first parameter register is full, and sends the second waiting notice information to the instruction classifier.
Specifically, if the state detection unit detects that the first parameter register is full (full), the second wait notification information is sent to the instruction classifier.
As a possible implementation, the instruction cache pulls the full bit of the first parameter register high when the first parameter register is full, and pulls the full bit of the first parameter register low when the first parameter register is not full. The state detection unit may determine whether the state of the first parameter register is full or not full according to the high or low of the full bit of the first parameter register.
S304, the instruction classifier stops executing the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second waiting notification information.
Specifically, after receiving the second waiting notification message, the instruction classifier stops executing the step of writing the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, that is, the parameter writing step is not executed any more, so that the previously written parameter is prevented from being flushed. And the instruction classifier stops executing the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and further stops executing the step of identifying the category of the current input instruction.
S305, the state detection unit detects that the first parameter register is not full, and sends a second stop waiting notification message to the instruction classifier.
Specifically, if the state detection unit detects that the first parameter register is not full (not full), the second stop-and-wait notification message is sent to the instruction classifier.
S306, the instruction classifier continues to execute the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second stop waiting notification information.
Specifically, after receiving the second stop-and-wait notification message, the instruction classifier continues to perform the step of writing the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, that is, continues to perform the parameter writing step. And the instruction classifier continues to execute the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and further continues to execute the step of identifying the category of the current input instruction.
To sum up, in the instruction execution method according to the embodiment of the present application, the instruction classifier identifies the category of the currently input instruction, if the category is the parameter configuration instruction, the corresponding parameter is written into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, the instruction classifier writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved. The state detection unit is adopted to synchronize software and hardware, so that extra power consumption overhead caused by the software in a query or interrupt mode can be avoided, and the design of the instruction execution device is simplified. Before the parameter is written, whether the first parameter register is full or not is detected, so that the condition that the parameter to be written subsequently washes away the parameter written previously can be avoided. By setting the parameter state indicating bit, software does not need to update all parameters, and the operation execution efficiency can be further improved.
For clarity of explaining the instruction execution method of the embodiment of the present application, the instruction execution method of the embodiment of the present application is described below with reference to fig. 4 and 5.
FIG. 4 is a block diagram of a system architecture of an instruction execution method according to an embodiment of the present application. As shown in fig. 4, the system comprises an instruction classifier, an instruction cache, a state detection unit, an arithmetic unit and a central processing arithmetic unit. The specific functions of the components are described in the embodiment shown in fig. 5, and are not described in detail here.
As shown in fig. 5, the instruction execution method according to the embodiment of the present application may specifically include the following steps:
s501, the instruction classifier identifies the category of the current input instruction.
S502, if the type is a parameter configuration instruction, the instruction classifier sends a second read state instruction to the state detection unit.
S503, the state detection unit detects the state of the first parameter register according to the second read state instruction. If the first parameter register is not full, steps S504-S506 are executed. If the first parameter register is full, steps S507-S508 are performed.
S504, the state detection unit detects that the first parameter register is not full, and sends a second stop-and-wait notification message to the instruction classifier.
And S505, the instruction classifier writes the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second stop waiting notification information.
S506, the instruction cache sets the parameter state indication position corresponding to the first parameter register written with the parameter to be a first numerical value.
S507, the state detection unit detects that the first parameter register is full, and sends the second waiting notice information to the instruction classifier.
And S508, the instruction classifier stops executing the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second waiting notification information.
S509, if the category is the calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in the instruction cache.
S510, the instruction cache updates the write address of the instruction register.
S511, the arithmetic unit detects that the instruction register is not empty, and then takes out the next calculation instruction from the instruction register.
S512, the instruction cache updates the read address of the instruction register.
S513, the arithmetic unit fetches the parameter with the parameter status indication bit being the first value from the corresponding first parameter register according to the fetched calculation instruction.
S514, the instruction cache sets the parameter state indication position corresponding to the first parameter register of the parameter to be taken out to be a second numerical value.
And S515, the arithmetic unit updates the extracted parameters to a second parameter register in the arithmetic unit for calculation.
S516, if the type is a hardware synchronization instruction, the instruction classifier sends the first read status instruction to the status detection unit.
S517, the state detection unit detects the state of the instruction register and the state of the arithmetic unit according to the first read state instruction;
s518, when the state detection unit detects that the instruction register is not empty or the arithmetic unit is in a busy state, the state detection unit sends the first waiting notification information to the instruction classifier;
s519, the instruction classifier stops executing the step of identifying the category of the current input instruction according to the first waiting notification information.
S520, the state detection unit detects that the instruction register is empty and the operation unit is in an idle state, and sends the first stop waiting notification information to the instruction classifier.
S521, the instruction classifier continues to execute the step of identifying the category of the current input instruction according to the first stop-and-wait notification information.
S522, if the type is the CPU instruction, the instruction classifier sends the CPU instruction to the CPU arithmetic unit.
S523, the central processing unit executes the central processing unit instruction.
Fig. 6 is a block diagram of an instruction execution apparatus according to a first embodiment of the present application.
As shown in fig. 6, the instruction execution apparatus 600 according to the embodiment of the present application may specifically include: instruction cache 601, instruction sorter 602, and arithmetic unit 603. The instruction cache 601 includes a first parameter register 6011 and an instruction register 6012.
An instruction classifier 602 for identifying a category of a currently input instruction; if the type is a parameter configuration instruction, writing the corresponding parameter into the corresponding first parameter register 6011 in the instruction cache 601 according to the parameter configuration instruction; if the category is a calculation instruction, the calculation instruction is written into the instruction register 6012 in the instruction cache 601.
The arithmetic unit 603 is configured to, when it is detected that the instruction register 6012 is not empty, fetch a next calculation instruction from the instruction register 6012, fetch a written parameter from the corresponding first parameter register 6011 according to the fetched calculation instruction, and update the fetched parameter to a second parameter register in the arithmetic unit 603 for calculation.
It should be noted that the above explanation of the embodiment of the instruction execution method is also applicable to the instruction execution apparatus in the embodiment of the present application, and the detailed process is not described here again.
To sum up, in the instruction execution apparatus according to the embodiment of the present application, the instruction classifier identifies the category of the currently input instruction, and if the category is the parameter configuration instruction, writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved.
Fig. 7 is a block diagram of an instruction execution apparatus according to a second embodiment of the present application.
As shown in fig. 7, an instruction execution apparatus 700 according to an embodiment of the present application includes: an instruction cache 701, an instruction classifier 702, and an arithmetic unit 703. The instruction cache 701 includes a first parameter register 7011 and an instruction register 7012.
The instruction cache 701 has the same function and structure as the instruction cache 601 in the above embodiment, and the instruction classifier 702 has the same function and structure as the instruction classifier 602 in the above embodiment. The arithmetic unit 703 has the same function and structure as the arithmetic unit 603 in the above-described embodiment. The first parameter register 7011 has the same function and structure as 7011 in the above-described embodiment. The instruction register 7012 has the same function and structure as 6011 in the above-described embodiments.
Further, the instruction execution apparatus 700 of the embodiment of the present application may further include a state detection unit 704. The instruction classifier 702 is further configured to: if the type is a hardware synchronization instruction, a first read status instruction is sent to the status detection unit 704; and stopping executing the step of identifying the category of the current input instruction according to the received first waiting notice information. The state detection unit 704 is configured to: detecting the state of the instruction register 7012 and the state of the arithmetic unit 703 according to the first read state instruction; when detecting that the instruction register 7012 is not empty or the arithmetic unit 703 is busy, the first wait notification message is sent to the instruction classifier 702.
Further, the state detection unit 704 is further configured to: when detecting that the instruction register 7012 is empty and the arithmetic unit 703 is in an idle state, sending a first stop-and-wait notification message to the instruction classifier 702; the instruction classifier 702 is further configured to: and continuing to execute the step of identifying the category of the current input instruction according to the first stop-and-wait notification information.
Further, the instruction classifier 702 is further configured to: sending the second read status instruction to the status detection unit 704; the state detection unit 704 is configured to: detecting the state of the first parameter register 7011 according to the second read state instruction; when detecting that the first parameter register 7011 is full, sending the second wait notification message to the instruction classifier 702; the instruction classifier 702 is further configured to: according to the second waiting notification message, the step of writing the corresponding parameter into the corresponding first parameter register 7011 in the instruction cache 701 according to the parameter configuration instruction is stopped.
Further, the state detection unit 704 is further configured to: when detecting that the first parameter register 7011 is not full, sending a second stop wait notification message to the instruction classifier 702; the instruction classifier 702 is further configured to: according to the second stop-and-wait notification message, the step of writing the corresponding parameter into the corresponding first parameter register 7011 in the instruction cache 701 according to the parameter configuration instruction is continuously performed.
Further, instruction cache 701 is configured to: setting a parameter state indication position corresponding to a first parameter register 7011, into which a parameter is written, as a first numerical value; setting a parameter state indication position corresponding to the first parameter register 7011 from which the parameter is taken out as a second numerical value; the operation unit 703 is specifically configured to: the parameter with the parameter status indicator bit being the first value is fetched from the corresponding first parameter register 7011 according to the fetched calculation instruction.
Further, instruction cache 701 is configured to: after the instruction sorter 702 writes the calculation instruction into the instruction register 7012 in the instruction cache 701, the write address of the instruction register 7012 is updated.
Further, instruction cache 701 is configured to: after the arithmetic unit 703 fetches the next calculation instruction from the instruction register 7012, the read address of the instruction register 7012 is updated.
Further, the instruction execution apparatus 700 of the embodiment of the present application may further include: a central processing arithmetic unit 705; the instruction classifier 702 is further configured to: if the class is the central processing unit instruction, the instruction classifier 702 sends the central processing unit instruction to the central processing arithmetic unit; the central processing arithmetic unit is used for: and executing the instructions of the central processing unit.
It should be noted that the above explanation of the embodiment of the instruction execution method is also applicable to the instruction execution apparatus in the embodiment of the present application, and the detailed process is not described here again.
To sum up, in the instruction execution apparatus according to the embodiment of the present application, the instruction classifier identifies the category of the currently input instruction, and if the category is the parameter configuration instruction, writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, the next calculation instruction is taken out from the instruction register, the written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved. The state detection unit is adopted to synchronize software and hardware, so that extra power consumption overhead caused by the software in a query or interrupt mode can be avoided, and the design of the instruction execution device is simplified. Before the parameter is written, whether the first parameter register is full or not is detected, so that the condition that the parameter to be written subsequently washes away the parameter written previously can be avoided. By setting the parameter state indicating bit, software does not need to update all parameters, and the operation execution efficiency can be further improved.
According to an embodiment of the present application, an electronic device and a readable storage medium are also provided.
Fig. 8 is a block diagram of an electronic device according to an instruction execution method of an embodiment of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as smart voice interaction devices, personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.
As shown in fig. 8, the electronic apparatus includes: one or more processors 801, memory 802, and interfaces for connecting the various components, including a high speed interface and a low speed interface. The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor 801 may process instructions for execution within the electronic device, including instructions stored in or on a memory to display graphical information of a GUI on an external input/output device (such as a display device coupled to an interface). In other embodiments, multiple processors and/or multiple buses may be used, along with multiple memories and multiple memories, as desired. Also, multiple electronic devices may be connected, with each device providing portions of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system). Fig. 8 illustrates an example of a processor 801.
The memory 802 is a non-transitory computer readable storage medium as provided herein. The memory stores instructions executable by the at least one processor, so that the at least one processor executes the instruction execution method provided by the application. The non-transitory computer-readable storage medium of the present application stores computer instructions for causing a computer to perform the instruction execution method provided herein.
The memory 802, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the instruction execution method in the embodiment of the present application (for example, the instruction cache 601, the instruction classifier 602, and the arithmetic unit 603 shown in fig. 6). The processor 801 executes various functional applications of the server and data processing by running non-transitory software programs, instructions, and modules stored in the memory 802, that is, implements the instruction execution method in the above-described method embodiment.
The memory 802 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the electronic device of the instruction execution method, and the like. Further, the memory 802 may include high speed random access memory and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 802 optionally includes memory located remotely from the processor 801, which may be connected via a network to an electronic device that executes the method. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The electronic device of the instruction execution method may further include: an input device 803 and an output device 804. The processor 801, the memory 802, the input device 803, and the output device 804 may be connected by a bus or other means, and are exemplified by a bus in fig. 8.
The input device 803 may receive input numeric or character information and generate key signal inputs related to user settings and function controls of the electronic apparatus instructing the execution method, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, a pointing stick, one or more mouse buttons, a track ball, a joystick, or the like. The output devices 804 may include a display device, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibrating motors), among others. The display device may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some implementations, the display device can be a touch screen.
Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, application specific ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
These computer programs (also known as programs, software applications, or code) include machine instructions for a programmable processor, and may be implemented using high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), the internet, and blockchain networks.
The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The Server can be a cloud Server, also called a cloud computing Server or a cloud host, and is a host product in a cloud computing service system, so as to solve the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service ("Virtual Private Server", or simply "VPS"). The server may also be a server of a distributed system, or a server incorporating a blockchain.
According to an embodiment of the present application, there is also provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the instruction execution method of the above-described embodiment of the present application.
According to the technical scheme of the embodiment of the application, the instruction classifier identifies the category of the current input instruction, if the category is the parameter configuration instruction, the corresponding parameter is written into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, and if the category is the calculation instruction, the instruction classifier writes the calculation instruction into the instruction register in the instruction cache. And when the arithmetic unit detects that the instruction register is not empty, taking out the next calculation instruction from the instruction register, taking out the written parameter from the corresponding first parameter register according to the taken out calculation instruction, and updating the taken parameter into a second parameter register in the arithmetic unit for calculation. By adopting the instruction cache, the preprocessing before operation (including parameter configuration and writing of calculation instructions) and the operation in the operation unit can be executed in parallel, namely asynchronous execution, so that the operation execution efficiency is improved.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solutions of the present application can be achieved.
The above-described embodiments should not be construed as limiting the scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (20)
1. An instruction execution method comprising:
the instruction classifier identifies the category of the current input instruction;
if the category is a parameter configuration instruction, the instruction classifier writes the corresponding parameter into a corresponding first parameter register in an instruction cache according to the parameter configuration instruction;
if the category is a calculation instruction, the instruction classifier writes the calculation instruction into an instruction register in the instruction cache;
when the arithmetic unit detects that the instruction register is not empty, a next calculation instruction is taken out from the instruction register, written parameters are taken out from the corresponding first parameter register according to the taken calculation instruction, and the taken parameters are updated to a second parameter register in the arithmetic unit for calculation;
wherein the instruction cache comprises a plurality of entries, each entry comprising the first parameter register and the instruction register.
2. The instruction execution method of claim 1, further comprising:
if the class is a hardware synchronization instruction, the instruction classifier sends a first read state instruction to a state detection unit;
the state detection unit detects the state of the instruction register and the state of the arithmetic unit according to the first read state instruction;
the state detection unit detects that the instruction register is not empty or the arithmetic unit is in a busy state, and sends first waiting notification information to the instruction classifier;
and the instruction classifier stops executing the step of identifying the category of the current input instruction according to the first waiting notice information.
3. The instruction execution method of claim 2, further comprising:
the state detection unit detects that the instruction register is empty and the arithmetic unit is in an idle state, and sends first stop waiting notification information to the instruction classifier;
and the instruction classifier continues to execute the step of identifying the category of the current input instruction according to the first stop-and-wait notification information.
4. The instruction execution method of claim 1, wherein prior to the instruction classifier writing the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, further comprising:
the instruction classifier sends a second read state instruction to a state detection unit;
the state detection unit detects the state of the first parameter register according to the second read state instruction;
the state detection unit detects that the first parameter register is full, and then sends second waiting notification information to the instruction classifier;
and the instruction classifier stops executing the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second waiting notification information.
5. The instruction execution method of claim 4, further comprising:
the state detection unit detects that the first parameter register is not full, and sends second stop waiting notification information to the instruction classifier;
and the instruction classifier continues to execute the step of writing the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction according to the second stop waiting notification information.
6. The instruction execution method of claim 1, wherein after the instruction classifier writes the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction, the method further comprises:
the instruction cache sets a parameter state indication position corresponding to the first parameter register written with the parameter as a first numerical value;
the operation unit fetches written parameters from the corresponding first parameter register according to the fetched calculation instruction, and includes:
the arithmetic unit takes out a parameter with a parameter state indicating bit as a first numerical value from the corresponding first parameter register according to the taken out calculation instruction;
the instruction execution method further comprises:
and the instruction cache sets the parameter state indication position corresponding to the first parameter register of the fetched parameter as a second numerical value.
7. The instruction execution method of claim 1, wherein after the instruction sorter writes the compute instruction into an instruction register in the instruction cache, further comprising:
the instruction cache updates a write address of the instruction register.
8. The instruction execution method of claim 1, wherein after the arithmetic unit fetches a next compute instruction from the instruction register, further comprising:
the instruction cache updates the read address of the instruction register.
9. The instruction execution method of claim 1, further comprising:
if the class is a central processing unit instruction, the instruction classifier sends the central processing unit instruction to a central processing arithmetic unit;
the central processing arithmetic unit executes the central processing unit instruction.
10. An instruction execution apparatus comprising:
an instruction cache, the instruction cache comprising a plurality of entries, each entry comprising a first parameter register and an instruction register;
the instruction classifier is used for identifying the category of the current input instruction; if the type is a parameter configuration instruction, writing corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction; if the category is a calculation instruction, writing the calculation instruction into the instruction register in the instruction cache;
and the arithmetic unit is used for taking out the next calculation instruction from the instruction register when detecting that the instruction register is not empty, taking out the written parameter from the corresponding first parameter register according to the taken out calculation instruction, and updating the taken parameter into a second parameter register in the arithmetic unit for calculation.
11. The instruction execution apparatus of claim 10, further comprising: a state detection unit;
the instruction classifier is further to: if the type is a hardware synchronization instruction, sending a first read state instruction to the state detection unit; stopping executing the step of identifying the category of the current input instruction according to the received first waiting notification information;
the state detection unit is used for: detecting the state of the instruction register and the state of the arithmetic unit according to the first read state instruction; and sending the first waiting notification information to the instruction classifier when detecting that the instruction register is not empty or the arithmetic unit is in a busy state.
12. The instruction execution apparatus of claim 11, wherein the state detection unit is further to: when detecting that the instruction register is empty and the arithmetic unit is in an idle state, sending first stop waiting notification information to the instruction classifier;
the instruction classifier is further to: and continuing to execute the step of identifying the category of the current input instruction according to the first stop-and-wait notification information.
13. The instruction execution apparatus of claim 10, further comprising: a state detection unit;
the instruction classifier is further to: sending a second read state instruction to the state detection unit;
the state detection unit is used for: detecting the state of the first parameter register according to the second read state instruction; when the first parameter register is detected to be full, second waiting notification information is sent to the instruction classifier;
the instruction classifier is further to: and according to the second waiting notification information, stopping executing the step of writing the corresponding parameters into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction.
14. The instruction execution apparatus of claim 13, wherein the state detection unit is further to: when detecting that the first parameter register is not full, sending second stop waiting notification information to the instruction classifier;
the instruction classifier is further to: and according to the second stop waiting notification information, continuing to execute the step of writing the corresponding parameter into the corresponding first parameter register in the instruction cache according to the parameter configuration instruction.
15. The instruction execution apparatus of claim 10, wherein the instruction cache is to: setting a parameter state indication position corresponding to the first parameter register written with the parameter as a first numerical value; setting a parameter state indicating position corresponding to the first parameter register with the parameter taken out as a second numerical value;
the arithmetic unit is specifically configured to: and fetching the parameter with the parameter state indication bit being the first numerical value from the corresponding first parameter register according to the fetched calculation instruction.
16. The instruction execution apparatus of claim 10, wherein the instruction cache is to:
after the instruction classifier writes the computation instruction into the instruction register in the instruction cache, updating a write address of the instruction register.
17. The instruction execution apparatus of claim 10, wherein the instruction cache is to:
and after the arithmetic unit fetches the next calculation instruction from the instruction register, updating the read address of the instruction register.
18. The instruction execution apparatus of claim 10, further comprising: a central processing arithmetic unit;
the instruction classifier is further to: if the class is a central processing unit instruction, the instruction classifier sends the central processing unit instruction to a central processing arithmetic unit;
the central processing arithmetic unit is used for: and executing the central processor instruction.
19. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the instruction execution method of any one of claims 1-9.
20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the instruction execution method of any one of claims 1-9.
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