CN112542482A

CN112542482A - Monolithic heterogeneous integrated structure of passive cavity type single crystal FBAR and active GaN HEMT

Info

Publication number: CN112542482A
Application number: CN202011392822.0A
Authority: CN
Inventors: 董树荣; 轩伟鹏; 金浩; 骆季奎
Original assignee: Heining Bernstein Biotechnology Co ltd
Current assignee: Hangzhou Shuxin Electronic Technology Co ltd
Priority date: 2020-12-02
Filing date: 2020-12-02
Publication date: 2021-03-23
Also published as: WO2022116395A1

Abstract

The invention relates to a monolithic heterogeneous integrated structure of a passive cavity type single crystal FBAR and an active GaN HEMT, which comprises a supporting substrate, a bonding adhesion layer, a thinned epitaxial substrate, a GaN HEMT device positioned on the thinned epitaxial substrate, a cavity type single crystal FBAR device positioned on the supporting substrate and interconnection metal between the FBAR and the GaN HEMT device. The invention improves the reliability, power capacity and integration level of the integrated chip by a monolithic heterogeneous integration mode, can be used for realizing a monolithic integrated ultra-low-phase oscillation chip of an FBAR and a GaN HEMT, a monolithic integrated amplifier chip of an FBAR filter and a GaN-based power amplifier, and further realizes a monolithic integrated radio frequency front-end chip, thereby improving the performances of the radio frequency front-end chip such as reliability, power capacity, integration level and the like, and meeting the high-performance application requirements of frequency bands of 5GHz and above.

Description

Monolithic heterogeneous integrated structure of passive cavity type single crystal FBAR and active GaN HEMT

Technical Field

The invention relates to the technical field of semiconductors, in particular to a monolithic heterogeneous integrated structure of a passive cavity type single crystal FBAR and an active GaN HEMT.

Background

The high-frequency 5GHz and above frequency band wireless transceiver circuit has wide application scenes in military and civil fields, and the research and development of a high-performance 5GHz frequency band radio frequency front-end chip has important significance. In the future, wireless communication puts high technical requirements on radio frequency front-end wireless transceiver chips with frequency bands of 5GHz and above, including the requirement of broadband with frequency bands of 5GHz and above, ultrahigh frequency, high power, high isolation, low noise, high integration and the like. In the face of the requirement of a radio frequency front-end chip in a frequency band of 5GHz or above, the traditional silicon-based CMOS technology cannot meet the requirement of high power and low noise in the frequency band, and the requirements are specifically shown as follows:

(1) conventional active passive devices have been unable to meet the high performance requirements of 5G applications. For the application of frequency bands of 5GHz and above, the current silicon-based circuit can not meet the requirement of high power, even gallium arsenide (GaAs) circuits can not meet the requirement in some occasions, and the high-power gallium nitride (GaN) compound semiconductor technology must be used. GaN-based high electron mobility transistors (hereinafter GaN HEMTs) are capable of outputting greater power and providing higher efficiency than conventional silicon-based or gallium arsenide devices. In addition, in terms of passive filters, the conventional dielectric ceramic filter and the filter of the surface Acoustic wave device cannot meet the requirement of the 5G frequency band due to process compatibility, resonant frequency and the like, and a Film Bulk Acoustic Resonator (FBAR) is the only filter solution of the current 5G terminal. The FBAR is a novel radio frequency MEMS device, the basic structure of the FBAR is a piezoelectric stack of a sandwich structure consisting of a piezoelectric film and upper and lower electrodes, the FBAR can be considered as an extremely thinned crystal oscillator plate in working principle, the FBAR has high working frequency (0.5-30GHz), ultrahigh quality factor Q (1000 plus 50000), and can be compatible with a series of advantages of semiconductor technology and the like. The piezoelectric film materials used in the current FBARs are mainly obtained by magnetron sputtering. The thickness of the piezoelectric layer of the FBAR is 500-600nm in the frequency band above 5GHz, and under the thickness, the traditional polycrystalline material prepared by magnetron sputtering cannot have good piezoelectric characteristics, and a single crystal piezoelectric film is required to obtain smaller loss, a larger Q value and a higher electromechanical coupling coefficient. Therefore, the mainstream technology of the frequency bands above 5GHz is a single crystal film FBAR device, which is a future technical trend.

(2) The traditional chip integration packaging mode (including System In Package (SiP) integrated, heterogeneous chip binding integration technology, etc.) can not meet the requirements of radio frequency front end chips with frequency bands of 5GHz and above. For example, in the radio frequency front end of a current mobile phone, a low noise amplifier, a power amplifier, a radio frequency filter, a frequency source and the like are mainly packaged into a radio frequency front end module by a circuit board or SiP component. However, as the frequency increases, the distribution effect increases, the existing multi-chip SiP component type integration or heterogeneous chip binding integration technology can bring about huge parasitic effect, and simultaneously, the impedance matching between chips is difficult, and the performance of the ultrahigh frequency 5GHz and above frequency bands of the chips is greatly reduced. Therefore, a monolithic heterogeneous integration technology needs to be developed, in which a passive device and an active device are integrated in one chip, so that the chip size is reduced, and the performance of the chip is improved to meet the application requirements of the frequency bands of 5GHz and above.

At present, a module where an active GaN-based electronic device is located and a module where a passive FBAR is located are integrated together in a SiP integration mode, and the reliability, the power capacity, the matching impedance, the integration level and the volume of an oscillator and even a radio frequency front-end transmitting-receiving chip module formed in the integration mode are inferior to those of single-chip integration.

Disclosure of Invention

The invention provides a structure and a process preparation method for monolithic heterogeneous integration of a passive cavity type single crystal FBAR and an active GaN HEMT device, aiming at the defect that a module where an active GaN-based electronic device is located and a module where a passive FBAR is located in an existing radio frequency front-end chip are integrated together in an SIP (session initiation protocol) integration mode, and the structure and the process preparation method can be used for realizing an ultralow phase noise oscillation chip with monolithic integration of the FBAR and the GaN HEMT, realizing a monolithic integration amplifier chip of an FBAR filter and a GaN-based power amplifier, and further realizing the monolithic integration radio frequency front-end chip, so that the performances of the radio frequency front-end chip, such as reliability, power capacity, integration level and the like, are improved.

The purpose of the invention is realized by the following technical scheme:

a monolithic heteroisomeric integrated structure of a passive cavity-type single crystal FBAR with an active GaN HEMT, the structure comprising:

a support substrate;

the bonding adhesion layer and the epitaxial substrate layer are sequentially arranged on the supporting substrate;

a cavity-type single crystal FBAR device located on the support substrate;

the active GaN HEMT device is positioned on the epitaxial substrate layer;

a first interconnect metal layer located between the cavity-type single crystal FBAR device and the active GaN HEMT;

the cavity-type single crystal FBAR device includes:

the single crystal piezoelectric layer covers part of the epitaxial substrate layer, and partial areas of the epitaxial substrate layer and the bonding adhesion layer are absent, so that a cavity is formed between the single crystal piezoelectric layer and the supporting substrate;

an upper electrode located on a side of the single crystal piezoelectric layer away from the support substrate;

a lower electrode located on a side of the single crystal piezoelectric layer facing the support substrate, the lower electrode being located within the cavity;

a second interconnect metal layer covering the upper electrode layer, a portion of the single crystal piezoelectric layer, and a portion of the epitaxial substrate layer;

the active GaN HEMT device includes:

the GaN hetero-epitaxial layer covers a part of the epitaxial substrate layer, and an ion implantation area for implanting ions is formed in the GaN hetero-epitaxial layer;

the source electrode and the drain electrode are both positioned on the GaN heteroepitaxial layer;

a passivation layer covering the GaN heteroepitaxial layer and exposing the source electrode and the drain electrode;

a gate electrode on the passivation layer and inserted into the gate groove of the passivation layer;

a silicon nitride dielectric protection layer covering the gate electrode and the passivation layer and exposing the source electrode and the drain electrode;

the third interconnection metal layer covers part of the silicon nitride dielectric protection layer and is connected with the drain electrode through the first through hole of the silicon nitride dielectric protection layer and the passivation layer;

the first interconnection metal layer covers a part of the silicon nitride dielectric protection layer, a part of the epitaxial substrate layer and a part of the single crystal piezoelectric layer, is connected with the source electrode through a second through hole of the silicon nitride dielectric protection layer and the passivation layer, and is connected with the lower electrode through a third through hole in the single crystal piezoelectric layer.

Further, the GaN heteroepitaxial layer is respectively a GaN buffer layer, a barrier layer and a cap layer from bottom to top; the thickness of the GaN buffer layer is 1-3 mu m, the barrier layer is made of a material with lattice constant difference with GaN, the thickness of the barrier layer is 5-30nm, and the material of the cap layer is GaN or AlGaN, and the thickness of the cap layer is 2-5 nm.

Further, the material of the source electrode and the drain electrode is a laminated combination of metal Ti/Al/Ni/Au, wherein Ti is on the bottommost layer, Al, Ni and Au are sequentially arranged on the Ti, and the total thickness is 200-400 nm.

Further, the material of the gate electrode is a metal stack combination of metal Ni/Au, wherein Ni is on the bottom layer, Au is on the bottom layer, and the total thickness is 100-300 nm.

Further, the passivation layer is silicon nitride and has a thickness of 100-200 nm.

Further, the first interconnection metal layer, the second interconnection metal layer and the third interconnection metal layer are made of one or any combination of molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten and nickel, and the thickness of the first interconnection metal layer, the second interconnection metal layer and the third interconnection metal layer is 10-5000 nm.

Further, the supporting substrate is a silicon wafer, the bonding adhesion layer is silicon dioxide or silicon, and the epitaxial substrate layer is selected from one or a combination of more of silicon carbide, silicon and sapphire;

the single crystal piezoelectric layer is selected from one or a combination of more of aluminum nitride single crystal, doped aluminum nitride single crystal, gallium nitride, zinc oxide single crystal, lithium nickelate single crystal, lead zirconate titanate single crystal, lithium niobate single crystal, lithium zirconate single crystal, lithium tantalate single crystal, lithium tetraborate single crystal, bismuth germanate single crystal, bismuth silicate single crystal, cadmium sulfide single crystal and quartz single crystal, and the thickness is 10-10000 nm;

the upper electrode and the lower electrode are made of one or any combination of molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten and nickel, and the thickness of the upper electrode and the lower electrode is 10-5000 nm.

A preparation method of a monolithic heterogeneous integrated structure of a passive cavity type single crystal FBAR and an active GaN HEMT specifically comprises the following steps:

the method comprises the following steps: respectively selecting regions on the epitaxial substrate layer by using MOCVD (metal organic chemical vapor deposition), and extending a single crystal piezoelectric layer and a GaN heteroepitaxial layer;

step two: sequentially depositing metal on the GaN heteroepitaxial layer by adopting an electron beam evaporation process to form a source electrode and a drain electrode of the GaN HEMT device, and then annealing at high temperature in a nitrogen atmosphere to form ohmic contact;

step three: adopting an ion implantation process to destroy two-dimensional electron gas in the GaN heteroepitaxial layer and forming electrical isolation between the GaN HEMTs;

step four: depositing a passivation layer on the whole wafer by adopting a plasma enhanced chemical vapor deposition process, and carrying out surface passivation on the GaN HEMT device;

step five: etching the passivation layer by adopting a dry etching process to form a gate groove and open holes for the source electrode and the drain electrode so as to expose the source electrode and the drain electrode, and etching off the passivation layer on the mask for selective area epitaxy;

step six: evaporating metal at the position of the gate groove by adopting an electron beam evaporation process to form a T-shaped gate electrode, wherein the bottom layer metal of the gate electrode is Ni;

step seven: depositing a dielectric protection layer on the whole wafer by adopting a plasma enhanced chemical vapor deposition process to protect the prepared GaN HEMT;

step eight: etching the dielectric protection layer on the mask of the selected region epitaxy by adopting a dry etching process, simultaneously etching the dielectric protection layers on the gate electrode, the source electrode and the drain electrode of the GaN HEMT device, and opening holes on the gate electrode, the source electrode and the drain electrode to expose the gate electrode, the source electrode and the drain electrode;

step nine: protecting the GaN HEMT device region by photoresist, and corroding a mask on the single crystal piezoelectric layer by a wet method;

step ten: forming an upper electrode on the single crystal piezoelectric layer by using a magnetron sputtering or electron beam evaporation process;

step eleven: etching the single crystal piezoelectric layer by adopting a dry etching process to form a third through hole;

step twelve: evaporating interconnection metal by adopting an electron beam evaporation process to form interconnection of the upper electrode of the FBAR and the metal of the GaN HEMT, filling the third through hole formed in the step eleven, and preparing for interconnection of the lower electrode of the FBAR and the metal of the GaN HEMT;

step thirteen: and spin-coating temporary bonding glue on the front surface of the wafer, and bonding the front surface of the wafer and the front surface of the support substrate together.

Fourteen steps: thinning the epitaxial substrate layer, and carrying out chemical mechanical polishing;

step fifteen: depositing a bonding adhesion layer on the back of the thinned and polished epitaxial substrate layer by adopting a plasma enhanced chemical vapor deposition mode to prepare for bonding a supporting substrate at the back;

sixthly, the steps are as follows: selectively etching the back of the wafer by adopting a dry method, and etching the bonding adhesion layer and the thinned and polished epitaxial substrate layer until the single crystal piezoelectric layer is exposed;

seventeen steps: depositing the lower electrode metal of the FBAR by adopting a magnetron sputtering or electron beam evaporation process, and simultaneously forming metal interconnection of the FBAR lower electrode and the GaN HEMT;

eighteen steps: bonding the back surface of the thinned and polished epitaxial substrate with a support substrate through a bonding adhesion layer to form a cavity structure of the FBAR;

nineteen steps: and dissociating the front surface of the wafer and the support substrate temporarily bonded in the step thirteen by adopting a thermal slip mode, and then removing the temporary bonding glue by using a temporary bonding glue cleaning agent, thereby completing the monolithic heterogeneous integration process of the cavity type single crystal FBAR device and the GaN HEMT device.

Further, the temperature of the high-temperature annealing in the second step is 850-; the dry etching process in the eighth step and the sixteenth step is a reactive ion etching or inductively coupled plasma etching process.

The invention has the following beneficial effects:

the invention combines the advantages of low loss, high Q value and high electromechanical coupling coefficient of the passive cavity type single crystal FBAR with the advantages of high power and high efficiency of an active GaN HEMT device, improves the reliability, power capacity and integration level of an integrated chip by a monolithic heterogeneous integration mode, can be used for realizing an ultra-low phase oscillation chip monolithically integrated with the GaN HEMT, a monolithic integrated amplifier chip for realizing an FBAR filter and a GaN-based power amplifier, and further realizing a monolithic integrated radio frequency front-end chip, thereby improving the performances of the radio frequency front-end chip such as reliability, power capacity, integration level and the like, and meeting the high-performance application requirements of the frequency band of 5GHz and above.

Drawings

FIG. 1 is a schematic structural diagram of a passive cavity type single crystal FBAR and active GaN HEMT monolithic heterogeneous integrated chip;

FIG. 2 is a schematic structural view of a selective epitaxial GaN heteroepitaxial layer;

fig. 3 to 21 are flow charts of a process for manufacturing a passive cavity type single crystal FBAR and active GaN HEMT monolithic heterologously integrated chip structure in an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments, and the objects and effects of the present invention will become more apparent, it being understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

As an example, as shown in fig. 1, a monolithic heterogeneous integrated structure of a passive cavity-type single-crystal FBAR and an active GaN HEMT according to the present invention is shown in fig. 3, and the chip structure includes a supporting silicon wafer 109, a silicon dioxide bonding adhesion layer 108 and a thinned silicon carbide (SiC) epitaxial substrate layer 107 sequentially disposed on the supporting substrate, an active GaN HEMT device 300 disposed on the thinned SiC epitaxial substrate layer 107, a cavity-type single-crystal FBAR device 200 disposed on the supporting silicon wafer 109, and a first interconnection metal layer 104-1 between the GaN HEMT device 300 and the cavity-type single-crystal FBAR device 200.

The cavity-type single crystal FBAR device in this embodiment comprises a single crystal AlN piezoelectric layer 201 and upper and

lower electrodes

202 and 203 overlying the single crystal AlN piezoelectric layer 201, and a second interconnect metal layer 104-2 overlying the upper electrode 202, a portion of the single crystal AlN piezoelectric layer 201, and a portion of the SiC epitaxial substrate layer 107. The single crystal AlN piezoelectric layer 201 covers part of the SiC epitaxial substrate layer 107, and partial areas of the SiC epitaxial substrate layer 107 and the silicon dioxide bonding adhesion layer 108 are lost, so that a cavity 204 is formed on the silicon dioxide bonding adhesion layer 108 by bonding the supporting silicon wafer 109.

The thickness of the single crystal AlN piezoelectric layer 201 was 500 nm.

The material of the upper electrode 202 and the lower electrode 203 of the cavity-type single crystal FBAR device 200 is magnetron sputtered molybdenum (Mo) with a thickness of 250 nm.

The GaN HEMT device 300 is electrically isolated by ion implantation, and the GaN HEMT device 300 includes a GaN hetero-epitaxial layer 301, a source electrode 302, a drain electrode 303, an ion implantation region 304, a passivation layer 305, a gate electrode 307, a dielectric protection layer 308, and a third interconnection metal layer 104-3.

The GaN hetero-epitaxial layer 301 covers a part of the thinned silicon carbide (SiC) epitaxial substrate layer 107, and the GaN hetero-epitaxial layer 301 has an ion implantation region 304 in which ions are implanted. The source electrode 302 and the drain electrode 303 are both located on the GaN heteroepitaxial layer 301. The passivation layer 305 covers the GaN hetero-epitaxial layer 301 and exposes the source electrode 302 and the drain electrode 303. A gate electrode 307 is located on the passivation layer 305.

As shown in fig. 2, the structure of GaN heteroepitaxial layer 301 from bottom to top is: the GaN buffer layer, the AlGaN barrier layer and the GaN cap layer. The thickness of the GaN buffer layer is 2 mu m, the thickness of the AlGaN barrier layer is 30nm, and the thickness of the GaN cap layer is 2 nm. The material of the source electrode 302 and the drain electrode 303 is a metal laminated combination of metal Ti/Al/Ni/Au, wherein Ti is at the bottommost layer, and Al, Ni and Au are sequentially arranged on the Ti. Wherein the thickness of the metal Ti is 20nm, the thickness of the metal Al is 130nm, the thickness of the metal Ni is 50nm, and the thickness of the metal Au is 40 nm.

The electrode material of the gate electrode 307 is a metal stack combination of metal Ni/Au, wherein the metal Ni is on the bottom layer as an adhesion layer, and the metal Au is on the adhesion layer, wherein the thickness of the metal Ni is 20nm, and the thickness of the metal Au is 200 nm.

The passivation layer 305 is silicon nitride, wherein the silicon nitride thickness is 100 nm.

The material of the dielectric protection layer 308 is silicon nitride, wherein the thickness of the silicon nitride is 200 nm.

The first interconnection metal layer 104-1, the second interconnection metal layer 104-2 and the third interconnection metal layer 104-3 are made of Ti/Au metal lamination layers, wherein Ti is bottom metal and is used as an adhesion layer, the thickness of Ti is 20nm, and the thickness of Au is 150 nm.

The preparation method of the monolithic heterogeneous integrated chip structure of the passive cavity type single crystal FBAR and the active GaN HEMT in the embodiment of the invention is shown in fig. 3, and the preparation method comprises the following steps:

the method comprises the following steps: on the SiC epitaxial substrate layer 107, single-crystal AlN piezoelectric thin film 201 and GaN hetero-epitaxial layer 301 were selectively epitaxial by Metal Organic Chemical Vapor Deposition (MOCVD), respectively, as shown in fig. 3.

The mask used for selective epitaxy is a silicon dioxide mask 102 with a thickness of 200 nm. The thickness of the single crystal AlN piezoelectric film 201 was 500 nm.

Wherein, the structure of the GaN heteroepitaxial layer 301 is from bottom to top: 2 μm GaN buffer layer, 30nm AlGaN barrier layer, and 2nm GaN cap layer.

Step two: by adopting an electron beam evaporation process, metals of Ti, Al, Ni and Au are sequentially deposited on the GaN heteroepitaxial layer 301 to form a source electrode 302 and a drain electrode 303 of the GaN HEMT device, and then high-temperature annealing is carried out in a nitrogen atmosphere to form ohmic contact, as shown in FIG. 4.

Wherein the thickness of the metal Ti is 20nm, the thickness of the metal Al is 130nm, the thickness of the metal Ni is 50nm, the thickness of the metal Au is 40nm, the high-temperature annealing temperature in the nitrogen atmosphere is 850 ℃, and the annealing time is 30 s.

Step three: an ion implantation process is used to break the two-dimensional electron gas in the GaN heteroepitaxial layer 301 and form electrical isolation between the GaN HEMT devices, as shown in fig. 5.

Wherein the ion implantation region 304 is implanted with boron ionsThe dosage is 2X 10¹⁴cm^-2The implantation energy is 120 keV.

Step four: a plasma enhanced chemical vapor deposition process is used to deposit a passivation layer 305 over the entire wafer to passivate the surface of the GaN HEMT device as shown in fig. 6.

Wherein the deposited passivation layer 305 is silicon nitride and has a thickness of 100 nm.

Step five: using an inductively coupled plasma etching process, the silicon nitride passivation layer 305 is etched to form a gate trench 306, and simultaneously, the silicon nitride passivation layer 305 on the source electrode 302 and the drain electrode 303 is etched to expose the source electrode 302 and the drain electrode 303, and the silicon nitride passivation layer 305 on the silicon dioxide mask 102 for selective area epitaxy is etched away, as shown in fig. 7.

The etching gas is selected from fluorine-based gas and mixed gas.

Step six: an electron beam evaporation process is used to evaporate metal Ni/Au as gate electrode 307 at the location of gate trench 306 to form a T-shaped gate, as shown in fig. 8.

Wherein the thickness of the metal Ni is 20nm, and the thickness of the metal Au is 200 nm.

Step seven: a plasma enhanced chemical vapor deposition process is used to deposit a silicon nitride dielectric protection layer 308 on the whole wafer to protect the prepared GaN HEMT device, as shown in fig. 9.

Wherein the thickness of the silicon nitride dielectric protection layer 308 is 200 nm.

Step eight: by using an inductively coupled plasma etching process, the silicon nitride dielectric protection layer 308 on the silicon dioxide mask 102 of the selective area epitaxy is etched, and simultaneously, the silicon nitride dielectric protection layer 308 on the source electrode 302, the drain electrode 303 and the gate electrode 307 of the GaN HEMT device is etched, so that the source electrode 302, the drain electrode 303 and the gate electrode 307 are exposed, as shown in fig. 10. Since the etched opening region of the gate electrode 307 is not in one cross section with the etched opening regions of the source electrode 302 and the drain electrode 303, the etched opening region of the gate electrode 307 is not shown in fig. 10.

The etching gas is fluorine-containing gas or mixed gas.

Step nine: the GaN HEMT device 300 is protected with photoresist and the silicon dioxide mask 102 on the single crystal AlN piezoelectric layer 201 is etched with a BOE solution as shown in fig. 11.

Step ten: an upper electrode 202 was formed on the single crystal AlN piezoelectric layer 201 by a magnetron sputtering process, as shown in fig. 12.

Wherein the upper electrode 202 is made of molybdenum and has a thickness of 250nm, as shown in fig. 12.

Step eleven: the third through hole 103 is formed by etching the single crystal AlN piezoelectric layer 201 using an inductively coupled plasma etching process, as shown in fig. 13.

The etching gas is selected from chlorine-based gas and mixed gas.

Step twelve: the interconnection metal 104 is evaporated by an electron beam evaporation process to form the metal interconnection of the FBAR upper electrode 202 and the GaN HEMT, and the third through hole 103 is filled in preparation for the metal interconnection of the FBAR lower electrode and the GaN HEMT, as shown in fig. 14.

The interconnection metal 104 is a metal stack of Ti/Au, where Ti is a bottom metal as an adhesion layer, Ti has a thickness of 20nm, and Au has a thickness of 150 nm.

Step thirteen: a temporary bonding glue 105 is spun on the front surface of the wafer, and the front surface of the wafer and the front surface of the temporarily bonded silicon wafer 106 are bonded together after baking, as shown in fig. 15.

Fourteen steps: the SiC epitaxial substrate layer 107 is thinned to make the SiC epitaxial substrate layer 107 thinned to 100 μm, and chemical mechanical polishing is performed to obtain the thinned and polished SiC epitaxial substrate 107, as shown in fig. 16.

Step fifteen: and depositing a 1 mu m thick silicon dioxide bonding adhesion layer 108 on the back surface of the thinned and polished SiC epitaxial substrate layer 107 by using a plasma enhanced chemical vapor deposition mode to prepare for bonding a supporting silicon wafer later, as shown in FIG. 17.

Sixthly, the steps are as follows: the silicon dioxide bonding adhesion layer 108 and the thinned and polished SiC epitaxial substrate layer 107 are etched from the back side of the wafer using an inductively coupled plasma etching process until the single crystal piezoelectric layer 201 is exposed, as shown in fig. 18.

The selected etching gas is etching gas containing fluorine radicals and mixed gas.

Seventeen steps: the lower electrode 203 of the FBAR is deposited using a magnetron sputtering process while forming a metal interconnection of the lower electrode 203 of the FBAR and the GaN HEMT as shown in fig. 19.

Wherein the lower electrode material is molybdenum, and the thickness is 300 nm.

Eighteen steps: the polished-down SiC epitaxial substrate layer 107 is bonded to a supporting silicon wafer 109 by a silicon dioxide bond adhesion layer 108 to form a cavity 204 of the FBAR, as shown in fig. 20.

Nineteen steps: and dissociating the front surface of the wafer from the temporarily bonded silicon wafer 106 in the step thirteen by adopting a thermal slip mode, and then removing the temporary bonding glue 105 by using a temporary bonding glue cleaning agent, thereby completing the monolithic heterogeneous integration process of the cavity type single crystal FBAR device 200 and the GaN HEMT device 300, as shown in FIG. 21.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and although the invention has been described in detail with reference to the foregoing examples, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made and equivalents may be substituted for elements thereof. All modifications, equivalents and the like which come within the spirit and principle of the invention are intended to be included within the scope of the invention.

Claims

1. A monolithic heteroisomeric integrated structure of a passive cavity-type single crystal FBAR with an active GaN HEMT, comprising:

a support substrate;

a cavity-type single crystal FBAR device located on the support substrate;

the active GaN HEMT device is positioned on the epitaxial substrate layer;

the cavity-type single crystal FBAR device includes:

a lower electrode located on a side of the single crystal piezoelectric layer facing the support substrate, and the lower electrode is located within the cavity.

the active GaN HEMT device includes:

2. The monolithic heterogeneous integrated structure of the passive cavity-type single crystal FBAR and the active GaN HEMT according to claim 1, wherein the GaN heteroepitaxial layer is a GaN buffer layer, a barrier layer and a cap layer from bottom to top; the thickness of the GaN buffer layer is 1-3 mu m, the barrier layer is made of a material with lattice constant difference with GaN, the thickness of the barrier layer is 5-30nm, and the material of the cap layer is GaN or AlGaN, and the thickness of the cap layer is 2-5 nm.

3. The monolithic heterogeneous integrated structure of passive cavity-type single-crystal FBAR and active GaN HEMT as claimed in claim 1, wherein the source and drain electrodes are made of a stacked combination of metal Ti/Al/Ni/Au, where Ti is at the bottom layer, and Al, Ni, Au are sequentially on it, and the total thickness is 200-400 nm.

4. The monolithic heterogeneous integrated structure of passive cavity-type single-crystal FBAR and active GaN HEMT as claimed in claim 1, wherein the gate electrode is made of a metal stack combination of Ni/Au, wherein Ni is on the bottom layer, Au is on it, and the total thickness is 100-300 nm.

5. The monolithic heterogeneous integrated structure of passive cavity-type single crystal FBAR and active GaN HEMT as claimed in claim 1, wherein the passivation layer is silicon nitride with a thickness of 100-200 nm.

6. The monolithic heterogeneous integrated structure of the passive cavity type single crystal FBAR and the active GaN HEMT according to claim 1, wherein the material of the first interconnection metal layer, the second interconnection metal layer and the third interconnection metal layer is one or any combination of molybdenum, gold, platinum, copper, aluminum, silver, titanium, tungsten and nickel, and the thickness is 10-5000 nm.

7. The monolithic heterogeneous integrated structure of the passive cavity type single crystal FBAR and the active GaN HEMT according to claim 1, wherein the supporting substrate is a silicon wafer, the bonding adhesion layer is silicon dioxide or silicon, and the epitaxial substrate layer is selected from one or a combination of silicon carbide, silicon and sapphire;

8. A preparation method of a monolithic heterogeneous integrated structure of a passive cavity type single crystal FBAR and an active GaN HEMT is characterized by comprising the following steps:

9. The method as claimed in claim 8, wherein the temperature of the high temperature annealing in step two is 850-890 ℃, and the annealing time is 30-40 s; the dry etching process in the eighth step and the sixteenth step is a reactive ion etching or inductively coupled plasma etching process.