CN112542452A

CN112542452A - Multiple edge through-silicon-vias and related systems, methods, and apparatus

Info

Publication number: CN112542452A
Application number: CN202010769221.0A
Authority: CN
Inventors: 西冈直久
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-09-20
Filing date: 2020-08-03
Publication date: 2021-03-23
Also published as: US20210088586A1; US11275111B2

Abstract

A plurality of edge through-silicon vias TSV and related systems, methods, and apparatuses are disclosed. An electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at a perimeter of the chip stack. The TSV regions of the chip stack are located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

Description

Multiple edge through-silicon-vias and related systems, methods, and apparatus

Priority requirement

The present application claims benefit of an application date of U.S. patent application serial No. 16/577,243 entitled "multiple Edge Through-Silicon Vias and Related Systems, Methods, and Devices" filed on 20/9/2019.

Technical Field

The present disclosure relates generally to identifying a minimum acceptable Through Silicon Via (TSV) distance from a side edge of a chip stack, and more particularly to identifying a minimum acceptable TSV distance in a memory device.

Background

Three-dimensional integrated circuits may be formed by stacking semiconductor chips having electronic circuitry formed therein or thereon. These stacked semiconductor chips may be vertically interconnected. For example, stacked semiconductor chips may be interconnected using TSVs.

Disclosure of Invention

In some embodiments, an electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at a perimeter of the chip stack. The through-silicon via regions (TSV regions) of the chip stack are located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

In some embodiments, a method of determining a minimum acceptable TSV distance to one or more side edges of a chip stack includes performing a conductivity test on a first TSV positioned a first distance from the one or more side edges of the chip stack; performing the conductivity test on a second TSV positioned a second distance from the one or more side edges, the second distance being shorter than the first distance; and identifying the minimum acceptable TSV distance to the one or more side edges as the first distance in response to determining: the first TSV passes the conductivity test, the second TSV fails the conductivity test and no other TSV farther from the one or more side edges than the first TSV fails the conductivity test.

In some embodiments, a memory device includes a chip stack, a plurality of TSVs, and control circuitry. The chip stack includes a logic die and a plurality of core dies stacked on the logic die. The plurality of TSVs are positioned at different distances from one or more side edges of the chip stack. An ordered sequence is associated with the plurality of TSVs from the TSV furthest from the one or more side edges to the TSV closest to the one or more side edges. The control circuitry is located on or in the logic die. The control circuitry is configured to perform a conductivity test on each of the plurality of TSVs; identifying a TSV of the plurality of TSVs that is the last consecutive TSV in the ordered sequence that passed the conductivity test if none of the preceding TSVs in the ordered sequence failed the conductivity test; and determining that the minimum acceptable TSV distance from the one or more side edges is the same as the distance from the identified TSV to the one or more side edges.

Drawings

While the present disclosure concludes with claims particularly pointing out and distinctly claiming specific embodiments, various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

FIG. 1 is a top view of an electronic device according to some embodiments;

FIG. 2 is a cross-sectional view of a portion of the electronic device of FIG. 1, the cross-section being taken at cross-section 2 of FIG. 1;

fig. 3 is a flow diagram showing a method of determining a minimum acceptable TSV distance to one or more side edges of a chip stack in accordance with some embodiments;

FIG. 4 is a cross-sectional view of a chip stack according to some embodiments;

FIG. 5 is a flow chart illustrating a method of performing a conductivity test according to some embodiments;

FIG. 6 is a top view of a chip stack according to some embodiments;

FIG. 7 is a top view of the chip stack of FIG. 6 demonstrating an example of signal management according to some embodiments;

FIG. 8 is a schematic diagram of a multiplexing circuit according to some embodiments;

FIG. 9 is a block diagram of an example of a logic die of the electronic device 100 of FIG. 1;

FIG. 10 is a block diagram of a high bandwidth memory HBM + system according to some embodiments; and is

FIG. 11 is a block diagram of a computing system according to some embodiments.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments implemented herein may be utilized, and structural, material, and process changes may be made without departing from the scope of the present disclosure.

The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations which are employed to describe the embodiments of the present disclosure. In some cases, similar structures or components in the various figures may retain the same or similar reference numbers for the convenience of the reader; however, similarity of reference numerals does not necessarily mean that structures or components are the same in size, composition, configuration, or any other property.

The following description may contain examples that help enable those of ordinary skill in the art to practice the disclosed embodiments. The use of the terms "exemplary," "by way of example," and "such as" are meant to be illustrative of the relevant description, and although the scope of the disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the disclosure to the specific components, steps, features, functions, etc.

It will be readily understood that the components of the embodiments, as generally described herein, and illustrated in the figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of the various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

Furthermore, the particular embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise indicated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure in unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between various blocks are examples of specific implementations. It will be apparent to those of ordinary skill in the art that the present disclosure may be practiced with many other partitioning solutions. In most cases, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the abilities of persons of ordinary skill in the relevant art.

Those of ordinary skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of illustration and description, some of the figures may show a signal as a single signal. Those of ordinary skill in the art will appreciate that the signals may represent a bus of signals, where the bus may be of various bit widths and the present disclosure may be implemented on any number of data signals including a single data signal.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with: a general purpose processor, a special purpose processor, a Digital Signal Processor (DSP), an Integrated Circuit (IC), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor, which may also be referred to herein as a host processor or simply a host, may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and the general purpose computer is configured to execute computing instructions (e.g., software code) related to embodiments of the present disclosure.

Embodiments may be described in terms of procedures depicted as a flowchart (or flow diagram) structure or block diagram. Although a flowchart may describe the operational acts as a sequential process, many of the acts can be performed in another order, in parallel, or substantially concurrently. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or a combination thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

Unless such limitations are expressly stated, the use of any reference herein to elements such as "first," "second," etc., does not limit the number or order of those elements. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not mean that only two elements may be employed or that the first element must somehow precede the second element. In addition, a set of elements may include one or more elements unless otherwise specified.

The term "substantially" as used herein with respect to a given parameter, property, or condition means and includes to the extent that a person of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a small degree of difference (e.g., difference within an acceptable tolerance). For example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

The term "chip" as used herein refers to a semiconductor wafer (e.g., a silicon wafer) having electronic circuitry formed therein or thereon. Examples of chips include memory logic chips, memory core chips, central processing unit chips, and other electronic device chips.

Fig. 1 is a top view of an electronic device 100 according to some embodiments. The electronic device 100 includes a chip stack 102 including one or more side edges 108 located at a perimeter of the chip stack 102, a TSV region 106 of the chip stack 102 located within a predetermined distance D (e.g., 230 micrometers (μ ι η)) from the one or more side edges 108. TSV region 106 is defined by side edge 108 and TSV region boundary 104 shown in fig. 1. The electronic device 100 also includes TSVs 110 positioned at various distances from the side edges 108.

Fig. 2 is a cross-sectional view of a portion of the electronic device 100 of fig. 1, the cross-section being taken at cross-section 2 of fig. 1. Referring to fig. 1 and 2 together, electronic device 100 includes a plurality of chips. For example, chip stack 102 includes chip 214, chip 216, chip 218, chip 220, and chip 222. It should be noted that chip stack 102 may contain any number of chips greater than or equal to two chips.

One of the chips in the chip stack 102 includes control circuitry 224 therein or thereon. The chip containing the control circuitry 224 may sometimes be referred to herein as a "control chip". In some embodiments, the bottom chip 214 in the chip stack 102 may include control circuitry 224 as in the example shown in fig. 2. In some embodiments, the top chip (e.g., chip 222) may contain control circuitry 224. As a specific, non-limiting example, chip 214 may include a logic die of a memory device, chip 216, chip 218, chip 220, and chip 222 may include memory core chips, and control circuitry 224 may include Direct Access (DA) control circuitry.

The chip stack 102 also includes TSVs 110, including

TSVs

202, 204, 206, 208, 210, and 212, within the TSV region 106 of the chip stack 102. Although fig. 1 and 2 show six TSVs 110, the electronic device 100 may include any number of TSVs greater than or equal to two TSVs. Each of the TSVs 110 is positioned a different distance from the side edge 108 of the chip stack 102. For example, the TSV 202 is positioned a distance D1 from the side edge 108; TSV 204 is positioned a distance D2 from side edge 108; TSV 206 is positioned a distance D2 from side edge 108; TSV 208 is located a distance D4 from side edge 108; TSV 210 is positioned a distance D5 from side edge 108; and TSV 212 is positioned a distance D6 from side edge 108.

With the TSVs 110 arranged at different distances from the side edge 108, the control circuitry 224 is configured to perform a conductivity test for each of the TSVs 110 and identify a minimum acceptable TSV distance from the side edge 108 using the results of the conductivity test. In other words, the control circuitry 224 is configured to use the results of the conductivity test to identify the limits at which well-formed TSVs can be formed. The limit may be determined to be a distance to a first TSV of the TSVs 110 if a first conductivity test of the first TSV of the TSVs 110 shows no problem and a second conductivity test of a second TSV of the TSVs 110, which is arranged adjacent to the first TSV of the TSVs 110, shows an open circuit. In other words, the control circuitry 224 is configured to perform a conductivity test on the TSVs 110 and identify the minimum acceptable TSV distance from the side edge 108 as a first distance corresponding to a first TSV of the TSVs 110 in response to determining: a first TSV of the TSVs 110 passes the conductivity test, a second TSV of the TSVs 110 adjacent to the first TSV of the TSVs 110 does not pass the conductivity test and no other TSVs 110 farther from the side edge than the first TSV of the TSVs 110 do not pass the conductivity test.

Still in other words, the ordered sequence may be associated with TSVs 110 from the TSVs furthest from the side edge 108 (TSVs 202) to the TSVs closest to the side edge 108 (TSVs 212). The control circuitry 224 is configured to perform a conductivity test on each of the TSVs 110, identifying a TSV of the TSVs 110 that is the last consecutive TSV in the ordered sequence that passes the conductivity test if none of the preceding TSVs in the ordered sequence fail the conductivity test. The control circuitry 224 is further configured to determine that the minimum acceptable TSV distance from the side edge 108 is the same as the distance from the identified TSV to the side edge 108.

As a specific, non-limiting example, the control circuitry 224 may perform a conductivity test on each of the TSVs 110, resulting in no problems in

TSVs

202, 204, 206, and 208 and open circuits in

TSVs

210 and 212. In this example, the minimum acceptable TSV distance, or the limit at which a well-formed TSV may be formed, may be determined as the distance D4 of the TSV 208 from the side edge 108.

Determining the minimum acceptable TSV distance using multiple TSVs 110 allows for evaluation of multiple different distances from the side edge 108 (e.g., D1, D2, D3, D4, D5, and D6) rather than a single distance, as compared to using a single TSV. Where only a single TSV is used, it may only be determined whether the distance of the single TSV from the side edge 108 is acceptable or unacceptable without providing the granularity provided by multiple TSVs.

Fig. 3 is a flow diagram showing a method 300 of determining a minimum acceptable TSV distance to one or more side edges of a chip stack in accordance with some embodiments. In operation 302, the method 300 performs a conductivity test on a first TSV positioned a first distance from the one or more side edges of the chip stack. Details regarding examples of conductivity tests are provided below in fig. 4 and 5.

In operation 304, the method 300 performs a conductivity test on a second TSV positioned a second distance from the one or more side edges. The second distance is shorter than the first distance. In operation 306, the method 300 identifies a minimum acceptable TSV distance from the one or more side edges as a first distance in response to determining: the first TSV passes the conductivity test, the second TSV fails the conductivity test and no other TSVs farther from the one or more side edges than the first TSV do not.

Fig. 4 is a cross-sectional view of a chip stack 400 according to some embodiments. Chip stack 400 includes a control chip 402 at the bottom of chip stack 400, an end chip 410 at the top of chip stack 400, and intermediate chips (chip 404, chip 406, and chip 408) located between control chip 402 and end chip 410. The chip stack 400 also includes TSVs 430 traversing the chip stack 400. The TSV 430 includes a first end 434 proximate the control chip 402 and a second end 432 proximate the end chip 410.

Control chip 402 includes control circuitry 412 similar to control circuitry 224 of fig. 2. Control chip 402 also includes switch 418 and detection circuitry 428. The switch 418 is operably coupled between the first test voltage potential 414 and the first end 434 of the TSV 430. A control input of the switch 418 is operably coupled to the control circuitry 412 to enable the control circuitry 412 to open and close the switch 418. The switch 418 is configured to selectively operatively couple and electrically isolate a first end 434 of the TSV 430 from a first test voltage potential 414 in response to control of the control circuitry 412. The detection circuitry 428 is configured to detect a voltage potential of the first end 434 of the TSV 430. The detection circuitry 428 is operatively coupled to the control circuitry 412 to provide the control circuitry 412 with a detected voltage potential of the first end 434 of the TSV 430.

The end chip 410 includes a switch 426 operably coupled between the second test voltage potential 416 and a second end 432 of the TSV 430. A control input of the switch 426 is operatively coupled to the control circuitry 412 to enable the control circuitry 412 to open and close the switch 426. The switch 418 is configured to selectively operatively couple and electrically isolate a second end 432 of the TSV 430 to a second test voltage potential 416 in response to control of the control circuitry 412.

The intermediate chips, i.e., chip 404, chip 406, and chip 408, include switches operably coupled between the second test voltage potential 416 and the TSV 430, respectively: switch 420, switch 422, and switch 424. Control inputs of switch 420, chip 406, and chip 408 are operably coupled to control circuitry 412 to enable control circuitry 412 to open and close switch 420, switch 422, and switch 424. The switches, i.e., the switch 420, the switch 422, and the switch 424, are configured to selectively operatively couple the TSV 430 at their respective locations along the TSV 430 to the second test voltage potential 416 and to electrically isolate the TSV 430 from the second test voltage potential in response to control of the control circuitry 412.

Spiral-type TSVs may be used to transmit signals (e.g., signals controlling switches 420, 422, 424, and 426) between control chip 402 and the other chips (chip 404, chip 406, chip 408, and end chip 410) of chip stack 400.

The control circuitry 412 is configured to perform a conductivity test on the second end 432. An example of a conductivity test is discussed below with reference to fig. 5. Although only one TSV 430 is shown in fig. 4, it should be understood that the chip stack 400 may contain multiple TSVs, such as the electronic device 100 of fig. 1 and 2, and that similar conductivity tests may be performed for each of the TSVs.

Fig. 5 is a flow chart illustrating a method 500 of performing a conductivity test according to some embodiments. Referring to fig. 4 and 5 together, in operation 502, the method 500 pre-charges the first end 434 of the TSV 430 to the first test voltage potential 414. In some embodiments, precharging the first end 434 of the TSV 430 to the first test voltage potential 414 includes activating the switch 418 operably coupled between the first end 434 of the TSV 430 and the first test voltage potential 414 until the first end 434 of the TSV 430 is charged to the first test voltage potential 414.

In operation 504, the method 500 discharges a second end 432 of the TSV 430, opposite the first end 434, to a second test voltage potential 416. In some embodiments, pre-discharging the second end 432 of the TSV 430 to the second test voltage potential 416 includes activating the switch 426 operably coupled between the second end 432 of the TSV 430 and the second test voltage potential 416 until the second end 432 of the TSV 430 discharges to the second test voltage potential 416.

In operation 506, the method 500 detects a voltage potential at the first end 434 of the TSV 430. In some embodiments, detecting the voltage potential at the first end 434 of the TSV 430 includes detecting the voltage potential using the detection circuitry 428. If the conductivity of the TSV 430 is good, discharging the second end 432 of the TSV 430 to the second test voltage potential 416 in operation 504 discharges the entire TSV 430 from the second end 432 to the first end 434 to the second test voltage potential 416. Thus, if the conductivity of the TSV 430 is good, the voltage potential detected at the first end 434 of the TSV 430 after the discharge of operation 504 will be at the second test voltage potential 416. On the other hand, if the conductivity of the TSV 430 is poor (e.g., an open circuit at some point such as a connection point between dies or the TSV 430 itself is not well formed), the voltage potential detected at the first end 434 of the TSV 430 after the discharge of operation 504 will not be at the second test voltage potential 416. For example, the voltage potential at the first end 434 may remain at the first test voltage potential 414 and end at some other voltage potential between the first test voltage potential 414 and the second test voltage potential 416.

In operation 508, the method 500 determines that the TSV 430 passes the conductivity test in response to detecting the second test voltage potential 416 at the first end 434 of the TSV 430. In operation 510, the method 500 determines that the TSV 430 failed the conductivity test in response to detecting the first test voltage potential 414 at the first end 434 of the TSV 430.

If it is determined that the TSV 430 fails the conductivity test, the method 500 may be repeated for each of the intermediate chips (chip 404, chip 406, and chip 408) of the chip stack 400, rather than the end chip 410, to identify the location of the failure in the TSV 430. For example, if the TSV 430 fails at the connection between the chip 404 and the chip 406, the TSV 430 will pass the conductivity test between the chip 404 and the control chip 402, but the TSV 430 will not pass the conductivity test between the control chip 402 and each of the chip 406, the chip 408, and the end chip 410.

Fig. 6 is a top view of a chip stack 600 according to some embodiments. The chip stack 600 may be similar to the electronic device 100 of fig. 1 and 2, and similar to the chip stack 400 of fig. 4. The chip stack 600 includes several sets of edge TSVs (

edge TSVs

604, 620, 628, 630, 632, 634, 638), VDD/VSS/VPP TSVs (VDD/VSS/

VPP TSVs

608, 610, 612, 614) and 640. The VDD/VSS/VPP TSVs include VDD/VSS/VPP edge TSVs (VDD/VSS/VPP edge TSV 606, VDD/VSS/VPP edge TSV 618, VDD/VSS/VPP edge TSV 624, VDD/VSS/VPP edge TSV 622). VDD/VSS TSV 640 includes VDD/VSS edge TSV 626 and VDD/VSS edge TSV 616.

Where various groups of TSVs are arranged at the side edge 602 of the chip stack 600, a limiting region or minimum acceptable TSV distance for placing the TSVs at the edge region (e.g., TSV region 106 of fig. 1) may be determined (e.g., using method 300 of fig. 3 and method 500 of fig. 5). In some embodiments, this minimum acceptable TSV distance may be determined globally (e.g., by selecting a largest minimum acceptable TSV distance of the minimum acceptable TSV distances for each of the edge TSV groups including edge TSVs, VDD/VSS edge TSVs, and VDD/VSS/VPP edge TSVs). However, the minimum acceptable TSV distance may be independently determined for each of the side edges 602 by placing a test TSV along each of the side edges 602 of the chip stack 600. Thus, in some embodiments, the minimum acceptable TSV distance may be determined independently for each of the side edges 602 of the chip stack 600. In some embodiments, a minimum acceptable TSV distance may be determined for each group of edge TSVs including edge TSVs, VDD/VSS edge TSVs, and VDD/VSS/VPP edge TSVs.

As a specific, non-limiting example, edge TSV 630 may include TSVs at each of 60270 μm, 110 μm, 150 μm, and 190 μm from the side edges, as shown in exploded view 642 of edge TSV 630. In this example, it can be determined that TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while TSVs at 70 μm do not. Thus, 110 μm may be selected as the minimum acceptable TSV distance of the edge TSV 630, the side edge of the chip stack 600 proximate to the edge TSV 630, or the entire chip stack 600.

As another specific, non-limiting example, the VDD/VSS edge TSV 626 may include two TSVs at each of 60270 μm, 110 μm, 150 μm and 190 μm from the side edge as shown in exploded view 644 of the VDD/VSS edge TSV 626. In this example, it may be determined that TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while at least one of the TSVs at 70 μm fails the conductivity test. Thus, 110 μm may be selected as the VDD/VSS edge TSV 626, the side edge of the chip stack 600 near the VDD/VSS edge TSV 626, or the minimum acceptable TSV distance of the entire chip stack 600.

In some embodiments, looking at the power source providing the power rail voltage, increasing the number of TSVs for the power rail voltage (e.g., VSS, VDD, VPP, etc.) may decrease the impedance of the chip stack 600. Using the embodiments disclosed herein, it may be determined how many additional TSVs may be placed near the side edge 602 for each set of VDD/VSS/VPP TSVs and VDD/VSS TSVs, thereby reducing impedance compared to previously known systems.

Fig. 7 is a top view of the chip stack 600 of fig. 6 demonstrating an example of signal management according to some embodiments. In the upper left quarter 706 of the chip stack 600, some signal management for outputting conductivity test results is shown from the perspective of the chip stack 600 in top view 6. For example, the chip stack 600 may include (e.g., in a control chip) a local multiplexer (e.g., local multiplexer 702, local multiplexer 704) configured to deliver results of the conductivity test from each of the TSVs in each of the groups of TSVs. In fig. 7, local multiplexer 702 multiplexes the results from

edge TSVs

604 and 620, and local multiplexer 704 multiplexes the results of VDD/VSS edge TSVs 616 and the output of local multiplexer 702. Thus, the local multiplexer 704 may selectively provide results from the

edge TSVs

620, 604, or VDD/VSS edge TSVs 616 in response to control applied (e.g., provided by control circuitry) over these edges. Although not shown, the chip stack 600 may include additional local multiplexers configured to multiplex the results of conductivity tests from other edge TSVs (e.g., edge TSVs 628, edge TSVs 630, VDD/VSS/VPP edge TSVs 624, VDD/VSS edge TSVs 626, VDD/VSS/VPP edge TSVs 622, edge TSVs 632, edge TSVs 634, edge TSVs 636, edge TSVs 638, VDD/VSS/VPP edge TSVs 618, VDD/VSS/VPP edge TSVs 606).

In some embodiments, the results of the conductivity tests may be output sequentially (e.g., continuously, one at a time on a single bus). In some embodiments, the results of the conductivity test may be output in parallel (e.g., simultaneously on enough of the test bus to carry all the results at once). In some embodiments, some intermediate multiplexing may occur. For example, the number of buses transmitting the results of the conductivity test may be less than the number of results of the conductivity test, and each of the buses transmits a series of successive different portions of the results.

Fig. 8 is a schematic diagram of a multiplexing circuit 800 according to some embodiments. Multiplexing circuit 800 may be used to multiplex TSV conductivity test results (e.g., TSV conductivity test results 816, TSV conductivity test results 818) from edge TSVs (e.g., edge TSVs, VDD/VSS/VPP edge TSVs of fig. 6 and 7) to global output 814. The multiplexing circuit 800 includes local multiplexers (e.g., local multiplexer 804, local multiplexer 806, local multiplexer 808, local multiplexer 810) configured to multiplex TSV conductivity test results 816 and TSV conductivity test results 818 to local outputs 812, where some of the TSV conductivity test results may be analog (e.g., to indicate a detected voltage potential on the TSV), and where some of the TSV conductivity test results may be digital (e.g., to indicate whether the corresponding TSV passed or failed the conductivity test). Multiplexing circuit 800 also includes a global multiplexer 802 configured to multiplex local output 812 into global output 814.

Each of the multiplexers (global multiplexer 802, local multiplexer 804, local multiplexer 806, local multiplexer 808, local multiplexer 810) is configured to selectively output one of the multiplexer inputs in response to a select signal SEL. Accordingly, depending on the value of the select signal SEL, either TSV conductivity test result 816 or TSV conductivity test result 818 may be provided at global output 814. Control circuitry (e.g., control circuitry 224, control circuitry 412) may be configured to provide a select signal SEL and receive a global output 814.

In some embodiments, local multiplexer 804, local multiplexer 806, local multiplexer 808, and/or local multiplexer 810 may be configured to receive signals unrelated to conductivity tests (e.g., signals related to other types of tests). Accordingly, multiplexing circuit 800 may be configured to selectively output to global output 814 any of TSV conductivity test results 816 or TSV conductivity test results 818 or other signals related to other tests.

Fig. 9 is a block diagram of an example of a logic die 900 of the electronic device 100 of fig. 1. The logic die 900 contains an AWORD/DWORD interface 904, a P1500 interface 906, and a direct access interface, DA interface 908. The logic die 900 also includes a command address data control circuit 902 operatively coupled to the AWORD/DWORD interface 904, a P1500 control circuit 916 operatively coupled to the P1500 interface 906 through a multiplexer 910, and a DA control circuit 914 operatively coupled to the DA interface 908. The command address data control circuit 902 is configured to control the operation of the AWORD/DWORD interface 904, the P1500 control circuit 916 is configured to control the operation of the P1500 interface 906, and the DA control circuit 914 is configured to control the operation of the DA interface 908. Each of the command address data control circuit 902, the P1500 control circuit 916, and the DA control circuit 914 are configured to communicate directly with a DRAM die (e.g., DRAM die 1006 of fig. 10). The P1500 control circuit 916 and the DA control circuit 914 are also configured to communicate indirectly with a DRAM die (e.g., the DRAM die 1006 of fig. 10) through the built-in self-test BIST 912. Further, the P1500 control circuit 916 and the DA control circuit 914 are configured to conduct hybrid communications with the DRAM die (e.g., the DRAM die 1006 of fig. 10), where the hybrid communications include both direct and indirect communications (through the BIST 912) with the DRAM die (e.g., the DRAM die 1006 of fig. 10).

The AWORD/DWORD interface 904 is an interface for providing address/command (AWORD) and data (DWORD) for normal operation of the high bandwidth memory (HBM 1002 of FIG. 10). By way of non-limiting example, the AWORD/DWORD interface 904 is configured to serve as an interface for conducting operational signals (e.g., commands, address signals, DQ input/output data signals, etc.). The AWORD/DWORD interface 904 contains an AWORD/DWORD port 918.

The P1500 interface 906 is an interface designated by JEDEC for test operations. P1500 interface 906 includes P1500 port 922. The number of P1500 ports 922 specified by JEDEC is fifteen P1500 ports 922. The P1500 test interface is a test interface between the embedded core and the system chip that can be used to test core interoperability. The functions and circuitry of the P1500 interface (e.g., P1500 control circuitry 916) between the various HBMs may be relatively similar, as JEDEC closely supervises the P1500 interface 906.

DA interface 908 is an interface for other operations (e.g., primarily test operations). For other test operations, the DA interface 908 (manufacturer/user specific) is not defined. Some of these test operations may include method 300 of fig. 3, method 500 of fig. 5, other test operations discussed herein, or any combination thereof. Thus, DA control circuitry 914 may implement control circuitry discussed herein (e.g., control circuitry 224, control circuitry 412).

The primary role of the DA interface 908 is to verify the functionality of the HBM (e.g., electronic device 100 of fig. 1) without using other interfaces (e.g., the AWORD/DWORD interface 904, the P1500 interface 906). DA interface 908 includes DA port 920. At least some of the DA ports 920 have a test pad 924. The number of DA ports 920 is sixty DA ports 920. The functionality and circuitry of DA interface 908 (e.g., DA control circuitry 914) may be relatively different from HBM to HBM, as the functionality and circuitry of DA interface 908 is not closely regulated as the functionality and circuitry of P1500 interface 906. For example, JEDEC defines the number and placement of microbumps (uBump) for DA port 920. However, port assignments and usage of DA interface 908 may vary from HBM to HBM.

Various arrows indicating the direction of the signals are shown in fig. 9. It should be noted that the address/command signals and corresponding test signals are driven in one direction from outside the logic die 900 to the DRAM die 1006 (fig. 10). On the other hand, the data signals and corresponding test signals are driven in both directions (i.e., to and from the DRAM die 1006 of FIG. 10).

FIG. 10 is a block diagram of a high bandwidth memory HBM + system 1000 according to some embodiments. HBM + system 1000 includes HBM 1002 and a processing unit 1004 (e.g., a central processing unit or CPU, a graphics processing unit or GPU, an accelerated processing unit or APU, etc.) operatively coupled to HBM 1002. HBM 1002 includes a dynamic random access memory die, a DRAM die 1006, and a logic die 1008. The logic die 1008 includes a processor 1010 and a near memory controller NMC 1012. The processing unit 1004 includes a far memory controller FMC 1014.

NMC 1012 and FMC 1014 are configured to function as a main memory controller master. FMC 1014 includes an off HBM memory controller and NMC 1012 includes an on HBM memory controller located on logic die 1008 of HBM 1002. The logic die 1008 may be a control chip (e.g., control chip 402 of fig. 4). By way of non-limiting example, the logic die 1008 may correspond to a bottom layer of the 3D stacked memory that is the HBM 1002, while the DRAM die 1006 may correspond to one of the upper layers of the HBM 1002. The logic die 1008 may control the DRAM die 1006 using the NMC 1012, which may be directed by the processor 1010 to control the DRAM die 1006. It should be noted that one or both of the NMC 1012 and FMC 1014 may be represented by a general purpose memory controller. The logic die 1008 may contain the logic die 900 of fig. 9.

Fig. 11 is a block diagram of a computing system 1100 according to some embodiments. The computing system 1100 includes one or more processors 1104 operably coupled to one or more memory devices 1102, one or more non-volatile data storage devices 1110, one or more input devices 1106, and one or more output devices 1108. In some embodiments, computing system 1100 includes a Personal Computer (PC), such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (e.g., a smartphone, a Personal Digital Assistant (PDA), etc.), a web server, or other computer device.

In some embodiments, the one or more processors 1104 may include a Central Processing Unit (CPU) or other processor configured to control the computing system 1100. In some embodiments, the one or more memory devices 1102 include Random Access Memory (RAM), such as volatile data storage (e.g., dynamic RAM (dram), static RAM (sram), etc.). In some embodiments, the one or more non-volatile data storage devices 1110 include hard disk drives, solid state drives, flash memory, erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, the one or more input devices 1106 include a keyboard 1112, a pointing device 1114 (e.g., a mouse, a trackpad, etc.), a microphone 1116, a keypad 1118, a scanner 1120, a camera 1122, other input devices, or any combination thereof. In some embodiments, the one or more output devices 1108 include an electronic display 1124, speakers 1126, a printer 1128, other output devices, or any combination thereof.

In some embodiments, the one or more memory devices 1102 include an HBM system such as the HBM + system 1000 of fig. 10. In some embodiments, the one or more memory devices 1102 include a chip stack (e.g., chip stack 102 of fig. 1, chip stack 400 of fig. 4, chip stack 600 of fig. 6) that includes the logic die 900 of fig. 9.

As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of the module or component and/or software objects or to execute software routines that may be stored on or executed by general purpose hardware of a computing system. In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on the computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and/or executed by general purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

As used in this disclosure, the term "combination" involving a plurality of elements may encompass a combination of all the elements or any of a variety of different subcombinations of some of the elements. For example, the phrase "A, B, C, D or a combination thereof" may refer to either A, B, C or D; A. b, C and D; and A, B, C or D, such as A, B and C; A. b and D; A. c and D; B. c and D; a and B; a and C; a and D; b and C; b and D; or C and D.

Terms used in this disclosure and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be understood as "including but not limited to," the term "having" should be understood as "having at least," the term "includes" should be understood as "includes but is not limited to," etc.).

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, means at least two recitations, or two or more recitations). Further, in those instances where a convention similar to "at least one of A, B and C, etc." or one or more of "A, B and C, etc." is used, such a construction is generally intended to encompass a alone, B alone, C, A and B, A and C, B and C or A, B and C, among others.

Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase "a or B" should be understood to include the possibility of "a" or "B" or "a and B".

While the present disclosure has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that it is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described embodiments may be made without departing from the scope of the invention as hereinafter claimed and its legal equivalents. Additionally, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the invention as contemplated by the inventors.

Claims

1. An electronic device, comprising:

a chip stack including one or more side edges at a perimeter of the chip stack, a through-silicon via region (TSV region) of the chip stack being located within a predetermined distance from the one or more side edges;

a first TSV located within the TSV region of the chip stack at a first distance from the one or more side edges; and

a second TSV located within the TSV region of the chip stack at a second distance from the one or more side edges, the second distance being shorter than the first distance.

2. The electronic device of claim 1, further comprising control circuitry on or in a control chip in the chip stack, the control circuitry configured to:

performing a conductivity test on the first TSV and the second TSV; and is

Identifying a minimum acceptable TSV distance from the one or more side edges as the first distance from the one or more side edges in response to determining: the first TSV passes the conductivity test, the second TSV fails the conductivity test and no other TSV farther from the one or more side edges than the first TSV does not pass the conductivity test.

3. The electronic device of claim 2, wherein the control chip includes a logic die of a memory device.

4. The electronic device of claim 3, wherein the control circuitry includes Direct Access (DA) control circuitry of the logic die.

5. The electronic device of claim 2, wherein:

the control chip is positioned at a first end of the first TSV;

the control chip includes a first electrically controllable switch configured to selectively operatively couple the first TSV to a first test voltage potential proximate the first end of the first TSV; and is

An end chip in the chip stack is positioned at a second end of the first TSV opposite the first end, the end chip including a second electrically controllable switch configured to selectively operatively couple the first TSV to a second test voltage potential proximate the second end, the second test voltage potential being different than the first test voltage potential.

6. The electronic device of claim 5, wherein the control circuitry is configured to:

controlling the first electrically controllable switch to operably couple the first TSV to the first test voltage potential until the first end of the first TSV is charged to the first test voltage potential;

controlling the second electrically controllable switch of the end chip to operably couple the first TSV to the second test voltage potential until the second end of the first TSV discharges to the second test voltage potential;

determining that the first TSV passes the conductivity test in response to determining that the first end of the first TSV is located at the second test voltage potential; and is

Determining that the first TSV fails the conductivity test in response to determining that the first end of the first TSV is located at the first test voltage potential.

7. The electronic device of claim 2, wherein:

the control chip is positioned at a first end of the second TSV;

the control chip includes a first electrically controllable switch configured to selectively operatively couple the second TSV to a first test voltage potential proximate the first end of the second TSV; and is

An end chip in the chip stack is positioned at a second end of the second TSV opposite the first end, the end chip including a second electrically controllable switch configured to selectively operatively couple the second TSV to a second test voltage potential proximate the second end, the second test voltage potential being different than the first test voltage potential.

8. The electronic device of claim 7, wherein the control circuitry is configured to:

controlling the first electrically controllable switch to operably couple the second TSV to the first test voltage potential until the first end of the second TSV is charged to the first test voltage potential;

controlling the second electrically controllable switch of the end chip to operably couple the second TSV to the second test voltage potential until the second end of the second TSV discharges to the second test voltage potential;

determining that the second TSV passes the conductivity test in response to determining that the first end of the second TSV is located at the second test voltage potential; and is

Determining that the second TSV fails the conductivity test in response to determining that the first end of the second TSV is located at the first test voltage potential.

9. The electronic device of claim 2, further comprising a third TSV located within the TSV region of the chip stack at a third distance from the one or more side edges, the third distance being shorter than the second distance, wherein the control circuitry is configured to:

performing the conductivity test on the third TSV; and is

Identifying the minimum acceptable TSV distance from the one or more side edges as the second distance from the one or more side edges in response to determining: the first and second TSVs pass the conductivity test, the third TSV fails the conductivity test and no other TSVs further from the one or more side edges than the first TSV do not pass the conductivity test.

10. The electronic device of claim 2, wherein:

the first and second TSVs are positioned in a first one of the TSV regions;

a first plurality of TSVs of the first region includes the first TSV and the second TSV; and is

The control chip includes a first local multiplexer configured to selectively provide one of a first plurality of TSV conductivity test results, each of the first plurality of TSV conductivity test results corresponding to a different TSV of the first plurality of TSVs.

11. The electronic device of claim 10, further comprising a second plurality of TSVs positioned in a second one of the TSV regions, wherein:

the control chip includes a second local multiplexer configured to selectively provide one of a second plurality of TSV conductivity test results, each TSV conductivity test result of the second plurality of TSV conductivity test results corresponding to a different TSV of the second plurality of TSVs;

the plurality of local multiplexers of the control chip include the first local multiplexer and the second local multiplexer; and is

The control chip includes a global multiplexer operably coupled to each of the plurality of local multiplexers, an output of the global multiplexer configured to selectively provide one of a plurality of outputs of the plurality of local multiplexers.

12. A method of determining a minimum acceptable through silicon via distance (minimum acceptable TSV distance) from one or more side edges of a chip stack, the method comprising:

performing a conductivity test on a first TSV positioned a first distance from the one or more side edges of the chip stack;

performing the conductivity test on a second TSV positioned a second distance from the one or more side edges, the second distance being shorter than the first distance; and

identifying the minimum acceptable TSV distance from the one or more side edges as the first distance in response to determining: the first TSV passes the conductivity test, the second TSV fails the conductivity test and no other TSV farther from the one or more side edges than the first TSV does not pass the conductivity test.

13. The method of claim 12, wherein performing the conductivity test on TSVs comprises:

precharging a first end of the TSV to a first test voltage potential;

discharging a second end of the TSV opposite the first end to a second test voltage potential;

detecting a voltage potential at the first end of the TSV;

determining that the TSV passes the conductivity test in response to detecting the second test voltage potential at the first end of the TSV; and

determining that the TSV fails the conductivity test in response to detecting the first test voltage potential at the first end of the TSV.

14. The method of claim 13, wherein precharging the first end of the TSV to the first test voltage potential comprises activating a switch operably coupled between the first end of the TSV and the first test voltage potential until the first end of the TSV is charged to the first test voltage potential.

15. The method of claim 13, wherein discharging the second end of the TSV to the second test voltage potential comprises activating a switch operably coupled between the second end of the TSV and the second test voltage potential until the second end of the TSV is discharged to the second test voltage potential.

16. A memory device, comprising:

a chip stack comprising a logic die and a plurality of core dies stacked on the logic die;

a plurality of through-silicon vias (TSVs) located at different distances from one or more side edges of the chip stack, an ordered sequence being associated with the plurality of TSVs from TSVs furthest from the one or more side edges to TSVs nearest the one or more side edges; and

control circuitry on or in the logic die, the control circuitry configured to:

performing a conductivity test on each of the plurality of TSVs;

identifying a TSV of the plurality of TSVs that is the last consecutive TSV in the ordered sequence that passed the conductivity test if none of the preceding TSVs in the ordered sequence failed the conductivity test; and is

Determining that the minimum acceptable TSV distance from the one or more side edges is the same as the distance from the identified TSV to the one or more side edges.

17. The memory device of claim 16, wherein the control circuitry comprises direct access control circuitry (DA control circuitry).

18. The memory device of claim 16, wherein:

the plurality of TSVs are positioned at a first side edge of the one or more side edges;

the memory device further includes an additional plurality of TSVs at a second side edge of the one or more side edges, the second side edge being different from the first side edge; and is

The control circuitry is configured to determine another minimum acceptable TSV distance corresponding to the other plurality of TSVs independent of determining the minimum acceptable TSV distance corresponding to the plurality of TSVs.

19. A computing device comprising the memory device of claim 16.

20. The computing device of claim 19, further comprising:

one or more processors operably coupled to the memory device;

one or more non-volatile data storage devices operably coupled to the one or more processors;

one or more input devices operably coupled to the one or more processors; and

one or more output devices operably coupled to the one or more processors.