CN112532553A - Transponder message demodulation circuit for 2FSK modulation - Google Patents
Transponder message demodulation circuit for 2FSK modulation Download PDFInfo
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- CN112532553A CN112532553A CN201910878005.7A CN201910878005A CN112532553A CN 112532553 A CN112532553 A CN 112532553A CN 201910878005 A CN201910878005 A CN 201910878005A CN 112532553 A CN112532553 A CN 112532553A
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- 238000001914 filtration Methods 0.000 claims abstract description 4
- 239000003990 capacitor Substances 0.000 claims description 39
- 230000000903 blocking effect Effects 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/106—M-ary FSK
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
- H04L27/148—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using filters, including PLL-type filters
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Abstract
The invention relates to a transponder message demodulation circuit for 2FSK modulation, comprising: a selective filtering circuit for attenuating a first frequency waveform, wherein the first frequency is a frequency representing 0; the first comparison amplifying circuit is connected with the output end of the selective filter circuit and used for cutting the bottom of the output signal of the selective filter circuit to remove the positive half cycle or negative half cycle signal and converting the signal into a square wave signal; the integrating circuit is connected with the output end of the first comparison amplifying circuit and is used for integrating the signal; and the second comparison amplifying circuit is connected with the output end of the integrating circuit and is used for converting the integrated signal into a square wave signal. Compared with the prior art, the invention is realized by pure hardware, and designers do not need to skillfully use special tools, HDL (high density hardware description) language, programming language, algorithm and the like.
Description
Technical Field
The invention relates to a demodulation circuit, in particular to a transponder message demodulation circuit for 2FSK modulation.
Background
The message information of the railway inquiry transponder is modulated by 2FSK and then transmitted to the outside, and then received, demodulated and decoded by the vehicle-mounted BTM equipment. Currently, there are many methods for demodulating 2FSK signals, such as envelope detection, coherent demodulation, frequency discrimination, and zero-crossing detection, and they are implemented by hardware and software. The applied circuit is complex, the used devices are expensive, such as chips of FPGA, DSP and the like, and the requirement on the professional skill of a designer is high, and the entry difficulty is high if special tools, HDL (high-density hardware description) languages, programming languages, algorithms and the like are used skillfully. Furthermore, the real-time performance of decoding the 2FSK signal by this method is not necessarily ideal.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned drawbacks of the prior art by providing a transponder message demodulation circuit for 2FSK modulation.
The purpose of the invention can be realized by the following technical scheme:
a transponder message demodulation circuit for 2FSK modulation, comprising:
a selective filtering circuit for attenuating a first frequency waveform, wherein the first frequency is a frequency representing 0;
the first comparison amplifying circuit is connected with the output end of the selective filter circuit and used for cutting the bottom of the output signal of the selective filter circuit to remove the positive half cycle or negative half cycle signal and converting the signal into a square wave signal;
the integrating circuit is connected with the output end of the first comparison amplifying circuit and is used for integrating the signal;
and the second comparison amplifying circuit is connected with the output end of the integrating circuit and is used for converting the integrated signal into a square wave signal.
The first comparison amplifying circuit comprises a first comparison amplifier, and the second comparison amplifying circuit comprises a second comparison amplifier.
The output end of the selective filter circuit is connected to the non-inverting input end of the first comparison amplifier, and the output end of the integrating circuit is connected to the non-inverting input end of the second comparison amplifier.
The second comparison amplifying circuit further comprises a feedback resistor and a high-frequency filter capacitor, and the feedback resistor and the high-frequency filter capacitor are connected in parallel and then are jointly bridged between the non-inverting input end and the output end of the second comparison amplifier.
The selective filter circuit comprises a first matching resistor, a band-pass filter and a blocking filter, wherein the band-pass filter and the blocking filter are sequentially connected, and the output end of the blocking filter is connected to the first comparison amplifying circuit and is grounded through the first matching resistor.
The band-pass filter comprises a first inductor and a first capacitor which are arranged in series.
The first capacitor is connected with a debugging capacitor in parallel.
The stop-pass filter comprises a second inductor and a third capacitor which are connected in parallel with each other.
And the third capacitor is connected with a debugging capacitor in parallel.
The integrating circuit comprises a second resistor, a fifth capacitor and a second matching resistor, one end of the second resistor is connected to the output end of the first comparing and amplifying circuit, the other end of the second resistor is connected to the input end of the fifth capacitor, the output end of the fifth capacitor is grounded, the input end of the fifth capacitor is further connected to the input end of the second comparing and amplifying circuit, and the input end of the fifth capacitor is grounded through the second matching resistor.
Compared with the prior art, the invention has the following beneficial effects:
1) the method is realized by pure hardware without the need of skillful application of special tools, HDL (hardware description language), programming language, algorithm and the like by designers.
2) The circuit is a low-cost scheme, and has stable performance, correct decoding and good real-time performance.
3) The circuit is simple and clear, mature and classical, the practicality is strong, and is applicable to other similar circuit occasions.
4) The circuit adopts general devices, supplies materials stably, the facilitate promotion.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a circuit diagram for implementing the embodiment of the present invention;
FIG. 3 is a diagram illustrating a waveform of an original signal;
FIG. 4 is a schematic diagram of a signal waveform output by the selective filter circuit;
FIG. 5(a) is a schematic diagram of a signal waveform after bottom-cutting;
FIG. 5(b) is a schematic diagram of the waveform of the signal output by the first comparing and amplifying circuit;
FIG. 6 is a schematic diagram of a waveform of a signal output from the integrating circuit;
FIG. 7 is a schematic diagram of a waveform of a signal output by the second comparing and amplifying circuit;
wherein: 1. the circuit comprises a selective filter circuit 2, a first comparison amplifying circuit 3, an integrating circuit 4 and a second comparison amplifying circuit.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present embodiment is implemented on the premise of the technical solution of the present invention, and a detailed implementation manner and a specific operation process are given, but the scope of the present invention is not limited to the following embodiments.
A transponder message demodulation circuit for 2FSK modulation, as shown in fig. 1, comprising:
a selective filter circuit 1 for attenuating a first frequency waveform, wherein the first frequency is a frequency representing 0;
the first comparison amplifying circuit 2 is connected with the output end of the selective filter circuit 1 and is used for cutting the bottom of the output signal of the selective filter circuit 1 to remove a positive half cycle signal or a negative half cycle signal and converting the signal into a square wave signal;
the integrating circuit 3 is connected with the output end of the first comparing and amplifying circuit 2 and is used for integrating signals;
and the second comparison amplifying circuit 4 is connected with the output end of the integrating circuit 3 and is used for converting the integrated signal into a square wave signal.
As shown in fig. 2, the first comparison amplification circuit 2 includes a first comparison amplifier, and the second comparison amplification circuit 4 includes a second comparison amplifier. In this embodiment, the output terminal of the selective filter circuit 1 is connected to the non-inverting input terminal of the first comparison amplifier, and the output terminal of the integrating circuit 3 is connected to the inverting input terminal of the second comparison amplifier.
The first comparison amplifier adopts MAX942, wherein a pin 3 is a non-inverting input end, a pin 2 is an inverting input end, 1 reference voltage Vref1 with adjustable amplitude is connected, a pin 4 is grounded, a pin 8 is connected with a power supply +5V, and a pin 1 is an output end. The second comparison amplifier adopts MAX942, wherein a pin 5 is a non-inverting input end, a pin 6 is an inverting input end and is connected with 1 reference voltage Vref2 with adjustable amplitude, and a pin 7 is an output end;
the second comparison amplifying circuit 4 further comprises a feedback resistor R4 and a high-frequency filter capacitor C6, wherein the feedback resistor R4 and the high-frequency filter capacitor C6 are connected in parallel and then are connected across the non-inverting input end and the output end of the second comparison amplifier, R4 is 100k Ω, and C6 is 33 pF. The output of the second comparator amplifier is also connected to ground via a resistor R5.
In another embodiment of the present application, the output terminal of the selective filter circuit 1 is connected to the inverting input terminal of the first comparison amplifier, and the output terminal of the integrating circuit 3 is connected to the inverting input terminal of the second comparison amplifier.
The selective filter circuit 1 includes a first matching resistor R1, and a band-pass filter and a stop-pass filter connected in sequence, and an output end of the stop-pass filter is connected to the first comparison amplifying circuit 2 and grounded through a first matching resistor R1. The band-pass filter comprises a first inductor L1 and a first capacitor C1 which are arranged in series, and the first capacitor C1 is connected with a debugging capacitor C2 in parallel. The blocking filter comprises a second inductor L2 and a third capacitor C3 which are connected in parallel, and the third capacitor C3 is connected with a debugging capacitor C4 in parallel.
The color wheel inductor with L1 of 22uH, the ceramic chip capacitor with C1 of 47p, form a band-pass filter, wherein the resonance frequency of C2 is adjusted to 3.952MHz (4.234MHz-282 kHz). L2 is a color wheel inductance of 3.3uH, C3 is a ceramic chip capacitance of 330p, the resonance frequency of C4 is adjusted to 4.516MHz (4.234MHz +282kHz), and R1 resistance is 510 omega.
The integrating circuit 3 comprises a second resistor R2, a fifth capacitor C5 and a second matching resistor R3, one end of the second resistor R2 is connected to the output end of the first comparing and amplifying circuit 2, the other end of the second resistor R2 is connected to the input end of the fifth capacitor C5, the output end of the fifth capacitor C5 is grounded, and the input end of the fifth capacitor C2 is also connected to the input end of the second comparing and amplifying circuit 4 and grounded through the second matching resistor R3. R2 is a chip resistor with the resistance of 51 omega, C5 is a ceramic chip capacitor with the capacity of 680p, and R3 is 510 omega.
The working principle of the application is as follows:
as shown in fig. 3, the message signal (2FSK) Vi uploaded by the transponder includes 2 phase-continuous sinusoidal signals with different frequencies, where the frequency of the low-frequency signal is 3.952MHz, the frequency of the high-frequency signal is 4.516MHz, 7 periods of the low-frequency signal (3.952MHz) are 1 bit 1, and 8 periods of the high-frequency signal (4.516MHz) are 1 bit 0. Taking a 2FSK modulation signal with Vi as a number 01 as an example, the Vi signal firstly passes through a L1 and C1(3.952MHz) band-pass network, and then a low-frequency signal 3.952MHz passes through the signal, so that the amplitude is unchanged, while a high-frequency signal 4.516MHz is attenuated, and the amplitude is reduced; after passing through the L2 and C3(4.516MHz) stop band network, the high-frequency signal 4.516MHz is further attenuated, so that the amplitude is greatly reduced, but the low-frequency signal 3.952MHz is slightly influenced, thereby forming the waveform of fig. 4, and the signal amplitude difference of 2 frequencies is obvious. In the circuit, because the signal is influenced by the low direct current potential at the input end of the comparison amplification circuit 1, the negative half cycle of the signal is cut off, so the actual waveform should be as shown in Va in fig. 5(a), and only has a positive half cycle; the Va signal is connected to the non-inverting input terminal of the comparison amplification circuit 1 and is compared and amplified with the reference voltage Vref1 at the inverting input terminal to output the Vb signal in fig. 5 (b); the Vb signal is a square wave signal of 3.952MHz, and passes through a dc voltage waveform formed on C5 after integration (charging) of the integrating circuit, such as Vc in fig. 6; the Vc signal is connected to the non-inverting input terminal of the comparing and amplifying circuit 2, and the reference voltage Vref2 at the inverting input terminal is compared and amplified to output the Vout signal in fig. 7, and the Vout signal is the demodulated signal 01 of Vi. Therefore, if Vi is a modulation signal (2FSK) of message information, a binary message information code can be obtained after the processing of the demodulation circuit.
The demodulation circuit can obtain excellent performance by using universal cheap devices, and the practical use proves that the demodulation circuit has stable performance, correct decoding and good real-time performance.
Claims (10)
1. A transponder message demodulation circuit for 2FSK modulation, comprising:
a selective filtering circuit for attenuating a first frequency waveform, wherein the first frequency is a frequency representing 0;
the first comparison amplifying circuit is connected with the output end of the selective filter circuit and used for cutting the bottom of the output signal of the selective filter circuit to remove the positive half cycle or negative half cycle signal and converting the signal into a square wave signal;
the integrating circuit is connected with the output end of the first comparison amplifying circuit and is used for integrating the signal;
and the second comparison amplifying circuit is connected with the output end of the integrating circuit and is used for converting the integrated signal into a square wave signal.
2. The transponder message demodulation circuit of claim 1, wherein the first comparison amplification circuit comprises a first comparison amplifier and the second comparison amplification circuit comprises a second comparison amplifier.
3. A transponder message demodulation circuit for 2FSK modulation according to claim 2, wherein the output of said selective filter circuit is connected to the non-inverting input of a first comparison amplifier and the output of said integrator circuit is connected to the non-inverting input of a second comparison amplifier.
4. The transponder message demodulation circuit for 2FSK modulation according to claim 3, wherein said second comparison amplifying circuit further comprises a feedback resistor and a high frequency filter capacitor, said feedback resistor and said high frequency filter capacitor being connected in parallel and connected in common across the non-inverting input terminal and the output terminal of the second comparison amplifier.
5. The transponder message demodulation circuit of claim 1, wherein the selective filtering circuit comprises a first matching resistor, and a band-pass filter and a blocking filter connected in sequence, and an output terminal of the blocking filter is connected to the first comparing and amplifying circuit and is grounded through the first matching resistor.
6. The transponder message demodulation circuit of claim 5 wherein said bandpass filter comprises a first inductor and a first capacitor arranged in series.
7. The transponder message demodulation circuit of claim 6 wherein the first capacitor is connected in parallel with a tuning capacitor.
8. The transponder message demodulation circuit of claim 5, wherein the blocking filter comprises a second inductor and a third capacitor connected in parallel with each other.
9. The transponder message demodulation circuit of claim 8 wherein the third capacitor is connected in parallel with a tuning capacitor.
10. The transponder message demodulation circuit of claim 1, wherein the integrating circuit comprises a second resistor, a fifth capacitor and a second matching resistor, wherein one end of the second resistor is connected to the output terminal of the first comparing and amplifying circuit, the other end of the second resistor is connected to the input terminal of the fifth capacitor, the output terminal of the fifth capacitor is grounded, and the input terminal of the fifth capacitor is further connected to the input terminal of the second comparing and amplifying circuit and grounded through the second matching resistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910878005.7A CN112532553A (en) | 2019-09-17 | 2019-09-17 | Transponder message demodulation circuit for 2FSK modulation |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910878005.7A CN112532553A (en) | 2019-09-17 | 2019-09-17 | Transponder message demodulation circuit for 2FSK modulation |
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| CN112532553A true CN112532553A (en) | 2021-03-19 |
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Citations (5)
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|---|---|---|---|---|
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| CN203014804U (en) * | 2012-12-21 | 2013-06-19 | 桂林电子科技大学 | Demodulator of modulation tracking loop |
| CN103188188A (en) * | 2011-12-28 | 2013-07-03 | 国民技术股份有限公司 | Signal system for demodulation and filtering and demodulation and filtering method |
| CN105391497A (en) * | 2015-10-30 | 2016-03-09 | 哈尔滨工程大学 | 433M digital frequency modulation receiver |
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2019
- 2019-09-17 CN CN201910878005.7A patent/CN112532553A/en active Pending
Patent Citations (5)
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| CN101917372A (en) * | 2010-08-20 | 2010-12-15 | 北京全路通信信号研究设计院 | Pre-demodulating, frequency discriminating and demodulating method, pre-demodulator, frequency discriminator and demodulator |
| CN103124247A (en) * | 2011-11-21 | 2013-05-29 | 国民技术股份有限公司 | Signal demodulating system, receiver and demodulation filtering method |
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| CN203014804U (en) * | 2012-12-21 | 2013-06-19 | 桂林电子科技大学 | Demodulator of modulation tracking loop |
| CN105391497A (en) * | 2015-10-30 | 2016-03-09 | 哈尔滨工程大学 | 433M digital frequency modulation receiver |
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