CN112532188A - Low-noise high-linearity capacitive coupling amplifier for bioelectric signal measuring circuit - Google Patents

Low-noise high-linearity capacitive coupling amplifier for bioelectric signal measuring circuit Download PDF

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CN112532188A
CN112532188A CN202011393972.3A CN202011393972A CN112532188A CN 112532188 A CN112532188 A CN 112532188A CN 202011393972 A CN202011393972 A CN 202011393972A CN 112532188 A CN112532188 A CN 112532188A
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switch
frequency
low
capacitor
module
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赵梦恋
邬明洲
杨小林
赵依博
周奕兆
吴晓波
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers

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Abstract

The invention discloses a low-noise high-linearity capacitive coupling amplifier for a bioelectricity signal measuring circuit, which reduces the thermal noise of the amplifier to half of the original thermal noise by adopting an amplifier topology of current multiplexing and greatly reduces the flicker noise of a low-frequency area by a high-frequency chopping technology. For huge burrs generated in the switching process of the chopping switch, the double dead zone switching technology is adopted for eliminating, so that the harmonic component of the output signal of the measuring circuit is greatly reduced, and the linearity of the system is improved. In addition, the differential operational amplifier adopts the common-mode feedback of the switched capacitor, thereby reducing the power consumption, avoiding the possible common-mode oscillation and further reducing the influence of the switching on the system by reasonably arranging the switching time sequence.

Description

Low-noise high-linearity capacitive coupling amplifier for bioelectric signal measuring circuit
Technical Field
The invention belongs to the technical field of biomedical electronics, and particularly relates to a low-noise high-linearity capacitive coupling amplifier for a bioelectricity signal measuring circuit.
Background
The bioelectric signal is used as a carrier capable of transmitting physiological conditions of various organs and tissues in a human body, and is widely researched and applied in the medical field. The bioelectric signals commonly used in clinic mainly comprise electrocardiosignals, electroencephalogram signals, electromyogram signals, electrooculogram signals and the like, wherein the electrocardiosignals can be used for diagnosing heart diseases and monitoring the working state of the heart, the electroencephalogram signals can be used for predicting and diagnosing epilepsy, sleep disorder and other brain diseases, and the electromyogram signals and the electrooculogram signals can be used for detecting pathological changes of muscles and eyes. The use of the bioelectric signal further enriches the diagnosis basis of modern medicine, improves the diagnosis accuracy, and has great significance for promoting the development of medical research.
The amplitude of the bioelectrical signal is very small, the frequency is low, and meanwhile, the noise interference is large, so that the measurement difficulty is very high. Taking EEG signals as an example, the distribution frequency of the EEG signals is 0.5-100 Hz, the amplitude of the signals is 1-100 muV, and electrode imbalance of up to 300mV exists in the measurement process, so that an analog-to-digital converter of at least 18 bits is needed for detecting the EEG signals. In view of the above-mentioned features, a low-speed high-precision Σ Δ analog-to-digital converter is often used in a bioelectrical signal measurement circuit, and the structure of the Σ Δ analog-to-digital converter is, as shown in fig. 1, constituted by a differentiator, an integrator, a quantizer, a feedback DAC, and a down-sampling filter, in which the differentiator functions to differentiate an input signal from a feedback signal. The sigma delta analog-to-digital converter theoretically can compress quantization noise in a signal bandwidth to be very low through a noise shaping and oversampling principle, so that very high measurement accuracy is achieved, but due to the existence of thermal noise and flicker noise in an actual circuit, the measurement accuracy of the sigma delta analog-to-digital converter with a high-order and high oversampling rate is still limited by the limitation of a circuit noise floor, and therefore how to reduce the thermal noise and the flicker noise in the circuit is a key in the bioelectrical signal measurement circuit.
In the circuit implementation process, the function of the differentiator is usually performed by an instrumentation amplifier, and since the amplifier is an interface for connecting the measuring electrode and the analog circuit, its noise performance determines the measurement accuracy of the whole system. In consideration of the low-frequency characteristics of the bioelectricity signals, the common technology is that a high-frequency chopping technology is adopted to carry flicker noise of an amplifier to high frequency, and finally the flicker noise is filtered by a down-sampling filter, but in the switching process of chopping, huge burrs can be generated at the input end of an operational amplifier of a differentiator, the frequency of the envelope curve of the burrs is the same as the frequency of an input signal, so the burrs can appear in a frequency spectrum analysis diagram of a system in the form of harmonic components of the signal after being quantized by a quantizer, the linearity of the system is seriously influenced, and the signal-to-noise-distortion ratio of the system is greatly reduced.
The document [ h.chandrakumar and d.markovic, "a 15.2-ENOB 5-kHz BW 4.5- μ W branched CT Δ \ sigma-ADC for implementation-free near recording front ends," IEEE Journal of Solid-State Circuits, vol.53, (12), pp.3470-3483,2018 ] proposes a dead-zone switching technique for chopper-induced glitches, in which a pair of switches is inserted at the input end of the differentiator operational amplifier, and the dead-zone switch is turned off at the switching instant of the chopper switch, thereby avoiding the generated glitches from being amplified to the output end of the operational amplifier by the operational amplifier. However, the dead-zone switch proposed in this document cannot avoid the coupling of the glitch signal to the output end through the operational amplifier feedback capacitor, when the parasitic capacitance of the operational amplifier output end is large, the glitch introduced into the system through this path will have a small influence on the linearity of the system, and in addition, the technique of this document does not perform an additional design on the operational amplifier common-mode feedback, and the power consumption generated by the common-mode feedback circuit can be further optimized.
Disclosure of Invention
In view of the above, the present invention provides a low-noise high-linearity capacitive coupling amplifier for a bioelectrical signal measuring circuit, which adopts a high-frequency chopping technique to greatly reduce the flicker noise in a low-frequency region; for huge burrs generated in the switching process of the chopping switch, the invention adopts a double dead-zone switching technology to eliminate, and simultaneously combines a current multiplexing technology and a switched capacitor common-mode feedback technology to reduce the thermal noise of the system and reduce the power consumption of the system.
A low-noise high-linearity capacitive coupling amplifier for a bioelectricity signal measuring circuit comprises a high-frequency chopping module, a direct-current bias module, a double dead zone switch module and a current multiplexing operational amplifier module; wherein:
the high-frequency chopping module consists of two high-frequency choppers CH1 and CH2, and CH1 is used for chopping the low-frequency bioelectric signals measured by the measuring circuit in a differential form into high-frequency bioelectric signals; the CH2 is used for chopping the high-frequency bioelectricity signals amplified by the current multiplexing operational amplifier module into amplified low-frequency bioelectricity signals, and chopping low-frequency noise in the amplified high-frequency bioelectricity signals into high-frequency noise;
the direct current bias module is used for providing direct current bias voltage for an input signal of the current multiplexing operational amplifier;
the double dead zone switch module is used for eliminating burrs in high-frequency bioelectricity signals obtained by chopping CH 1;
the current multiplexing operational amplifier module is used for amplifying the high-frequency bioelectricity signals after the burrs are removed.
Furthermore, a positive phase input end of the high-frequency chopper CH1 is connected with the measuring circuit to output a positive phase low-frequency bioelectric signal, a negative phase input end of the high-frequency chopper CH1 is connected with the measuring circuit to output a negative phase low-frequency bioelectric signal, and a positive phase output end and a negative phase output end of the high-frequency chopper CH1 are respectively connected with the input capacitor Cin1And Cin2Connected to the dual dead band switch module; the positive phase input end of the high-frequency chopper CH2 is connected with the positive phase output end of the current multiplexing operational amplifier module, the negative phase input end of the high-frequency chopper CH2 is connected with the negative phase output end of the current multiplexing operational amplifier module, and the positive phase output end and the negative phase output end output the low-frequency bioelectricity signals amplified in a differential mode.
Further, the high-frequency choppers CH1 and CH2 are identical in structure and are composed of four transmission gates T1 to T4, an input terminal of the transmission gate T1 is connected to an input terminal of the transmission gate T4 as a non-inverting input terminal of the high-frequency chopper, an output terminal of the transmission gate T1 and an output terminal of the transmission gate T3 as a non-inverting output terminal of the high-frequency chopper, an input terminal of the transmission gate T2 is connected to an input terminal of the transmission gate T3 as an inverting input terminal of the high-frequency chopper, an output terminal of the transmission gate T2 and an output terminal of the transmission gate T4 as an inverting output terminal of the high-frequency chopper, gates of NMOS transistors in the transmission gates T1 and T2 and gates of PMOS transistors in the transmission gates T3 and T4 are connected to the clock signal Φ 1, gates of PMOS transistors in the transmission gates T1 and T2 and gates of NMOS transistors in the transmission gates T3 and T4 are connected to the clock signal Φ 2, and the clock signals Φ 1 and Φ 2 are.
Further, the direct current bias module comprises two resistors R with the same resistance value1And R2And two switches SW1And SW2Resistance R1One terminal of and an input capacitor Cin1One end of which is connected as a DAC feedback point X, an input capacitor Cin1The other end of the resistor R is connected with the non-inverting output end of the high-frequency chopper CH12One terminal of and an input capacitor Cin2One end of which is connected as a DAC feedback point Y, an input capacitor Cin2The other end of the resistor R is connected with the inverting output end of the high-frequency chopper CH11And the other end of (1) and a switch SW1Is connected to one end of a resistor R2And the other end of (1) and a switch SW2Is connected to one end of a switch SW1And the other end of (1) and a switch SW2Is connected in parallel with an externally supplied bias voltage Vcm(typically VDD/2), switch SW1And SW2The switching timings are the same.
Further, the dual dead-zone switch module is composed of four switches SW3～SW6Composition in which a switch SW3One end of and a switch SW4Is connected in parallel with a DAC feedback point X and a switch SW5One end of and a switch SW6Is connected in parallel with DAC feedback point Y and switch SW3And SW6The other end of the two feedback capacitors C respectivelyfb1And Cfb2A switch SW connected to the inverting output terminal and the non-inverting output terminal of the current multiplexing operational amplifier module4And SW5The other end is respectively connected with the positive phase input end and the negative phase input end of the current multiplexing operational amplifier module, and four switches SW3～SW6Is the same and is controlled by the clock signal S3.
Further, the current multiplexing operational amplifier module includes 10 MOS transistors M1-M10 and a switch capacitor common mode feedback module, wherein the source of the MOS transistor M9 is connected to the working voltage VDD, the gate of the MOS transistor M9 is connected to the dc bias voltage Vbias provided from the outside, the drain of the MOS transistor M9 is connected to the source of the MOS transistor M1 and the source of the MOS transistor M2, the gate of the MOS transistor M1 is connected to the gate of the MOS transistor M3 as the positive input terminal of the current multiplexing operational amplifier module, the gate of the MOS transistor M2 is connected to the gate of the MOS transistor M4 as the negative input terminal of the current multiplexing operational amplifier module, the drain of the MOS transistor M1 is connected to the source of the MOS transistor M5, the drain of the MOS transistor M2 is connected to the source of the MOS transistor M6, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M6 as the positive dc bias voltage Vbp provided from the outside, the drain of the MOS transistor M5 is connected to the drain of the MOS transistor M7 and the common mode feedback module as the negative output terminal of the switch, the drain of the MOS transistor M6 is connected with the drain of the MOS transistor M8 and the switch capacitor common mode feedback module to serve as the positive phase output end of the current multiplexing operational amplifier module, the gate of the MOS transistor M7 is connected with the gate of the MOS transistor M8 to provide a reverse direct current bias voltage Vbn externally, the source of the MOS transistor M7 is connected with the drain of the MOS transistor M3, the source of the MOS transistor M8 is connected with the drain of the MOS transistor M4, the source of the MOS transistor M3 is connected with the source of the MOS transistor M4 and the drain of the MOS transistor M10, the gate of the MOS transistor M10 is connected with the switch capacitor common mode feedback module, the source of the MOS transistor M10 is grounded, the MOS transistors M1, M2, M5, M6 and M9 are PMOS transistors, and the MOS transistors M3, M4, M7, M8 and M10 are NMOS transistors.
Further, the switched capacitor common mode feedback module comprises 6 switches SW7～SW12And 4 capacitors C1-C4, wherein the switch SW7One end of the switch SW is connected with one end of a capacitor C1 and the drain electrode of a MOS tube M67And one end of the capacitor C3 and the switch SW10Is connected to one end of a switch SW10Is connected to an externally supplied bias voltage Vcm(typically VDD/2), switch SW9One end of the switch SW is connected with one end of a capacitor C2 and the drain electrode of a MOS tube M59And one end of the capacitor C4 and the switch SW12Is connected to one end of a switch SW12Is connected to an externally supplied bias voltage VcmThe other end of the capacitor C4, the other end of the capacitor C3 and the switch SW8And a switch SW11One end of the two ends of the connecting rod is connected,switch SW11Is connected to an externally supplied reference voltage VbSwitch SW8The other end of the switch SW is connected with the other end of the capacitor C1, the other end of the capacitor C2 and the drain electrode of the MOS transistor M107、SW8、SW9Controlled by a clock signal S1, a switch SW10、SW11、SW12Under the control of the clock signal S2, the clock signals S1 and S2 are complementary in phase and have non-overlapping time zones (i.e., time zones that are low at the same time).
Further, the low level time zone of the clock signal S3 covers the rising edges of the clock signals Φ 1 and Φ 2.
Further, the rising and falling edges of the clock signals S1 and S2 are required to be in the non-overlapping time zones of the clock signals φ 1 and φ 2.
The invention greatly reduces the equivalent input noise of the low-frequency bandwidth region of the capacitive coupling amplifier through a high-frequency chopping technology and a current multiplexing technology, and meets the measurement requirements of weak human body electrical signals such as electroencephalogram EEG signals and the like. Aiming at the nonlinear influence of switching brought by the chopping switch switching process, the invention provides an improved double dead zone switching technology, and the linearity of the system is further improved. In addition, the invention avoids the possible common mode oscillation while reducing the power consumption by using the common mode feedback technology of the switched capacitor, and further reduces the influence of the switching on the system by reasonably arranging the switching time sequence.
Drawings
Fig. 1 is a schematic diagram of a Σ Δ type analog-to-digital converter system.
Fig. 2 is a schematic structural diagram of a low-noise high-linearity capacitive coupling amplifier according to the present invention.
FIG. 3 is a schematic view of the high-frequency chopper of the present invention.
FIG. 4 is a timing diagram of clock signals according to the present invention.
Fig. 5(a) is a schematic diagram of the output differential voltage transient waveforms of a capacitively coupled amplifier without dead-zone switches.
FIG. 5(b) illustrates the use of a dead band Switch (SW)4And SW5) Output differential voltage transient waveform display of the capacitive coupling amplifierIntention is.
FIG. 5(c) is a schematic diagram of the transient waveform of the output differential voltage of the capacitively coupled amplifier using the dual dead band switch according to the present invention.
Detailed Description
In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.
As shown in fig. 2, the low-noise high-linearity capacitive coupling amplifier for a Σ Δ bioelectrical signal measurement circuit of the present invention includes: the high-frequency chopper module, the direct current offset module, the dual dead zone switch and the current multiplexing operational amplifier.
In the present example, the high-frequency chopper modules are composed of high-frequency choppers CH1 and CH2 with the same structure, as shown in fig. 3, wherein each high-frequency chopper includes four transmission gates T1 to T4, the gate terminals of NMOS transistors T1 and T2 are Φ 1, the gate terminals of PMOS transistors are Φ 2, the gate terminals of NMOS transistors T3 and T4 are Φ 2, and the gate terminals of PMOS transistors are Φ 1, so that T1 and T2 are turned on when Φ 1 is high level, and T3 and T4 are turned on when Φ 2 is high level. Chopping clocks φ 1 and φ 2 are shown in FIG. 4 as a pair of complementary non-overlapping clocks; an input signal is chopped to a high frequency through a high-frequency chopper CH1, amplified through a capacitive coupling amplifier and chopped to a low frequency through a high-frequency chopper CH 2; the low-frequency flicker noise and the direct-current offset are amplified through the current multiplexing operational amplifier, then chopped to a high frequency through the high-frequency chopper CH2, so that the separation of the signal and the low-frequency noise in a frequency domain is realized, and finally the noise chopped to the high frequency is filtered through a low-pass filtering effect of an integrator in the sigma delta loop and a subsequent down-sampling filter. The chopping frequency is half of the sampling frequency, low-frequency noise can be chopped to the half position of the sampling frequency, and meanwhile, the low-frequency noise folded through sampling also falls on the half position of the sampling frequency.
In the embodiment, the direct current bias module consists of two resistors R with the same resistance value1、R2Switches SW identical to both control signals1、SW2Formed by periodically switching two switches SW1And SW2Is conducted at DAC feedback points X and Y and VcmAn equivalent high resistance is realized, thereby providing a static DC bias point for the input end of the capacitive coupling amplifier. Suppose SW1And SW2Control signal duty ratio of D, X and Y to VcmHas an equivalent input resistance of R1(2)D, when the pulse width of the control signal is extremely short, the bias resistor can realize equivalent impedance of several G, and R1And R2Only a few M, thereby greatly reducing the area required for the large bias resistor.
In the example, the current multiplexing operational amplifier consists of five PMOS tubes of M1, M2, M5, M6 and M9, five NMOS tubes of M3, M4, M7, M8 and M10 and a switch capacitor common-mode feedback module; the grid ends of the PMOS tube M1 and the NMOS tube M3 are connected to be used as the positive input end of the current multiplexing operational amplifier, and the grid ends of the PMOS tube M2 and the NMOS tube M4 are connected to be used as the negative input end of the current multiplexing operational amplifier, so the transconductance g of the current multiplexing operational amplifiermThe transconductance is the sum of the transconductances of the PMOS input tube M1 and the NMOS input tube M3, double transconductance is realized under the same current, and the equivalent input thermal noise of the operational amplifier is reduced on the premise of not improving the power consumption. PMOS tubes M5 and M6 and NMOS tubes M7 and M8 form a cascode tube, so that the output impedance of the operational amplifier is increased, and the high gain of the operational amplifier is realized; the grid end of the PMOS tube M9 is connected with the Vbias voltage provided by the current mirror, and provides tail current for the operation and amplification; and the grid end of the NMOS tube is connected with the CMFB output end of the common-mode feedback of the switch capacitor, so that the negative feedback of the output common-mode voltage is realized, and the output common-mode voltage is stabilized.
In the example, the switch capacitor common mode feedback is composed of capacitors C1-C4 and a switch SW7～SW12Composition, wherein C1 and C2 have equal volume value, C3 and C4 have equal volume value, SW7～SW9The control signals are S1, SW10～SW12The control signal is S2, and the switched capacitor common mode feedback control signals S1, S2 are a pair of complementary non-overlapping clocks as shown in fig. 4. The operational amplifier output voltage can be decomposed into a common mode component VcmoSum and difference mode components VdmoWherein the operational amplifier outputs a common mode component VcmoInfluenced by the tail current of the PMOS tube M9 and the tail current of the NMOS tube M10, when the tail current of the PMOS is larger than that of the NMOScmoIncreasing, otherwise decreasing; differential mode component V of operational amplifier outputdmoIt is determined by the op-amp input signal. Considering the common-mode signal of the operational amplifier output, in each common-mode feedback period of the switched capacitor, when S2 is high, the switch SW10～SW12On, SW7～SW9Open, capacitors C3 and C4 store a voltage proportional to Vcm-VbThe charge of (a); when S1 is high, switch SW7～SW9On, SW10～SW12When the NMOS transistor is disconnected, the C1 and the C2 carry out charge transfer with the C3 and the C4, and the CMFB changes in the process, so that the gate terminal of the NMOS transistor M10 is controlled to influence the tail current of the N transistor, and further the operational amplifier outputs a common-mode voltage VcmoA change is made. After several charge transfer cycles, VcmoCMFB approaching V graduallycm-VbThus by adjusting VbThe output common-mode voltage V of the operational amplifier can be controlled to be close to the CMFB value after the operational amplifier is stabilizedcmoApproach to the set Vcm. For the differential mode signal output by the operational amplifier, the input signal can be approximately regarded as unchanged in a short common mode feedback period of the switched capacitor, so that the differential mode signal V is outputdmoAnd will not change. In summary, V is adjustedbThe common-mode feedback of the switched capacitor can stabilize the output common-mode voltage at the set V similar to the stabilized CMFB voltagecmAnd meanwhile, the output differential mode voltage of the operational amplifier is not influenced. In addition, to avoid possible occurrence of the switch SW7～SW9The switching process is arranged in the dead time of chopping, so that the fluctuation of charge balance and the switching process on the output differential mode voltage of the operational amplifier is prevented from being introduced into the system.
The dual dead band switch in this example consists of four identical switches SW3～SW6The components, their control signals are the same, and the timing sequence is shown in fig. 4. According to fig. 1, an input signal and a DAC output signal of a Σ Δ analog-to-digital converter are differentiated in a differentiator, wherein the DAC output signal is a signal restored after quantizing the input signal. Specifically in fig. 2, the input signal is chopped to high frequency by CH1 and is differenced and amplified with the feedback signal in a capacitively coupled amplifierLarge, this link is charged at CinFeedback DAC capacitor and feedback capacitor CfbAnd charge balance is realized. As shown in FIG. 4, each time a chopping rising edge (t1, t3) occurs, the input signal is at the input capacitance Cin1、Cin2The front end of the feedback DAC generates an abrupt change, and the input charge and the feedback DAC charge generated by the abrupt change are on the input capacitor CinAnd the DAC capacitors, while a glitch is created between DAC feedback points X and Y. The dual dead-zone switch is turned off before the chopping rising edge begins and continues to be turned off until the DAC feedback points X and Y where the differential signal is stable, wherein: switch SW4And SW5Prevent glitches from being amplified to the operational amplifier output via the current multiplexing operational amplifier, switch SW3And SW6Glitch prevention via feedback capacitance Cfb1And Cfb2Coupled to the op-amp output. When the input signal and the feedback signal are at CinAnd after the balance between the DAC capacitance is stabilized, the dual dead-zone switch SW3～SW6Closing, and transporting the differential charge to a feedback capacitor C through a current multiplexing operational amplifierfbIn (2), an amplification process is implemented. In fact, the dual dead-zone switch realizes the isolation of a difference link and an amplification link in the capacitive coupling amplifier, the difference process and the amplification process are carried out simultaneously in the traditional capacitive coupling amplifier, therefore, burrs generated in the difference process can be amplified to an output end so as to deteriorate the linearity, the dual dead-zone switch carries out the difference link through adding an extra phase, then amplifies the residual voltage after the difference, and eliminates the influence caused by the burrs generated in the difference link.
FIGS. 5(a) to 5(c) show the use of the dead-zone Switch (SW) instead of the dead-zone switch4And SW5) And outputting transient waveforms of the differential voltage by using the capacitive coupling amplifier after the dual dead zone switch (corresponding to the invention). It can be seen that fig. 5(b) adds to fig. 5(C) a noise component related to the frequency of the input signal, which is a spur at DAC feedback point X, Y through feedback capacitor CfbCoupled to the output; FIG. 5(a) is a diagram in which a noise component related to the frequency of an input signal is superimposed on the basis of FIG. 5(b), andthe noise components are amplified to the output by the current-multiplexed op-amp, and thus the two noise components are in opposite phase. Analyzing the frequency spectrum output by the sigma delta bioelectricity signal measuring circuit under the condition that the input signals are the same, wherein the THD, the SNDR and the SFDR of the circuit are respectively-89.7 dB, 89.7dB and 89.7dB respectively when the dead zone switch is not used; when the dead zone switch is used, the THD is-114.1 dB, the SNDR is 112.7dB, and the SFDR is 115.3 dB; the THD is-119.1 dB, the SNDR is 117.9dB, and the SFDR is 122dB when the dual dead zone switch is used. Therefore, the double dead-zone switch further reduces the harmonic component of the signal on the basis of the dead-zone switch, improves the linearity of the amplifier, and accordingly improves the signal-to-noise-distortion ratio of the system.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.

Claims (9)

1. A low-noise, high-linearity capacitively coupled amplifier for use in bioelectrical signal measurement circuits, characterized by: the device comprises a high-frequency chopping module, a direct-current bias module, a double dead zone switch module and a current multiplexing operational amplifier module; wherein:
the high-frequency chopping module consists of two high-frequency choppers CH1 and CH2, and CH1 is used for chopping the low-frequency bioelectric signals measured by the measuring circuit in a differential form into high-frequency bioelectric signals; the CH2 is used for chopping the high-frequency bioelectricity signals amplified by the current multiplexing operational amplifier module into amplified low-frequency bioelectricity signals, and chopping low-frequency noise in the amplified high-frequency bioelectricity signals into high-frequency noise;
the direct current bias module is used for providing direct current bias voltage for an input signal of the current multiplexing operational amplifier;
the double dead zone switch module is used for eliminating burrs in high-frequency bioelectricity signals obtained by chopping CH 1;
the current multiplexing operational amplifier module is used for amplifying the high-frequency bioelectricity signals after the burrs are removed.
2. The low-noise high-linearity capacitively coupled amplifier of claim 1, wherein: the positive phase input end of the high-frequency chopper CH1 is connected with the measuring circuit to output positive phase low-frequency bioelectricity signals, the negative phase input end is connected with the measuring circuit to output negative phase low-frequency bioelectricity signals, and the positive phase output end and the negative phase output end are respectively connected with the input capacitor Cin1And Cin2Connected to the dual dead band switch module; the positive phase input end of the high-frequency chopper CH2 is connected with the positive phase output end of the current multiplexing operational amplifier module, the negative phase input end of the high-frequency chopper CH2 is connected with the negative phase output end of the current multiplexing operational amplifier module, and the positive phase output end and the negative phase output end output the low-frequency bioelectricity signals amplified in a differential mode.
3. The low-noise high-linearity capacitively coupled amplifier of claim 2, wherein: the high-frequency choppers CH1 and CH2 have the same structure and are composed of four transmission gates T1-T4, the input end of a transmission gate T1 is connected with the input end of a transmission gate T4 to serve as a positive phase input end of the high-frequency chopper, the output end of the transmission gate T1 and the output end of the transmission gate T3 serve as a positive phase output end of the high-frequency chopper, the input end of a transmission gate T2 is connected with the input end of a transmission gate T3 to serve as an inverted phase input end of the high-frequency chopper, the output end of the transmission gate T2 and the output end of the transmission gate T4 serve as an inverted phase output end of the high-frequency chopper, gates of NMOS tubes in the transmission gates T1 and T2 and gates of PMOS tubes in the transmission gates T3 and T4 are connected with a clock signal phi 1, gates of PMOS tubes in the transmission gates T1 and T2 and overlapping gates of NMOS tubes in the transmission gates T3 and T4 are connected.
4. The low-noise high-linearity capacitively coupled amplifier of claim 3, wherein: the direct current bias module comprises two resistors R with the same resistance value1And R2And two switches SW1And SW2Resistance R1One terminal of and an input capacitor Cin1One end of which is connected as a DAC feedback point X, an input capacitor Cin1The other end of the resistor R is connected with the non-inverting output end of the high-frequency chopper CH12One terminal of and an input capacitor Cin2One end of which is connected as a DAC feedback point Y, an input capacitor Cin2The other end of the resistor R is connected with the inverting output end of the high-frequency chopper CH11And the other end of (1) and a switch SW1Is connected to one end of a resistor R2And the other end of (1) and a switch SW2Is connected to one end of a switch SW1And the other end of (1) and a switch SW2Is connected in parallel with an externally supplied bias voltage VcmSwitch SW1And SW2The switching timings are the same.
5. The low-noise high-linearity capacitively coupled amplifier of claim 4, wherein: the dual dead zone switch module is composed of four switches SW3～SW6Composition in which a switch SW3One end of and a switch SW4Is connected in parallel with a DAC feedback point X and a switch SW5One end of and a switch SW6Is connected in parallel with DAC feedback point Y and switch SW3And SW6The other end of the two feedback capacitors C respectivelyfb1And Cfb2A switch SW connected to the inverting output terminal and the non-inverting output terminal of the current multiplexing operational amplifier module4And SW5The other end is respectively connected with the positive phase input end and the negative phase input end of the current multiplexing operational amplifier module, and four switches SW3～SW6Is the same and is controlled by the clock signal S3.
6. The low-noise high-linearity capacitively coupled amplifier of claim 5, wherein: the current multiplexing operational amplifier module comprises 10 MOS tubes M1-M10 and a switch capacitor common mode feedback module, wherein the source of the MOS tube M9 is connected with a working voltage VDD, the gate of the MOS tube M9 is connected with a direct current bias voltage Vbias provided by the outside, the drain of the MOS tube M9 is connected with the source of the MOS tube M1 and the source of the MOS tube M2, the gate of the MOS tube M1 is connected with the gate of the MOS tube M3 to be used as a positive phase input end of the current multiplexing operational amplifier module, the gate of the MOS tube M2 is connected with the gate of the MOS tube M4 to be used as a negative phase input end of the current multiplexing operational amplifier module, the drain of the MOS tube M1 is connected with the source of the MOS tube M5, the drain of the MOS tube M2 is connected with the source of the MOS tube M6, the gate of the MOS tube M5 is connected with the gate of the MOS tube M6 to be used as a positive phase bias voltage Vbp provided by the outside, the drain of the MOS tube M5 is connected with the drain of the MOS tube M7, the drain of the MOS transistor M6 is connected with the drain of the MOS transistor M8 and the switch capacitor common mode feedback module to serve as the positive phase output end of the current multiplexing operational amplifier module, the gate of the MOS transistor M7 is connected with the gate of the MOS transistor M8 to provide a reverse direct current bias voltage Vbn externally, the source of the MOS transistor M7 is connected with the drain of the MOS transistor M3, the source of the MOS transistor M8 is connected with the drain of the MOS transistor M4, the source of the MOS transistor M3 is connected with the source of the MOS transistor M4 and the drain of the MOS transistor M10, the gate of the MOS transistor M10 is connected with the switch capacitor common mode feedback module, the source of the MOS transistor M10 is grounded, the MOS transistors M1, M2, M5, M6 and M9 are PMOS transistors, and the MOS transistors M3, M4, M7, M8 and M10 are NMOS transistors.
7. The low-noise high-linearity capacitively coupled amplifier of claim 6, wherein: the switch capacitor common mode feedback module comprises 6 switches SW7～SW12And 4 capacitors C1-C4, wherein the switch SW7One end of the switch SW is connected with one end of a capacitor C1 and the drain electrode of a MOS tube M67And one end of the capacitor C3 and the switch SW10Is connected to one end of a switch SW10Is connected to an externally supplied bias voltage VcmSwitch SW9One end of the switch SW is connected with one end of a capacitor C2 and the drain electrode of a MOS tube M59And one end of the capacitor C4 and the switch SW12Is connected to one end of a switch SW12Is connected to an externally supplied bias voltage VcmThe other end of the capacitor C4, the other end of the capacitor C3 and the switch SW8And a switch SW11Is connected to one end of a switch SW11Is connected to an externally supplied reference voltage VbSwitch SW8And the other end of the capacitor C1One end of the capacitor C2, the other end of the capacitor C2 and the drain of the MOS transistor M10 are connected, and the switch SW7、SW8、SW9Controlled by a clock signal S1, a switch SW10、SW11、SW12Controlled by the clock signal S2, the clock signals S1 and S2 are complementary in phase and have non-overlapping time zones.
8. The low-noise high-linearity capacitively coupled amplifier of claim 5, wherein: the low time zone of the clock signal S3 covers the rising edges of the clock signals phi 1 and phi 2.
9. The low-noise high-linearity capacitively coupled amplifier of claim 7, wherein: the rising and falling edges of the clock signals S1 and S2 are required to be in the non-overlapping time zones of clock signals φ 1 and φ 2.
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Application publication date: 20210319