CN112531874A - Hardware interlocking circuit - Google Patents
Hardware interlocking circuit Download PDFInfo
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- CN112531874A CN112531874A CN202011327156.2A CN202011327156A CN112531874A CN 112531874 A CN112531874 A CN 112531874A CN 202011327156 A CN202011327156 A CN 202011327156A CN 112531874 A CN112531874 A CN 112531874A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
- H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
- H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
- H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
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Abstract
The invention provides a hardware interlock circuit, which comprises a first triode, a second triode, a third triode, a fourth triode and a fifth triode, wherein the base electrode of the first triode is connected with the output end of an external singlechip, the emitting electrode of the first triode is grounded, the collecting electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the second triode is connected with a power supply, the collecting electrode of the second triode is connected with the emitting electrode of the third triode, the base electrode of the third triode detects commercial power, the collecting electrode of the third triode is connected with the base electrode of the fifth triode, the emitting electrode of the fifth triode is grounded, the collecting electrode of the fifth triode is connected with the base electrode of the fourth triode, the emitting electrode of the fourth triode is connected with the power supply, and the collecting electrode of the fourth triode is used as the output. The technical scheme provided by the invention can realize self-protection under the abnormal condition, and ensure the use safety of the device.
Description
Technical Field
The invention relates to the field of emergency power supply, in particular to a hardware interlocking circuit.
Background
At present, in the elevator control field, for coping with the power failure of a power grid, a power failure emergency device is often required to be equipped to ensure that the elevator can normally run to a safe position after the power failure, so that the elevator is prevented from staying in an illegal area, and further potential safety hazards are prevented from being generated.
And still need to keep elevator work after the commercial power falls down, generally adopt the mode that the battery boosts among the prior art, make the elevator can the short time operation. The power failure emergency device generally uses a mode of reading battery charging voltage to confirm whether commercial power exists, an external circuit detects a door lock and a door area to judge whether the commercial power can be output, and if the commercial power can be output, a single chip Microcomputer (MCU) sends an instruction to control the output. In the design, the external circuit and the output control are isolated by the MCU, when the MCU chip is abnormal, the commercial power can be output or the commercial power can be output, so the potential safety hazard will occur under such abnormal conditions, and how to avoid the potential safety hazard is an urgent need in the industry.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a hardware interlock circuit, which can realize self-protection and ensure the safety of the device in use when there is an abnormality.
The invention provides a hardware interlock circuit, which comprises a first triode, a second triode, a third triode, a fourth triode and a fifth triode, wherein, the base electrode of the first triode is connected with the output end of the external singlechip, the emitting electrode of the first triode is grounded, the collector of the first triode is connected with the base of the second triode, the emitter of the second triode is connected with a power supply, the collector of the second triode is connected with the emitter of the third triode, the base of the third triode detects the commercial power, the collector of the third triode is connected with the base of the fifth triode, the emitter of the fifth triode is grounded, and the collector of the fifth triode is connected with the base of the fourth triode, the emitter of the fourth triode is connected with the power supply, and the collector of the fourth triode is used as an output end to output an emergency power supply.
Preferably, the circuit further comprises a first resistor, a second resistor and a first capacitor, wherein one end of the first resistor is connected with the base of the first triode, the other end of the first resistor is connected with the output end of the external singlechip, one end of the second resistor is connected with one end of the first resistor, the other end of the second resistor is grounded, and the two ends of the first capacitor are respectively connected with the two ends of the second resistor.
Preferably, the circuit further includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor, wherein one end of the third resistor is connected to the collector of the first triode, the other end of the third resistor is connected to the base of the second triode, one end of the fourth resistor is connected to the power supply, the other end of the fourth resistor is connected to the base of the third triode, one end of the fifth resistor is connected to the power supply, the other end of the fifth resistor is connected to the base of the second triode, one end of the seventh resistor is connected to the base of the third triode, the other end of the seventh resistor is connected to the commercial power detecting terminal, one end of the sixth resistor is connected to the commercial power detecting terminal, and the other end of the sixth resistor is grounded.
Preferably, the circuit further includes a second capacitor, an eighth resistor, a ninth resistor and a tenth resistor, wherein one end of the second capacitor is connected to the base of the third triode, the other end of the second capacitor is grounded, one end of the eighth resistor is connected to the collector of the third triode, the other end of the eighth resistor is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to the base of the fifth triode, one end of the tenth resistor is connected to the base of the fifth triode, and the other end of the tenth resistor is grounded.
Preferably, the circuit further includes a third capacitor, an eleventh resistor and a twelfth resistor, wherein one end of the third capacitor is connected to the base of the fifth triode, the other end of the third capacitor is grounded, one end of the eleventh resistor is connected to the collector of the fifth triode, the other end of the eleventh resistor is connected to the power supply, one end of the twelfth resistor is connected to the base of the fourth triode, and the other end of the twelfth resistor is connected to the collector of the fifth triode.
Preferably, the circuit further includes a fourth capacitor, a relay and a thirteenth resistor, wherein one end of the fourth capacitor is connected to the collector of the fourth triode, the other end of the fourth capacitor is grounded, two input ends of the relay receive a door lock signal respectively, a first output end of the relay is connected to one end of the thirteenth resistor, and the other end of the thirteenth resistor is connected to the 12V power supply.
Preferably, the circuit further includes a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a sixth triode, wherein one end of the fourteenth resistor is connected to the 24V power supply, the other end of the fourteenth resistor is connected to a collector of the sixth triode, one end of the fifteenth resistor is connected to the commercial power detecting terminal, the other end of the fifteenth resistor is connected to a base of the sixth triode, an emitter of the sixth triode is grounded, one end of the sixteenth resistor is connected to a base of the sixth triode, and the other end of the sixteenth resistor is grounded.
Preferably, the circuit further includes a winding, a seventeenth resistor and a seventh triode, wherein the winding is close to the second output end of the relay, the positive electrode of the winding is connected with the 24V power supply, the negative electrode of the winding is connected with the collector of the seventh triode, the emitter of the seventh triode is grounded, the base of the seventh triode is connected with the collector of the sixth triode, one end of the seventeenth resistor is connected with the base of the seventh triode, and the other end of the seventeenth resistor is grounded.
Preferably, the circuit still includes first diode, second diode, eighteenth resistance, nineteenth resistance and fifth electric capacity, wherein, the positive pole of first diode with the positive pole of second diode is all connected the collecting electrode of seventh triode, the negative pole of first diode with the negative pole of second diode all connects the 24V power, the one end of eighteenth resistance is connected the second output of relay, the other end of eighteenth resistance is connected the one end of nineteenth resistance, the other end ground connection of nineteenth resistance, the one end of fifth electric capacity is connected the other end of eighteenth resistance, the other end of fifth electric capacity is connected the other end of nineteenth resistance and ground connection.
Preferably, the circuit further comprises an optical coupler and a sixth capacitor, wherein two ends of a primary side of the optical coupler are respectively connected with two ends of the fifth capacitor, one end of the secondary side of the optical coupler is grounded, the other end of the secondary side of the optical coupler serves as an output end to output a door lock detection signal to an external single chip microcomputer, and two ends of the sixth capacitor are respectively connected with two ends of the secondary side of the optical coupler.
The technical scheme provided by the invention has the following advantages: hardware interlocking is added aiming at output drive, charging voltage is added at a drive control end to carry out AND control, when commercial power exists, control over drive output is realized through software and hardware interlocking, at the moment, if a single chip Microcomputer (MCU) outputs abnormally, abnormal protection can be realized through commercial power locking, the self-protection can be realized under the condition that the device is abnormal, and the use safety of the device is guaranteed.
Drawings
Fig. 1 is a schematic diagram of a driving interlock circuit in a hardware interlock circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a door lock detection circuit in a hardware interlock circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A hardware interlock circuit provided by the present invention will be described in detail below.
Fig. 1 is a schematic diagram of a driving interlock circuit in a hardware interlock circuit according to an embodiment of the present invention.
In the embodiment, the hardware interlock circuit is particularly applied to an elevator control device, and can ensure that self-protection can be realized even if a single chip Microcomputer (MCU) in an elevator is abnormal, and the safety of the use of the elevator is ensured.
In this embodiment, the hardware interlock circuit includes a driving interlock circuit, which is connected to an output terminal (e.g., a CRT _ MCU terminal in fig. 1) of the external single chip microcomputer and is configured to receive a control signal output by the single chip microcomputer. The driving interlock circuit comprises a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4 and a fifth triode Q5, wherein the first triode Q1 and the fifth triode Q5 are both NPN type triodes, and the second triode Q2, the third triode Q3 and the fourth triode Q4 are all PNP type triodes. Wherein, the base electrode of the first triode Q1 is connected with the output end of an external singlechip, namely, the CRT _ MCU end of the singlechip, the emitting electrode of the first triode Q1 is grounded GND, the collector electrode of the first triode Q1 is connected with the base electrode of the second triode Q2, the emitting electrode of the second triode Q2 is connected with a power supply, namely 12V power supply, the collector of the second transistor Q2 is connected with the emitter of the third transistor Q3, the base of the third transistor Q3 detects the commercial power, namely, the base electrode of the third triode Q3 is connected with the BAT _12V end, the collector electrode of the third triode Q3 is connected with the base electrode of the fifth triode Q5, the emitter electrode of the fifth triode Q5 is grounded GND, the collector electrode of the fifth triode Q5 is connected with the base electrode of the fourth triode Q4, the emitter electrode of the fourth triode Q4 is connected with the power supply, i.e., 12V power supply, and the collector of the fourth transistor Q4 is used as an output terminal (e.g., PWM _ CTR terminal in fig. 1) to output emergency power.
In this embodiment, the driving interlock circuit further includes a first resistor R1 and a second resistor R2, wherein one end of the first resistor R1 is connected to the base of the first transistor Q1, the other end of the first resistor R1 is connected to the output terminal of the external single chip, that is, the CRT _ MCU terminal of the single chip, one end of the second resistor R2 is connected to one end of the first resistor R1, and the other end of the second resistor R2 is grounded to GND.
In this embodiment, the driving interlock circuit further includes a first capacitor C1, wherein two ends of the first capacitor C1 are respectively connected to two ends of the second resistor R2 and are commonly grounded GND.
In this embodiment, the driving interlock circuit further includes a third resistor R3, a fourth resistor R4, and a fifth resistor R5, wherein one end of the third resistor R3 is connected to the collector of the first transistor Q1, the other end of the third resistor R3 is connected to the base of the second transistor Q2, one end of the fourth resistor R4 is connected to the power supply, i.e., the 12V power supply, the other end of the fourth resistor R4 is connected to the base of the third transistor Q3, one end of the fifth resistor R5 is connected to the power supply, i.e., the 12V power supply, and the other end of the fifth resistor R5 is connected to the base of the second transistor Q2.
In this embodiment, the driving interlock circuit further includes a sixth resistor R6 and a seventh resistor R7, wherein one end of the seventh resistor R7 is connected to the base of the third transistor Q3, the other end of the seventh resistor R7 is connected to the mains supply detection terminal, that is, the other end of the seventh resistor R7 is connected to the BAT _12V terminal, one end of the sixth resistor R6 is connected to the mains supply detection terminal, that is, one end of the sixth resistor R6 is connected to the BAT _12V terminal, and the other end of the sixth resistor R6 is grounded to GND.
In this embodiment, the driving interlock circuit further includes a second capacitor C2, wherein one end of the second capacitor C2 is connected to the base of the third transistor Q3, and the other end of the second capacitor C2 and the other end of the sixth resistor R6 are connected to the ground GND.
In this embodiment, the driving interlock circuit further includes an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10, wherein one end of the eighth resistor R8 is connected to the collector of the third transistor Q3, the other end of the eighth resistor R8 is connected to one end of the ninth resistor R9, the other end of the ninth resistor R9 is connected to the base of the fifth transistor Q5, one end of the tenth resistor R10 is connected to the base of the fifth transistor Q5, and the other end of the tenth resistor R10 is grounded to GND.
In this embodiment, the driving interlock circuit further includes a third capacitor C3, wherein one end of the third capacitor C3 is connected to the base of the fifth transistor Q5, and the other end of the third capacitor C3 and the other end of the tenth resistor R10 are connected to the ground GND.
In this embodiment, the driving interlock circuit further includes an eleventh resistor R11 and a twelfth resistor R12, wherein one end of the eleventh resistor R11 is connected to the collector of the fifth transistor Q5, the other end of the eleventh resistor R11 is connected to the power supply, i.e., the 12V power supply, one end of the twelfth resistor R12 is connected to the base of the fourth transistor Q4, the emitter of the fourth transistor Q4 is connected to the power supply, i.e., the 12V power supply, and the other end of the twelfth resistor R12 is connected to the collector of the fifth transistor Q5.
In this embodiment, the driving interlock circuit further includes a fourth capacitor C4, wherein one end of the fourth capacitor C4 is connected to the collector of the fourth transistor Q4, and the other end of the fourth capacitor C4 is connected to the ground GND.
In this embodiment, the operation principle of the drive interlock circuit is as follows: when the singlechip detects that the door lock is short-circuited, the commercial power is disconnected and an output instruction is obtained, the singlechip sends an instruction to control the MCU _ CTR end to be high, namely, a high level is output, at the moment, the first triode Q1 and the second triode Q2 are conducted, if no commercial power exists at the moment, namely, the BAT _12V end is detected to be power-off, the third triode Q3 is conducted, at the moment, the fourth triode Q4 and the fifth triode Q5 are driven to be conducted, at the moment, the singlechip obtains a driving enabling signal to send a driving signal, namely, an emergency power supply is output from the collector electrode of the fourth triode Q4, if the CRT _ MCU end is abnormally operated due to the fault of the singlechip, at the moment, the commercial power exists, namely, the BAT _12V end is powered, the third triode Q3 is turned off, at the moment, the driving enabling output cannot be realized due to the non-conduction of the fifth triode Q5, at the moment, the emergency power supply is, thereby realizing hardware interlock of drive control.
In addition, the hardware interlock circuit also includes a door lock detection circuit, as shown in FIG. 2.
Fig. 2 is a schematic diagram of a door lock detection circuit in a hardware interlock circuit according to an embodiment of the present invention.
In this embodiment, the latch detection circuit includes a relay RLY and a thirteenth resistor R13, wherein two input terminals of the relay RLY receive latch signals (such as DL + and DL-' in fig. 2), respectively, a first output terminal of the relay RLY is connected with one end of the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is connected with a 12V power supply.
In this embodiment, the door lock detection circuit further includes a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a sixth triode Q6, wherein the sixth triode Q6 is an NPN-type triode, one end of the fourteenth resistor R14 is connected to the 24V power supply, the other end of the fourteenth resistor R14 is connected to the collector of the sixth triode Q6, one end of the fifteenth resistor R15 is connected to the utility power detection terminal, that is, one end of the fifteenth resistor R15 is connected to the BAT — 12V terminal, the other end of the fifteenth resistor R15 is connected to the base of the sixth triode Q6, the emitter of the sixth triode Q6 is grounded GND, one end of the sixteenth resistor R16 is connected to the base of the sixth triode Q6, and the other end of the sixteenth resistor R16 and the emitter of the sixth triode Q6 are commonly grounded.
In this embodiment, the door lock detection circuit further includes a winding W1, wherein the winding W1 is close to the second output terminal of the relay RLY, and the positive pole of the winding W1 is connected to a 24V power supply.
In this embodiment, the door lock detection circuit further includes a seventeenth resistor R17 and a seventh transistor Q7, wherein the negative electrode of the winding W1 is connected to the collector of the seventh transistor Q7, the emitter of the seventh transistor Q7 is grounded to GND, the base of the seventh transistor Q7 is connected to the collector of the sixth transistor Q6, one end of the seventeenth resistor R17 is connected to the base of the seventh transistor Q7, and the other end of the seventeenth resistor R17 and the emitter of the seventh transistor Q7 are commonly grounded to GND.
In this embodiment, the door lock detection circuit further includes a first diode D1 and a second diode D2, wherein the anode of the first diode D1 and the anode of the second diode D2 are both connected to the collector of the seventh transistor Q7; the cathode of the first diode D1 and the cathode of the second diode D2 are both connected to a 24V power supply, i.e., are both connected to the anode of the winding W1.
In the present embodiment, the door lock detection circuit further includes an eighteenth resistor R18, a nineteenth resistor R19, and a fifth capacitor C5, wherein one end of the eighteenth resistor R18 is connected to the second output terminal of the relay RLY, the other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19, the other end of the nineteenth resistor R19 is grounded GND, one end of the fifth capacitor C5 is connected to the other end of the eighteenth resistor R18, and the other end of the fifth capacitor C5 is connected to the other end of the nineteenth resistor R19 and commonly grounded GND.
In this embodiment, this lock detection circuitry still includes opto-coupler U1 and sixth electric capacity C6, wherein, the both ends of fifth electric capacity C5 are connected respectively to the both ends of opto-coupler U1's primary limit, one end ground GND in the secondary of opto-coupler U1, the other end in the secondary of opto-coupler U1 is as output lock detected signal to outside singlechip, DL end is connected to the other end in the secondary of opto-coupler U1 promptly, both ends in the secondary of opto-coupler U1 are connected respectively to the both ends of sixth electric capacity C6.
In the present embodiment, the operation principle of the door lock detection circuit is as follows: the door lock signal DL +/DL-is connected to an internal door lock detection circuit through the relay RLY, when no commercial power exists, namely the BAT _12V end in the figure 2 loses power, the seventh triode Q7 is conducted, the sixth triode Q6 is disconnected, the relay RLY attracts, the primary side of the optical coupler U1 is conducted, the secondary side DL end signal of the optical coupler U1 is pulled down, the level is identified through software at the moment, the door lock is judged to be conducted, when the commercial power exists, namely the BAT _12V end in the figure 2 gets power, the relay RLY does not attract, the software detects that the door lock is disconnected, the door lock cannot operate, and therefore hardware blocking of door lock detection can be achieved.
The technical scheme provided by the invention has the following advantages: hardware interlocking is added aiming at output drive, charging voltage is added at a drive control end to carry out AND control, when commercial power exists, control over drive output is realized through software and hardware interlocking, at the moment, if a single chip Microcomputer (MCU) outputs abnormally, abnormal protection can be realized through commercial power locking, the self-protection can be realized under the condition that the device is abnormal, and the use safety of the device is guaranteed.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A hardware interlock circuit is characterized in that the circuit comprises a first triode, a second triode, a third triode, a fourth triode and a fifth triode, wherein, the base electrode of the first triode is connected with the output end of the external singlechip, the emitting electrode of the first triode is grounded, the collector of the first triode is connected with the base of the second triode, the emitter of the second triode is connected with a power supply, the collector of the second triode is connected with the emitter of the third triode, the base of the third triode detects the commercial power, the collector of the third triode is connected with the base of the fifth triode, the emitter of the fifth triode is grounded, and the collector of the fifth triode is connected with the base of the fourth triode, the emitter of the fourth triode is connected with the power supply, and the collector of the fourth triode is used as an output end to output an emergency power supply.
2. The hardware interlock circuit of claim 1, further comprising a first resistor, a second resistor and a first capacitor, wherein one end of the first resistor is connected to the base of the first transistor, the other end of the first resistor is connected to the output terminal of the external single chip, one end of the second resistor is connected to one end of the first resistor, the other end of the second resistor is grounded, and two ends of the first capacitor are respectively connected to two ends of the second resistor.
3. The hardware interlock circuit of claim 2, further comprising a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, wherein one end of the third resistor is connected to the collector of the first transistor, the other end of the third resistor is connected to the base of the second transistor, one end of the fourth resistor is connected to the power source, the other end of the fourth resistor is connected to the base of the third transistor, one end of the fifth resistor is connected to the power source, the other end of the fifth resistor is connected to the base of the second transistor, one end of the seventh resistor is connected to the base of the third transistor, the other end of the seventh resistor is connected to the utility power detecting terminal, one end of the sixth resistor is connected to the utility power detecting terminal, and the other end of the sixth resistor is grounded.
4. The hardware interlock circuit of claim 3, further comprising a second capacitor, an eighth resistor, a ninth resistor, and a tenth resistor, wherein one end of the second capacitor is connected to the base of the third transistor, the other end of the second capacitor is grounded, one end of the eighth resistor is connected to the collector of the third transistor, the other end of the eighth resistor is connected to one end of the ninth resistor, the other end of the ninth resistor is connected to the base of the fifth transistor, one end of the tenth resistor is connected to the base of the fifth transistor, and the other end of the tenth resistor is grounded.
5. The hardware interlock circuit of claim 4, further comprising a third capacitor, an eleventh resistor, and a twelfth resistor, wherein one end of the third capacitor is connected to the base of the fifth transistor, the other end of the third capacitor is connected to ground, one end of the eleventh resistor is connected to the collector of the fifth transistor, the other end of the eleventh resistor is connected to the power source, one end of the twelfth resistor is connected to the base of the fourth transistor, and the other end of the twelfth resistor is connected to the collector of the fifth transistor.
6. The hardware interlock circuit of claim 5, further comprising a fourth capacitor, a relay and a thirteenth resistor, wherein one terminal of the fourth capacitor is connected to the collector of the fourth transistor, the other terminal of the fourth capacitor is connected to ground, two input terminals of the relay respectively receive a door lock signal, the first output terminal of the relay is connected to one terminal of the thirteenth resistor, and the other terminal of the thirteenth resistor is connected to a 12V power supply.
7. The hardware interlock circuit as claimed in claim 6, wherein the circuit further comprises a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a sixth triode, wherein one end of the fourteenth resistor is connected to the 24V power supply, the other end of the fourteenth resistor is connected to the collector of the sixth triode, one end of the fifteenth resistor is connected to the commercial power detection terminal, the other end of the fifteenth resistor is connected to the base of the sixth triode, the emitter of the sixth triode is grounded, one end of the sixteenth resistor is connected to the base of the sixth triode, and the other end of the sixteenth resistor is grounded.
8. The hardware interlock circuit of claim 7, further comprising a winding, a seventeenth resistor, and a seventh transistor, wherein the winding is near the second output of the relay, the positive terminal of the winding is connected to a 24V power supply, the negative terminal of the winding is connected to the collector of the seventh transistor, the emitter of the seventh transistor is grounded, the base of the seventh transistor is connected to the collector of the sixth transistor, one terminal of the seventeenth resistor is connected to the base of the seventh transistor, and the other terminal of the seventeenth resistor is grounded.
9. The hardware interlock circuit of claim 8, further comprising a first diode, a second diode, an eighteenth resistor, a nineteenth resistor, and a fifth capacitor, wherein the anode of the first diode and the anode of the second diode are connected to the collector of the seventh transistor, the cathode of the first diode and the cathode of the second diode are connected to a 24V power source, one end of the eighteenth resistor is connected to the second output terminal of the relay, the other end of the eighteenth resistor is connected to one end of the nineteenth resistor, the other end of the nineteenth resistor is grounded, one end of the fifth capacitor is connected to the other end of the eighteenth resistor, and the other end of the fifth capacitor is connected to the other end of the nineteenth resistor and grounded.
10. The hardware interlock circuit of claim 9, further comprising an optocoupler and a sixth capacitor, wherein two ends of a primary side of the optocoupler are respectively connected to two ends of the fifth capacitor, one end of a secondary side of the optocoupler is grounded, the other end of the secondary side of the optocoupler is used as an output end to output a door lock detection signal to an external single chip, and two ends of the sixth capacitor are respectively connected to two ends of the secondary side of the optocoupler.
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| CN202011327156.2A CN112531874B (en) | 2020-11-23 | 2020-11-23 | Hardware interlocking circuit |
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| CN202011327156.2A CN112531874B (en) | 2020-11-23 | 2020-11-23 | Hardware interlocking circuit |
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| CN112531874B CN112531874B (en) | 2023-04-07 |
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| CN201238201Y (en) * | 2008-07-11 | 2009-05-13 | 颜怀略 | Special uninterrupted emergency operation power supply device for elevator with automatic leveling function |
| US20140209415A1 (en) * | 2013-01-29 | 2014-07-31 | Reynolds & Reynolds Electronics, Inc. | Emergency Back-Up Power System For Traction Elevators |
| CN104283540A (en) * | 2014-10-31 | 2015-01-14 | 德力西电气有限公司 | Electric interlock circuit |
| CN205082005U (en) * | 2015-10-10 | 2016-03-09 | 广州华元电气科技有限公司 | Emergency light invertion power supply's automatic switch -over interlock circuit |
| CN211857234U (en) * | 2020-03-24 | 2020-11-03 | 上海广为美线电源电器有限公司 | Interlocking protection circuit, switching circuit, double-voltage conversion circuit, electronic equipment and emergency starting power supply |
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| CN112531874B (en) | 2023-04-07 |
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