CN112531073B - Preparation method of side-incident SOI (silicon on insulator) based Si/SiGe HPT (high-performance heterojunction bipolar transistor) with photonic crystal structure - Google Patents

Preparation method of side-incident SOI (silicon on insulator) based Si/SiGe HPT (high-performance heterojunction bipolar transistor) with photonic crystal structure Download PDF

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CN112531073B
CN112531073B CN202011033951.0A CN202011033951A CN112531073B CN 112531073 B CN112531073 B CN 112531073B CN 202011033951 A CN202011033951 A CN 202011033951A CN 112531073 B CN112531073 B CN 112531073B
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谢红云
刘先程
向洋
郭敏
沙印
张万荣
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Beijing University of Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0232Optical elements or arrangements associated with the device
    • H01L31/02327Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/11Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor
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Abstract

A preparation method of side incident SOI base Si/SiGe HPT with a photonic crystal structure belongs to the technical field of semiconductors and comprises the following steps: preparing an SOI base Si/SiGe HPT epitaxial material on an SOI substrate, preparing a photonic crystal structure, etching to form a base region, a collector region table top, an epitaxial passivation layer, etching an electrode contact hole, and manufacturing a metal electrode. Compared with the traditional Si/SiGe HPT, the method has the following advantages: the absorption rate of the device to light is improved by trapping incident light in the device by utilizing the point defect and line defect characteristics of the photonic crystal, and meanwhile, the absorption length of the device to light is increased by adopting a side incident mode compared with a vertical incident mode to ensure that the thickness of the absorption layer is not changed, and the absorption rate of the device to light is also improved.

Description

Preparation method of side-incident SOI (silicon on insulator) based Si/SiGe HPT (hydrogen phosphide) with photonic crystal structure
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a side-incident SOI (silicon on insulator) based Si/SiGe HPT (silicon germanium) with a photonic crystal structure.
Background
With the further development of the information society and the arrival of the big data era, compared with the traditional electrical interconnection technology, the optical interconnection technology has many advantages in the aspects of transmission capacity, communication speed, signal delay, transmission distance, electric energy consumption and the like in the data transmission and processing links. It has become common knowledge to replace electrical interconnects with optical interconnects. Silicon-based optical interconnect technology is considered one of the most promising developments. As one of core devices of an optical interconnection system, the performance of a photoelectric detector also influences the performance of the whole system, and the conventional vertical incidence type Si/SiGe HPT has contradiction between high-efficiency absorption and high-speed operation because the thickness of an absorption layer is in direct proportion to the moving distance of a carrier.
Disclosure of Invention
In view of the defects of the prior art, the invention aims to provide a preparation method of a side incident type SOI base Si/SiGe HPT with a photonic crystal structure, which has both high-efficiency absorption and high-speed operation.
The invention provides a preparation method of a side-incident SOI (silicon on insulator) based Si/SiGe HPT (silicon oxygen transport/silicon germanium) with a photonic crystal structure, which has the advantages of high-efficiency absorption and high-speed work, and comprises the following steps:
(1) sequentially extending n-type Si secondary collector region, Si collector region and p-type Si on an SOI substrate x Ge 1-x Base region, polycrystalline Si emitter region.
(2) And manufacturing a photonic crystal structure.
(3) And etching the base region and the collector region mesa.
(4) And depositing an insulating layer.
(5) And etching the contact hole.
(6) And photoetching to manufacture metal electrodes to form ohmic contact.
Further, the p-type Si of step (1) x Ge 1-x The base region is Si 0.8 Ge 0.2 The base region is 50-100nm thick.
Further, the method for manufacturing the photonic structure in the step (2) includes electron beam exposure, nanoimprint lithography or laser direct writing.
Further, the etching method in the step (3) includes ICP.
Further, in the step (4), the insulating layer is SiO 2 Or Si 3 N 4
Further, the etching method in the step (5) is wet etching.
Further, the metal electrode in the step (6) is prepared by alignment, evaporation and annealing.
Further, in the step (6), the metal is Ti/Al/Ti/Au, and the metal electrode and the device form ohmic contact.
Compared with the prior art, the invention has the beneficial technical effects that:
the invention provides a preparation method of a side incident type SOI base Si/SiGe HPT with a photonic crystal structure, which has the following advantages compared with the traditional vertical incident type Si/SiGe HPT through the design of epitaxial materials and devices: the light trapping and slow light effect control light mode and light transmission are generated by utilizing the point defect and line defect characteristics of the photonic crystal, incident light is trapped in the device, the light absorption rate of the device is improved, and meanwhile, the light absorption length of the device to light is increased under the condition that the thickness of an absorption layer is not changed by adopting a side incident mode of light compared with a vertical incident mode, and the light absorption rate of the device to light is also improved. After the photonic crystal structure is added, the absorption of the device to light is increased by 30-35%, and the responsivity of the device is increased by more than 30%.
The invention provides a preparation method of side incident type SOI base Si/SiGe HPT with a photonic crystal structure, which gives consideration to efficient absorption and high-speed work, and has the advantages of simple preparation process, low cost, easy implementation and large-scale popularization.
Drawings
FIG. 1 is a schematic diagram of the epitaxial growth of Si subcollector region, Si collector region, Si on an SOI substrate according to the present invention x Ge 1-x And the epitaxial structure behind the base region and the polycrystalline Si emitter region is schematically shown.
FIG. 2 is a top view of a side-incident SOI-based Si/SiGe HPT having a photonic crystal structure in an embodiment.
FIG. 3 is a side view of a side-incident SOI-based Si/SiGe HPT having a photonic crystal structure in an embodiment. Fig. 4 is a perspective view of the structure of the present invention.
In the figure: 1-an SOI substrate; a 101-Si substrate; 102-SiO 2 A layer; 2-Si secondary collector region; 3-a Si collector region; 4-Si x Ge 1-x A base region; 5-a poly-Si emitter region; 6-a metal electrode; 601-collector region electrode; 602-base region electrodes; 603-emitter electrodes; 7-photonic crystal structure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art without any creative work based on the embodiments of the present invention belong to the protection scope of the present invention.
The invention will be further elucidated with reference to the drawings and examples.
The invention provides a preparation method of a side-incident SOI (silicon on insulator) based Si/SiGe HPT (silicon oxygen transport/silicon germanium) with a photonic crystal structure, which has the advantages of high-efficiency absorption and high-speed work, and comprises the following steps:
(1) on an SOI substrate 1(101-Si substrate; 102-SiO) 2 Layer) is sequentially extended with a Si sub-collector region 2, a Si collector region 3 and Si x Ge 1-x Base region 4, poly-Si emitter region 5.
(2) A photonic crystal structure 7 is fabricated.
(3) And etching the base region and the collector region mesa.
(4) And depositing an insulating layer.
(5) And etching the contact hole.
(6) And photoetching to manufacture a metal electrode 6 (601-collector region electrode; 602-base region electrode; 603-emitter region electrode) to form ohmic contact.
Example 1
The invention provides a preparation method of a side-incident SOI (silicon on insulator) based Si/SiGe HPT (silicon oxygen transport/silicon germanium) with a photonic crystal structure, which has the advantages of high-efficiency absorption and high-speed work, and comprises the following steps:
(1) selecting a 4-inch diameter (100) -face Si wafer with a thickness of about 150 μm, implanting oxygen ions into the Si wafer to form a highly concentrated oxygen-implanted layer, and then annealing at high temperature to react the implanted oxygen with silicon to form SiO 2 And finally, grinding and polishing the insulating layer to obtain the SOI substrate. Sequentially growing an n-type Si secondary collector region 2 and an n-type Si collector region 3 on an SOI silicon wafer by adopting low-pressure chemical vapor deposition (LPCVD), wherein the thicknesses are respectively 300nm and 600nm, and SiH 4 As a Si source, the growth temperature is 700 ℃; as serves As an n-type impurity source. Followed by growing p-type Si on the n-type Si collector region 3 by Reduced Pressure Chemical Vapor Deposition (RPCVD) 0.8 Ge 0.2 A base region 4 with a thickness of 100nm and a reaction source of SiH 4 And GeH 4 The growth temperature is 600 ℃, and B is used as a p-type doped impurity source. Finally, Low Pressure Chemical Vapor Deposition (LPCVD) is adopted to form p-type Si 0.8 Ge 0.2 An n-type polysilicon emitter region 5 with the thickness of 200nm and SiH is grown on the base region 4 4 As a source of SiThe long temperature is 700 ℃; as serves As an n-type impurity source.
(2) And performing electron beam Exposure (EBL) on the surface of the polysilicon emitting region 5, and etching periodically arranged air columns by adopting dry etching (ICP), wherein the aperture size is 200nm, the aperture depth is 1.2um, and the period is 850nm to form a two-dimensional photonic crystal structure 7. Etching conditions are as follows: source power 810W, radio frequency power 10W, etching gas SF 6 Flow rate of 50cm 3 Min etching passivation gas C 4 F 8 Flow rate of 110cm 3 Min, etching time 40 seconds.
(3) And photoetching is carried out on the basis of the structure, and a base region mesa is etched by adopting dry etching (ICP). The etching depth is 200 nm. Etching conditions are as follows: source power 450W, RF Power 10W, etching gas SF 6 Flow rate of 50cm 3 Min etching passivation gas C 4 F 8 Flow rate of 110cm 3 Min, etching time 20 seconds. And photoetching is carried out, and the collector region mesa is etched by adopting dry etching (ICP). The etching depth was 1.2. mu.m. Etching conditions are as follows: source power 810W, radio frequency power 10W, etching gas SF 6 Flow rate of 50cm 3 Min etching passivation gas C 4 F 8 Flow rate of 110cm 3 Min, etching time 40 seconds.
(4) Depositing a layer of SiO on the surface of the structure in the step (3) by adopting PECVD 2 The film serves as an insulating layer. SiO 2 2 The film thickness is 100 nm.
(5) In the above SiO 2 And photoetching the film and etching a contact hole by adopting wet etching. Etching solution: BOE solution was prepared from 49% aqueous HF: 40% NH 4 F aqueous solution 1: 6 (volume ratio) are mixed. The etching time was 30 s.
(6) Photoetching is carried out on the basis of the structure in the step (5), an electron beam evaporation is adopted to deposit a Ti/Al/Ti/Au electrode 6 to form ohmic contact with the device, and the thickness of each layer of metal is as follows: ti (50nm)/Al (150nm)/Ti (50nm)/Au (100nm), deposition conditions: the voltage is 6kv, the electron beam current is 6mA, and the temperature is 180 ℃. And finally carrying out rapid thermal annealing for 8s at the temperature of 450 ℃. Finally, the side incident type SOI base Si/SiGe HPT with the photonic crystal structure is obtained.
Example 2
The invention provides a preparation method of a side-incident SOI (silicon on insulator) based Si/SiGe HPT (silicon oxygen transport/silicon germanium) with a photonic crystal structure, which has the advantages of high-efficiency absorption and high-speed work, and comprises the following steps:
(1) selecting 2 Si wafers with the (100) surfaces of 4 inches in diameter and the thickness of about 100um, thermally oxidizing, bonding and annealing the two wafers, and finally grinding and polishing to about 15um to obtain the SOI substrate. Sequentially growing an n-type Si secondary collector region 2 and an n-type Si collector region 3 on an SOI silicon wafer by adopting low-pressure chemical vapor deposition (LPCVD), wherein the thicknesses are respectively 300nm and 600nm, and SiH 4 As a Si source, the growth temperature is 700 ℃; as serves As an n-type impurity source. Followed by growing p-type Si on the n-type Si collector region 3 by Reduced Pressure Chemical Vapor Deposition (RPCVD) 0.8 Ge 0.2 A base region 4 with a thickness of 100nm and a reaction source of SiH 4 And GeH 4 The growth temperature is 600 ℃, and B is used as a p-type doped impurity source. Finally, Low Pressure Chemical Vapor Deposition (LPCVD) is adopted to form p-type Si 0.8 Ge 0.2 An n-type polysilicon emitter region 5 with the thickness of 200nm and SiH is grown on the base region 4 4 As a Si source, the growth temperature is 700 ℃; as serves As an n-type impurity source.
(2) And performing electron beam Exposure (EBL) on the surface of the polysilicon emission region 5, and etching periodically arranged air columns by adopting dry etching (ICP), wherein the aperture size is 200nm, the aperture depth is 1.2um, and the period is 850nm to form a two-dimensional photonic crystal structure 7. . Etching conditions are as follows: source power 810W, RF power 10W, etching gas SF 6 Flow rate of 50cm 3 Min, etching passivation gas C 4 F 8 Flow rate of 110cm 3 Min, etching time 40 seconds.
(3) And photoetching is carried out on the basis of the structure, and a base region mesa is etched by adopting dry etching (ICP). The etching depth is 200 nm. Etching conditions are as follows: source power 450W, RF Power 10W, etching gas SF 6 Flow rate of 50cm 3 Min etching passivation gas C 4 F 8 Flow rate of 110cm 3 Min, etching time 20 seconds. And photoetching is carried out, and the collector region mesa is etched by adopting dry etching (ICP). The etching depth was 1.2. mu.m. Etching conditions are as follows: source power 810W, radio frequency power 10W, etching gas SF 6 Flow rate of 50cm 3 Min etching passivation gas C 4 F 8 Flow rate of110cm 3 Min, etching time 40 seconds.
(4) Depositing a layer of SiO on the surface of the structure in the step (3) by adopting PECVD 2 The film serves as an insulating layer. SiO 2 2 The film thickness is 100 nm.
(5) In the above SiO 2 And photoetching the film and etching a contact hole by adopting wet etching. Etching solution: BOE solution was prepared from 49% aqueous HF: 40% aqueous NH4F solution ═ 1: 6 (volume ratio) are mixed. The etching time was 30 s.
(6) Photoetching is carried out on the basis of the structure in the step (5), an electron beam evaporation is adopted to deposit a Ti/Al/Ti/Au electrode 6 to form ohmic contact with the device, and the thickness of each layer of metal is as follows: ti (50nm)/Al (150nm)/Ti (50nm)/Au (100nm), deposition conditions: the voltage is 6kv, the electron beam current is 6mA, and the temperature is 180 ℃. And finally carrying out rapid thermal annealing for 8s at the temperature of 450 ℃. Finally, the side incident type SOI base Si/SiGe HPT with the photonic crystal structure is obtained.
While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.

Claims (7)

1. A preparation method of a side incident type SOI-based Si/SiGe HPT with a photonic crystal structure comprises the following steps:
(1) sequentially epitaxially growing an n-type Si sub-collector region, an n-type Si collector region and p-type Si on a p-type SOI substrate x Ge 1-x A base region and an n-type polycrystalline Si emitter region;
(2) active silicon regions are formed from the n-type Si secondary collector region to the n-type polycrystalline Si emitter region, and a photonic crystal structure is manufactured in the whole active silicon region; a photonic crystal structure comprising a periodic arrangement of air columns (701) and a Si medium (702); the aperture d of the air column is 800nm and the period L of the photonic crystal structure is 2000nm and 250-;
(3) etching the base region and the collector region mesa;
(4) depositing an insulating layer;
(5) etching a contact hole;
(6) photoetching and manufacturing a metal electrode to form ohmic contact;
the active silicon area after the photonic crystal structure is manufactured and the SOI substrate form a waveguide structure to control a light path, and the width of the waveguide structure is determined by the following structure:
Figure FDA0003765366640000011
wherein: λ is the incident light wavelength, h is the waveguide height, and e is a natural constant.
2. The method of claim 1, wherein: the thickness range of the n-type polycrystalline Si emitting region in the step (1) is 100-200nm, and the doping concentration range is 5 multiplied by 10 19 cm -3 -2×10 20 cm -3 (ii) a p-type Si x Ge 1-x X in the base region is in the range of 0.16-0.35, Si x Ge 1-x The thickness range of the base region is 50-100nm, and the doping concentration range is 8 multiplied by 10 17 cm -3 -5×10 18 cm -3
3. The method of claim 1, wherein: the method for manufacturing the photonic crystal structure in the step (2) is electron beam exposure, nano imprinting or laser direct writing.
4. The method of claim 1, wherein: the etching method in the step (3) is ICP, and the etching conditions are as follows: source power of 450- 6 The flow rate is 50-80cm 3 Min etching passivation gas C 4 F 8 Flow rate of 110- 3 /min。
5. The method of claim 1, wherein: in the step (4), the passivation and insulation layer is SiO 2 Or Si 3 N 4 The growth mode is PECVD, and the film thickness is 100nm-200 nm.
6. The method of claim 1, wherein: and (5) performing wet etching, wherein the etching solution is BOE solution, and the etching time is 30-35 s.
7. The method of claim 1, wherein: in the step (6), the metal electrode is prepared by alignment, evaporation and thermal annealing, wherein the evaporation mode is as follows: electron beam evaporation; the thermal annealing temperature is 400-1000 ℃, and the time is 5-10 s.
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CN102696114A (en) * 2010-01-07 2012-09-26 夏普株式会社 Photoelectric transducer
CN105556680A (en) * 2013-05-22 2016-05-04 王士原 Microstructure enhanced absorption photosensitive devices
CN107946383A (en) * 2017-11-23 2018-04-20 北京工业大学 A kind of silica-based waveguides type photistor detector with traveling wave electrode
CN110047969A (en) * 2019-05-06 2019-07-23 北京工业大学 A kind of SOI base SiGe double-heterojunctiophototransistor phototransistor detector

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016081476A1 (en) * 2014-11-18 2016-05-26 Shih-Yuan Wang Microstructure enhanced absorption photosensitive devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102696114A (en) * 2010-01-07 2012-09-26 夏普株式会社 Photoelectric transducer
CN105556680A (en) * 2013-05-22 2016-05-04 王士原 Microstructure enhanced absorption photosensitive devices
CN107946383A (en) * 2017-11-23 2018-04-20 北京工业大学 A kind of silica-based waveguides type photistor detector with traveling wave electrode
CN110047969A (en) * 2019-05-06 2019-07-23 北京工业大学 A kind of SOI base SiGe double-heterojunctiophototransistor phototransistor detector

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