CN112530932A

CN112530932A - Electrostatic protection structure

Info

Publication number: CN112530932A
Application number: CN201910877029.0A
Authority: CN
Inventors: 雷玮; 李宏伟; 程惠娟
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-09-17
Filing date: 2019-09-17
Publication date: 2021-03-19

Abstract

An electrostatic protection structure comprising: a plurality of voltage domain circuits, each of the voltage domain circuits including at least a ground level bus; the conducting circuit is connected with the ground level buses of the adjacent voltage domain circuits, the conducting circuit at least comprises a control end, and the control end is used for controlling the conducting circuit to establish a passage between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses, so that the potential difference on the ground level buses can be timely reduced, the clamping circuit failure or overlong reaction time caused by overlarge potential of the floating ground level buses is avoided, and the protection performance of the electrostatic protection structure is improved.

Description

Electrostatic protection structure

Technical Field

The invention relates to the field of semiconductor integrated circuits, in particular to an electrostatic protection structure.

Background

In Integrated Circuits (Integrated Circuits), the influence of Electrostatic discharge (ESD) on the reliability of a chip is not negligible, and especially at present when deep submicron and nanometer technologies are commonly applied, the destructive influence of Electrostatic discharge such as external environment, human body, machinery, radiation field and the like on an IC is more significant, and a great deal of research and practice is made on ESD protection in the design and manufacturing process of the IC in the industry.

In the manufacture and application of integrated circuit chips, with the continuous improvement of super-large-scale integrated circuit process technology, the current CMOS integrated circuit manufacturing technology has entered the deep submicron and nanometer stage, the size of MOS devices has been continuously reduced, the thickness of gate oxide layer has been thinner and thinner, the voltage endurance capability of MOS devices has been continuously reduced, and the damage of electrostatic discharge to integrated circuits has become more and more obvious. Therefore, ESD protection of integrated circuits is also becoming important.

When designing a large SOC chip with multiple voltage domains and multiple functional modules, global ESD protection is required for the chip. Most conventionally, each power line of different voltage domains is isolated, and adjacent ground lines are connected by one or more stages of back-to-back diodes (diodes) to drain ESD current. This structure is typically designed with I/O libraries, called Power cut cells.

However, the Power cut cell method is adopted to perform the global ESD protection of the chip, and the protection performance is still to be improved.

Disclosure of Invention

The invention provides an electrostatic protection structure, which improves the electrostatic protection performance of a device.

To solve the above problems, the present invention provides an electrostatic protection structure, including: a plurality of voltage domain circuits, each of the voltage domain circuits including at least a ground level bus; the conducting circuit is connected with ground level buses of adjacent voltage domain circuits and at least comprises a control end, and the control end controls the conducting circuit to establish a path between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses.

Preferably, the adjacent ground level buses include a first ground level bus and a second ground level bus;

the conducting circuit comprises a first conducting unit and a second conducting unit, wherein the first conducting unit is used for establishing a path from the first ground level bus to the second ground level bus, and the second conducting unit is used for establishing a path from the second ground level bus to the first ground level bus.

Preferably, the first conducting unit and the second conducting unit are both MOS devices.

Preferably, the control terminal includes a first control terminal located in the first conducting unit and a second control terminal located in the second conducting unit;

the first conducting unit is a first PMOS transistor, the grid and the source of the first PMOS transistor are connected with the second ground level bus, the drain of the first PMOS transistor is connected with the first ground level bus, and the grid of the first PMOS transistor is used as the first control end;

the second conduction unit is a second PMOS transistor, a gate and a source of the second PMOS transistor are connected to the first ground level bus, and a drain of the second PMOS transistor is connected to the second ground level bus, wherein the gate of the second PMOS transistor serves as the second control terminal.

Preferably, the first PMOS transistor is located on a semiconductor substrate, and includes:

a first n-well region located within the semiconductor substrate;

a first PMOS device unit and a first n-type doped region located in the first n-well region;

the first PMOS device unit comprises a grid electrode positioned on the first n-type well region, a source region and a drain region positioned on two sides of the grid electrode, a source electrode connected with the source region and a drain electrode connected with the drain region;

the first n-type doped region is located on one side of the source region of the first PMOS device unit, the first n-type doped region and the drain region of the first PMOS device form a parasitic diode, and the first n-type doped region is connected with the source electrode of the first PMOS device.

Preferably, the second PMOS transistor is located on the same semiconductor substrate as the first PMOS transistor, and includes:

a second n-well region located within the semiconductor substrate;

a second PMOS device unit and a second n-type doped region located in the second n-well region;

the second PMOS device unit comprises a grid electrode positioned on the second n-type well region, a source region and a drain region positioned on two sides of the grid electrode, a source electrode connected with the source region and a drain electrode connected with the drain region;

the second n-type doped region is located on one side of the source region of the second PMOS device unit, the second n-type doped region and the drain region of the second PMOS device form a parasitic diode, and the second n-type doped region is connected with the source electrode of the second PMOS device.

Preferably, the number of the first PMOS device units in the first PMOS transistor is plural, and the plural first PMOS device units are arranged in the first n well region in an array manner; the number of the second PMOS device units in the second PMOS transistor is multiple, and the second PMOS device units are arranged in the second n well region in an array mode.

Preferably, the ground level bus includes a plurality of ground level lines, and one ground level line connects a row of the first PMOS device unit and/or the second PMOS device unit.

Preferably, the first conducting unit is a first NMOS transistor, a gate and a source of the first NMOS transistor are connected to the first ground level bus, and a drain of the first NMOS transistor is connected to the second ground level bus, where a gate of the first NMOS transistor is used as a first control terminal;

the second conducting unit is a second NMOS transistor, a gate and a source of the second NMOS transistor are connected to the second ground level bus, and a drain of the second NMOS transistor is connected to the first ground level bus, wherein the gate of the second NMOS transistor serves as a second control terminal.

Preferably, the first NMOS transistor is located on a semiconductor substrate, and includes:

a first p-well region located within the semiconductor substrate, a first isolation layer being provided between the first p-well region and the semiconductor substrate;

a first NMOS device unit and a first p-type doped region located in the first p-well region;

the first NMOS device unit comprises a grid electrode positioned on the first p-type well region, a source region and a drain region positioned on two sides of the grid electrode, a source electrode connected with the source region and a drain electrode connected with the drain region;

the first p-type doped region is located on one side of the source region of the first NMOS device unit, the first p-type doped region and the drain region of the first NMOS device form a parasitic diode, and the first p-type doped region is connected with the source electrode of the first NMOS device.

Preferably, the second NMOS transistor is located on the same semiconductor substrate as the first NMOS transistor, and includes:

a second p-well region located within the semiconductor substrate, a second isolation layer being provided between the second p-well region and the semiconductor substrate;

a second NMOS device unit and a second p-type doped region located in the second p-well region;

the second NMOS device unit comprises a grid electrode positioned on the second p-type well region, a source region and a drain region positioned on two sides of the grid electrode, a source electrode connected with the source region and a drain electrode connected with the drain region;

the second p-type doped region is located on one side of the source region of the second NMOS device unit, the second p-type doped region and the drain region of the second NMOS device form a parasitic diode, and the second p-type doped region is connected with the source electrode of the second NMOS device.

Preferably, the number of the first NMOS device units in the first NMOS transistor is multiple, and multiple first NMOS device units are arranged in the first p-well region in an array manner; the number of the second NMOS device units in the second NMOS transistor is multiple, and the second NMOS device units are arranged in the second p-well region in an array mode.

Preferably, the ground level bus includes a plurality of ground level lines, and one ground level line connects a row of the first NMOS device cells and/or the second NMOS device cells.

Preferably, the voltage domain circuit includes a power bus and a clamp circuit connecting the power bus and the ground level bus.

Preferably, the voltage domain circuit further comprises a voltage domain operating circuit, the voltage domain operating circuit being powered by the power bus.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the embodiment of the invention, the conduction circuit is arranged between the adjacent voltage domain circuits and at least comprises the control end, and the control end is used for establishing a channel between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses, so that the potential difference on the ground level buses can be timely reduced, the clamping circuit failure or overlong reaction time caused by overlarge potential of the floating ground level buses is avoided, and the protection performance of the electrostatic protection structure is improved.

Drawings

FIG. 1 is a diagram of a Power cut cell chip global ESD protection;

fig. 2 is a schematic structural diagram of an electrostatic protection structure according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a voltage domain circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a conducting circuit according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a turn-on circuit according to an embodiment of the present invention;

FIG. 6 is a block diagram of a first PMOS transistor and a second PMOS transistor according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the connection of the horizontal lines to the PMOS device units according to the embodiment of the invention;

FIG. 8 is a graph of performance parameters of the ESD protection structure of FIG. 1 when discharging ESD current;

FIG. 9 is a graph of performance parameters for an embodiment of the present invention when discharging ESD current;

FIG. 10 is a circuit diagram of a turn-on circuit according to another embodiment of the present invention;

FIG. 11 is a diagram illustrating the structure of a first NMOS transistor and a second NMOS transistor according to another embodiment of the present invention;

FIG. 12 is a schematic diagram of the connection of a horizontal line and an NMOS device unit according to another embodiment of the present invention;

fig. 13 is a schematic diagram of a clamp circuit according to an embodiment of the invention.

Detailed Description

As known from the background art, the conventional electrostatic protection structure has poor protection performance. The reason why the protection performance of the electrostatic protection structure needs to be improved is analyzed in combination with an electrostatic protection structure.

Referring to fig. 1, the Power cut cell chip global ESD protection includes a voltage Domain circuit (Domain)11 and a voltage Domain circuit 12, wherein the voltage Domain circuit 11 includes a Power bus VDD1, a ground level bus VSS1, and a first Clamp circuit (Clamp)13 and a first internal operating circuit (Inner Circuits)14 connected between the Power bus VDD1 and the ground level bus VSS 1; the voltage domain circuit 12 includes a power bus VDD2, a ground level bus VSS2, a second clamp circuit 15 and a second internal operation circuit 16 connected between the power bus VDD2 and the ground level bus VSS 2. The ground level bus VSS2 is a ground voltage power supply, and a multi-stage conduction circuit 17 connected by back-to-back diodes is provided between the voltage domain circuit 11 and the voltage domain circuit 12.

It can be seen that with this configuration of ESD protection, not all ground level buses are grounded, and the floating ground level bus VSS1 needs to drain ESD current via the ground level bus VSS2 of the ground voltage power supply, i.e., the drain path a shown by the dashed arrow in fig. 1. However, since the diode has a certain on-resistance, the floating ground level bus VSS1 has a large potential difference during ESD transient, and if the potential difference reaches a certain level, it is easy to cause the clamp circuit connecting these ground level buses to fail or to have a too long reaction time, so that the ESD current is released through the internal operating circuit between the voltage domains, i.e. the release path B shown by the dotted arrow in fig. 1, thereby causing the damage of the internal operating circuit.

In a large SOC chip with multiple voltage domains and multiple functional modules, there are many voltage domains and many corresponding cascaded diodes, which may easily cause an excessive potential of a floating ground level bus, so that a clamp circuit connecting the ground level buses fails or has an excessively long response time, and finally, ESD current is released through an internal working circuit between the voltage domains, resulting in damage to the internal working circuit.

In order to solve the technical problem, an embodiment of the present invention provides an electrostatic protection structure, including: a plurality of voltage domain circuits, each of the voltage domain circuits including at least a ground level bus; and the conducting circuit is connected with the ground level buses of the adjacent voltage domain circuits and at least comprises a control end, and the control end is used for establishing a path between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 2, a schematic structural diagram of an electrostatic protection structure according to an embodiment of the present invention is shown, where the electrostatic protection structure includes: a plurality of voltage domain circuits 1 (only two shown in the figure), each of which comprises at least a ground level bus 2; and the conduction circuit 3 is connected with the ground level buses of the adjacent voltage domain circuits, the conduction circuit at least comprises a control end, and the control end controls the conduction circuit 2 to establish a path between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses.

The voltage domain circuit 1 is a circuit for implementing a specific function, wherein the plurality of voltage domain circuits may be a plurality of circuits for implementing the same function or a plurality of circuits for implementing different functions. Referring to fig. 3, which is a schematic structural diagram of voltage domain circuits according to an embodiment of the present invention, each voltage domain circuit 1 is provided with a ground level bus 2, a power supply bus 5, a clamp circuit 6 connecting the power supply bus 5 and the ground level bus 2, and a voltage domain operating circuit 7 powered by the power supply bus 5.

The clamping circuit 6 is used for discharging the ESD current of the voltage domain circuit 1 to the ground level bus 2, and the voltage domain working circuit 7 is used for implementing a corresponding function. The ground level bus in at least one of the plurality of voltage domain circuits is grounded to drain ESD current in the corresponding voltage domain circuit.

Referring to fig. 2 in combination, the ground level buses 2 of adjacent voltage domain circuits are connected by a pass-through circuit 3. In this embodiment, the conducting circuit 3 at least includes a control end, and when the control end detects the potential difference of the adjacent ground level buses, the control end controls the conducting circuit 3 to establish a path between the adjacent ground level buses, so as to timely and effectively reduce the potential difference on the ground level buses, avoid the clamp circuit failure or overlong reaction time caused by the overlarge potential of the floating ground level buses, and improve the protection performance of the electrostatic protection structure.

Specifically, referring to fig. 4, it is a schematic structural diagram of a conducting circuit according to an embodiment of the present invention, where the adjacent ground level buses include a first ground level bus and a second ground level bus, specifically, one of the adjacent ground level buses is a first ground level bus VSS1, and another of the adjacent ground level buses is a second ground level bus VSS 2; the conducting circuit 3 includes a first conducting unit 31 and a second conducting unit 32, the control terminals include a first control terminal 41 located in the first conducting unit 31 and a second control terminal 42 located in the second conducting unit 32, the first control terminal 41 is used for controlling the first conducting unit 31 to establish a path from the first ground level bus VSS1 to the second ground level bus VSS2, and the second control terminal 42 is used for controlling the second conducting unit 32 to establish a path from the second ground level bus VSS2 to the first ground level bus VSS 1.

In the ground level buses, the direction of the potential difference between adjacent ground level buses is uncertain, taking the example that the potential difference between the current flowing from the first ground level bus VSS1 to the second ground level bus VSS2 is a positive potential difference, and the potential difference between the current flowing from the second ground level bus VSS2 to the first ground level bus VSS1 is a negative potential difference, the potential difference between adjacent ground level buses may be a positive potential difference or a negative potential difference, and therefore, in this embodiment, the conduction circuit includes the first conduction unit 31 for establishing a path from the first ground level bus VSS1 to the second ground level bus VSS2, and the second conduction unit 32 for establishing a path from the second ground level bus VSS2 to the first ground level bus VSS1, and the control of the first conduction unit 31 and the second conduction unit 32 is realized according to different directions of the potential differences.

Specifically, when the first control terminal 41 detects a positive potential difference, the first conducting unit 31 is controlled to establish the path from the first ground level bus VSS1 to the second ground level bus VSS2, and when the second control terminal 42 detects a negative potential difference, the second conducting unit 32 is controlled to establish the path from the second ground level bus VSS2 to the first ground level bus VSS 1.

In an alternative example, the first and second turn-on

units

31 and 32 are MOS devices. Because the MOS device can be quickly conducted in an ESD transient state, and the conducting resistance is very small (nearly 0), the potential on the ground level bus can be timely reduced.

Referring to fig. 5, which is a schematic circuit structure diagram of a turn-on circuit according to an embodiment of the present invention, the first turn-on unit 31 is a first PMOS transistor P1, a gate of the first PMOS transistor P1 is used as the first control terminal 41, a source of the first PMOS transistor P1 is connected to the second ground level bus VSS2, and a drain of the first PMOS transistor P1 is connected to the first ground level bus VSS 1; the second conducting unit 32 is a second PMOS transistor P2, the gate of the second PMOS transistor P2 is the second control terminal 42, the source is connected to the first ground level bus VSS1, and the drain is connected to the second ground level bus VSS 2.

The gate of the first PMOS transistor P1 is used as the first control terminal 41, and when a positive potential difference is detected, the first PMOS transistor P1 is turned on, so as to establish a path from the first ground level bus VSS1 to the second ground level bus VSS2, so that the potential on the first ground level bus VSS1 is rapidly reduced, thereby avoiding the clamp circuit in the voltage domain circuit where the first ground level bus VSS1 is located from failing or having too long reaction time due to the excessively large potential of the first ground level bus VSS1, and improving the protection performance of the electrostatic protection structure.

Correspondingly, the gate of the second PMOS transistor P2 is used as the second control terminal 42, and when a negative potential difference is detected, the second PMOS transistor P2 is turned on, so as to establish a path from the second ground level bus VSS2 to the first ground level bus VSS1, so that the potential on the second ground level bus VSS2 is rapidly reduced, thereby avoiding the clamp circuit in the voltage domain circuit where the second ground level bus VSS2 is located from failing or having too long reaction time due to the excessively large potential of the second ground level bus VSS2, and improving the protection performance of the electrostatic protection structure.

Referring to fig. 6, a block diagram of a first PMOS transistor and a second PMOS transistor according to an embodiment of the present invention is shown, the first PMOS transistor being located on a semiconductor substrate 100.

Specifically, the first PMOS transistor includes: a first n-well region 110 located within the semiconductor substrate; a first PMOS device cell 120 and a first n-type doped region 130 located within the first n-well region 110; the first PMOS device unit 120 includes a gate 121 located on the first n-type well region 110, a source region 122 and a drain region 123 located at two sides of the gate, and a source 124 connected to the source region 122 and a drain 125 connected to the drain region 123; the first n-type doped region 130 is located at one side of the source region 122 of the first PMOS device unit 120, the first n-type doped region 130 and the drain region 123 of the first PMOS device constitute a parasitic diode, and the first n-type doped region 130 is connected to the source 124 of the first PMOS device.

The parasitic diode formed by the first n-type doped region 130 and the drain region 123 of the first PMOS device can utilize the channel of the MOS and the parasitic diode to work simultaneously, so as to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

In this embodiment, the second PMOS transistor is located on the same semiconductor substrate as the first PMOS transistor.

Specifically, the second PMOS transistor includes: a second n-well region 210 located within the semiconductor substrate; a second PMOS device cell 220 and a second n-type doped region 230 located within the second n-well region 210; the second PMOS device unit 220 includes a gate 221 located on the second n-type well region 210, a source region 222 and a drain region 223 located at two sides of the gate, and a source 224 connected to the source region 222 and a drain 225 connected to the drain region 223; the second n-type doped region 230 is located at one side of the source region 222 of the second PMOS device unit 220, the second n-type doped region 230 and the drain region 223 of the second PMOS device form a parasitic diode, and the second n-type doped region 230 is connected to the source 224 of the second PMOS device.

Similarly, the parasitic diode formed by the second n-type doped region 230 and the drain region 223 of the second PMOS device can utilize the channel of the MOS to work simultaneously with the parasitic diode, so as to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

In this embodiment, the number of the first PMOS device units in the first PMOS transistor is plural, and a plurality of the first PMOS device units are arranged in the first n well region in an array; the number of the second PMOS device units in the second PMOS transistor is multiple, and the second PMOS device units are arranged in the second n well region in an array mode.

The first PMOS device unit and the second PMOS device unit which are arranged in an array improve the perimeter of a parasitic diode of the MOS tube in unit area, can further improve the effective perimeter of an ESD passage, and improve the discharge capacity of ESD current of the device. In addition, the perimeter of the active region of the MOS transistor is increased, and the drain control capability of the MOS transistor is improved.

In this embodiment, the ground level bus includes a plurality of ground level lines, one ground level line connecting a row of the first PMOS device unit and/or the second PMOS device unit.

Fig. 7 is a schematic diagram of the connection between the ground plane and the PMOS device units according to the embodiment of the invention, and the connection between the ground plane and the first PMOS device unit 120 in the first PMOS transistor is schematically illustrated by taking the example that the first PMOS transistor includes 6 first PMOS device units 120. Specifically, the first ground level bus includes a plurality of first ground level lines VSS11, the second ground level bus includes a plurality of first ground level lines VSS21, one first ground level line VSS11 connects the drains (not shown) of a row of first PMOS device cells 120, one second ground level line VSS21 connects the sources and gates (not shown) of a row of first PMOS device cells 120 and the first n-type doped region 130.

The first PMOS transistor and the second PMOS transistor can be manufactured on one chip, the first PMOS transistor and the second PMOS transistor can be transversely arranged on the chip or vertically arranged on the chip, and when the first PMOS transistor and the second PMOS transistor are transversely arranged, contact points corresponding to the transistors can be arranged in a unified mode, so that a row of ground horizontal lines are connected with the first PMOS transistor and the second PMOS transistor at the same time. When the first PMOS transistor and the second PMOS transistor are vertically arranged, one ground electric bisector can be only connected with one row of first PMOS device units or only connected with one row of second PMOS device units, so that the device structure can be simplified, and the process cost of the device can be reduced.

Referring to fig. 8 and 9, fig. 8 is a performance parameter diagram of the ESD protection structure shown in fig. 1 when discharging ESD current, and fig. 9 is a performance parameter diagram of the embodiment when discharging ESD current. Wherein Vesd is the ESD voltage, Vss1 is the potential on the first ground bus, Icmp is the ESD current discharged by the clamp circuit, and Ic is the sum of the ESD current discharged by the clamp circuit.

It can be seen that, in the electrostatic protection structure in this embodiment, when the ESD current is discharged, the potential on the floating ground level bus Vss1 is 1.1V, which is much smaller than 2.0V in the structure of fig. 1, and the ESD current Icmp discharged by the clamp circuit is 1.6A, which is much larger than 54.7mA in the structure of fig. 1.

Optionally, referring to fig. 10, a schematic circuit structure diagram of a turn-on circuit according to another embodiment of the present invention is shown; the first conducting unit 31 is a first NMOS transistor N1, the gate of the first NMOS transistor N1 is the first control terminal 41, the source is connected to the first ground level bus VSS1, and the drain is connected to the second ground level bus VSS 2;

the second pass unit 32 is a second NMOS transistor N2, the gate of the second NMOS transistor N2 is used as the second control terminal 42, the source is connected to the second ground level bus VSS2, and the drain is connected to the first ground level bus VSS 1.

The gate of the first NMOS transistor N1 is used as the first control terminal 41, and when a positive potential difference is detected, the first NMOS transistor N1 is turned on, so as to establish a path from the first ground level bus VSS1 to the second ground level bus VSS2, so that the potential on the first ground level bus VSS1 is rapidly reduced, thereby avoiding a clamp circuit in a voltage domain circuit where the first ground level bus VSS1 is located from failing or having too long reaction time due to an excessively large potential of the first ground level bus VSS1, and improving the protection performance of the electrostatic protection structure.

Correspondingly, the gate of the second NMOS transistor N2 is used as the second control terminal 42, and when a negative potential difference is detected, the second NMOS transistor N2 is turned on, so as to establish a path from the second ground level bus VSS2 to the first ground level bus VSS1, so that the potential on the second ground level bus VSS2 is rapidly reduced, thereby avoiding the failure or the too long reaction time of the clamp circuit in the voltage domain circuit where the second ground level bus VSS2 is located, which is caused by the too large potential of the second ground level bus VSS2, and improving the protection performance of the electrostatic protection structure.

Referring to fig. 11, there is shown a structural diagram of a first NMOS transistor and a second NMOS transistor in the present embodiment, the first NMOS transistor being located on a semiconductor substrate 200.

Specifically, the first NMOS transistor includes: a first p-well region 310 within the semiconductor substrate with a first isolation layer 340 therebetween; a first NMOS device cell 320 and a first p-type doped region 330 located within the first p-well region 310; the first NMOS device unit 320 includes a gate 321 located on the first p-type well region 310, a source region 322 and a drain region 323 located at two sides of the gate, a source 324 connected to the source region 322, and a drain 325 connected to the drain region 323; the first p-type doped region 330 is located at one side of the source region 322 of the first NMOS device unit 320, the first p-type doped region 330 and the drain region 323 of the first NMOS device constitute a parasitic diode, and the first p-type doped region 330 is connected to the source 324 of the first NMOS device.

The parasitic diode formed by the first p-type doped region 330 and the drain region 323 of the first NMOS device can utilize the channel of the MOS to work simultaneously with the parasitic diode, so as to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

In this embodiment, the second NMOS transistor is located on the same semiconductor substrate as the first NMOS transistor.

Specifically, the second NMOS transistor includes: a second p-well region 410 within the semiconductor substrate with a second isolation layer 440 therebetween; a second NMOS device cell 420 and a second p-type doped region 430 located within the second p-well region 410; the second NMOS device unit 420 includes a gate 421 located on the second p-type well region 410, a source region 422 and a drain region 423 located at two sides of the gate, and a source 424 connected to the source region 422 and a drain 425 connected to the drain region 423; the second p-type doped region 430 is located at one side of the source region 422 of the second NMOS device unit 420, the second p-type doped region 430 and the drain region 423 of the second NMOS device constitute a parasitic diode, and the second p-type doped region 430 is connected to the source 424 of the second NMOS device.

Similarly, the parasitic diode formed by the second p-type doped region 430 and the drain region 423 of the second NMOS device can utilize the channel of the MOS to work simultaneously with the parasitic diode, so as to quickly reduce the potential difference between different ground lines, thereby reducing the risk of cross-region ESD protection.

In this embodiment, the number of the first NMOS device units in the first NMOS transistor is plural, and the plural first NMOS device units are arranged in the first p-well region in an array manner; the number of the second NMOS device units in the second NMOS transistor is multiple, and the second NMOS device units are arranged in the second p-well region in an array mode.

The first NMOS device unit and the second NMOS device unit which are arranged in an array improve the perimeter of a parasitic diode of the MOS tube in unit area, and can further effectively pass ESD current and improve ESD protection. In addition, the perimeter of the active region of the MOS tube is increased, so that the effective perimeter of ESD current discharge is effectively increased, and the discharge capacity of the ESD current of the device is improved.

In this embodiment, the ground level bus includes a plurality of ground level lines, and one ground level line connects a row of the first NMOS device cells and/or the second NMOS device cells.

Fig. 12 is a schematic diagram of the connection between the horizontal lines and the NMOS device units according to the embodiment of the present invention. The first ground level bus line includes a plurality of first ground level lines VSS11, the second ground level bus line includes a plurality of first ground level lines VSS21, one first ground level line VSS11 connects the drains (not shown) of a row of first PMOS device cells 120, and one second ground level line VSS21 connects the sources and gates (not shown) of a row of first PMOS device cells 120.

The first NMOS transistor and the second NMOS transistor can be arranged horizontally or vertically, and when the first NMOS transistor and the second NMOS transistor are arranged horizontally, contact points corresponding to the transistors can be arranged in a coordinated manner, so that a line of ground horizontal lines are connected with the first NMOS transistor and the second NMOS transistor simultaneously. When the first NMOS transistor and the second NMOS transistor are vertically arranged, one ground level line is connected with one row of the first NMOS device units or the second NMOS device units, so that the structure of the device can be simplified, and the process cost of the device can be reduced.

In an alternative example, referring to fig. 13, a schematic diagram of a clamp circuit according to an embodiment of the present invention is shown, where the clamp circuit structure may be disposed in any one of a plurality of voltage domain circuits. Specifically, the clamp circuit includes: a first resistor R1, a first capacitor C1, a third PMOS transistor P3, a third NMOS transistor N3, and a fourth NMOS transistor N4;

one end of the first resistor R1 is connected to the power bus VDD, and the other end is connected to the first capacitor C1, and is connected to the ground bus VSS through the first capacitor C1; the source of the third PMOS transistor P3 is connected to the power bus VDD, the drain is connected to the drain of the third NMOS transistor N3, and the gate is connected to the gate of the third NMOS transistor N3 and the other end of the first resistor R1; a source of the third NMOS transistor N3 is connected to the first ground level bus VSS; the source of the fourth NMOS transistor N4 is connected to the power bus VDD, the drain is connected to the first ground bus VSS, and the gate is connected to the other end of the first resistor R1.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device-like embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An electrostatic protection structure, comprising:

a plurality of voltage domain circuits, each of the voltage domain circuits including at least a ground level bus;

and the conduction circuit is connected with the adjacent ground level buses and at least comprises a control end, and the control end controls the conduction circuit to establish a path between the adjacent ground level buses when detecting the potential difference of the adjacent ground level buses.

2. The electrostatic protection structure of claim 1, wherein the adjacent ground level buses comprise a first ground level bus and a second ground level bus;

3. The electrostatic protection structure of claim 2, wherein the first conducting unit and the second conducting unit are both MOS devices.

4. The electrostatic protection structure of claim 3, wherein the control terminal comprises a first control terminal located at the first conducting unit and a second control terminal located at the second conducting unit;

5. The electrostatic protection structure of claim 4, wherein the first PMOS transistor is located on a semiconductor substrate, comprising:

a first n-well region located within the semiconductor substrate;

6. The electrostatic protection structure of claim 5, wherein the second PMOS transistor is located on the same semiconductor substrate as the first PMOS transistor, comprising:

a second n-well region located within the semiconductor substrate;

7. The esd-protection structure of claim 6, wherein a number of the first PMOS device cells in the first PMOS transistor is plural, and a plurality of the first PMOS device cells are arranged in the first nwell region in an array; the number of the second PMOS device units in the second PMOS transistor is multiple, and the second PMOS device units are arranged in the second n well region in an array mode.

8. The electrostatic protection structure of claim 7, wherein the ground level bus comprises a plurality of ground level lines, one ground level line connecting a row of the first and/or second PMOS device cells.

9. An electrostatic protection structure according to claim 3, wherein:

the first conducting unit is a first NMOS transistor, the grid electrode and the source electrode of the first NMOS transistor are connected with the first ground level bus, the drain electrode of the first NMOS transistor is connected with the second ground level bus, and the grid electrode of the first NMOS transistor is used as a first control end;

10. The electrostatic protection structure of claim 9, wherein the first NMOS transistor is located on a semiconductor substrate, comprising:

11. The electrostatic protection structure of claim 10, wherein the second NMOS transistor is located on the same semiconductor substrate as the first NMOS transistor, comprising:

12. The esd-protection structure of claim 11, wherein said first NMOS device cells of said first NMOS transistor are plural in number, and a plurality of said first NMOS device cells are arranged in an array in said first p-well region; the number of the second NMOS device units in the second NMOS transistor is multiple, and the second NMOS device units are arranged in the second p-well region in an array mode.

13. The electrostatic protection structure of claim 12, wherein the ground level bus comprises a plurality of ground level lines, one ground level line connecting a row of the first NMOS device cells and/or second NMOS device cells.

14. The electrostatic protection structure of claim 1, wherein the voltage domain circuit comprises a power bus and a clamp circuit connecting the power bus and the ground bus.

15. The esd protection structure of claim 14, wherein the voltage domain circuit further comprises a voltage domain operating circuit, the voltage domain operating circuit being powered by the power bus.