CN112527361B - FPGA test program updating method and device, electronic equipment and storage medium - Google Patents
FPGA test program updating method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of computers, and discloses a method and a device for updating an FPGA test program, electronic equipment and a storage medium. The method comprises the following steps: acquiring an FPGA bit stream to be updated, and acquiring an update test file according to a test task; updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file; and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program. By the method, the test program is merged into the FPGA bit stream, so that the FPGA design is prevented from being re-integrated. Compared with the prior art, the replacement mode has the advantages that Flash is programmed and re-synthesized, the required time is less, and the test efficiency is improved. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an FPGA test program updating method and device, electronic equipment and a storage medium.
Background
Verification plays a very important role in RISC-V (Reduced Instruction Set Computing Five) processor design. Because the FPGA (Field Programmable Gate Array) prototype verification of the processor has high operation speed, is closer to the real operation environment of the processor and becomes an important verification means of the RISC-V processor.
In the verification process, a large number of test cases need to be run to verify the functional correctness of the processor core and perform performance evaluation. Therefore, the test program needs to be constantly updated. The current program updating method needs to program the program to the Flash chip (coding type Flash memory), and the programming time is long. The processor core verifies that a large number of test programs need to be operated, and reading and writing the Flash chip consumes a large amount of time. Although the upper computer can directly configure the FPGA through a Joint Test Action Group (JTAG) interface, thereby omitting the programming process, the above method needs to re-integrate the entire FPGA design every time the program is updated, and the integration process often takes a long time (e.g., more than tens of minutes) according to the size of the design scale.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide an FPGA test program updating method, an FPGA test program updating device, electronic equipment and a storage medium, and aims to solve the technical problem that in the prior art, the time required for updating an FPGA test program of an FPGA verification module is long.
In order to achieve the above object, the present invention provides an FPGA test program updating method, including:
acquiring an FPGA bit stream to be updated, and acquiring an update test file according to a test task;
updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file;
and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program.
Optionally, the step of obtaining the FPGA bitstream to be updated and obtaining the update test file according to the test task specifically includes:
acquiring an FPGA bit stream to be updated, wherein the FPGA bit stream to be updated does not comprise a test program;
and generating a corresponding updated test file according to the test task.
Optionally, the step of updating the to-be-updated FPGA bitstream according to the update test file to obtain an update FPGA bitstream corresponding to the update test file specifically includes:
and storing the updating test file in an instruction memory of the FPGA bit stream to be updated so as to obtain an updating FPGA bit stream corresponding to the updating test file.
Optionally, the step of obtaining the FPGA bitstream to be updated and obtaining the update test file according to the test task specifically includes:
acquiring an initial test program, and generating an FPGA bit stream to be updated according to the initial test program;
and generating a corresponding updated test file according to the test task.
Optionally, the step of updating the to-be-updated FPGA bitstream according to the update test file to obtain an update FPGA bitstream corresponding to the update test file specifically includes:
and replacing the initial test file stored in the instruction memory of the FPGA bit stream to be updated with the updated test file to obtain an updated FPGA bit stream corresponding to the updated test file.
Optionally, after the step of obtaining the initial test program and generating the FPGA bitstream to be updated according to the initial test program, the method further includes:
and configuring the FPGA verification module according to the FPGA bit stream to be updated so that the FPGA verification module obtains an initial test program according to the configured FPGA bit stream to be updated and tests according to the initial test program.
Optionally, after the step of configuring the FPGA verification module according to the updated FPGA bitstream to update the test program, the method further includes:
and sending a test instruction to the FPGA verification module so that a processor core of the FPGA verification module obtains a test program according to the configured updated FPGA bit stream and tests according to the test program.
In addition, in order to achieve the above object, the present invention further provides an FPGA test program updating apparatus, including:
the bit stream acquisition module is used for acquiring the FPGA bit stream to be updated and acquiring an update test file according to the test task;
the bit stream updating module is used for updating the FPGA bit stream to be updated according to the updating test file so as to obtain an updating FPGA bit stream corresponding to the updating test file;
and the program updating module is used for configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program.
In addition, in order to achieve the above object, the present invention further provides an electronic device, a memory, a processor, and an FPGA test program update program stored on the memory and operable on the processor, where the FPGA test program update program is configured to implement the steps of the FPGA test program update method.
In addition, in order to achieve the above object, the present invention further provides a storage medium, where an FPGA test program update program is stored, and when the FPGA test program update program is executed by a processor, the steps of the FPGA test program update method are implemented.
The method comprises the steps of obtaining an FPGA bit stream to be updated, and obtaining an update test file according to a test task; updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file; and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program. By the method, the test program is merged into the FPGA bit stream, so that the FPGA design is prevented from being re-integrated. Compared with Flash programming and re-synthesis, the replacement mode takes much less time, and improves the test efficiency. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
Drawings
Fig. 1 is a schematic structural diagram of an electronic device in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flowchart of a first embodiment of a method for updating an FPGA test program according to the present invention;
FIG. 3 is a block diagram of an FPGA verification system according to an embodiment of the FPGA test program updating method of the present invention;
FIG. 4 is a flowchart illustrating a second embodiment of the FPGA test program updating method according to the present invention;
FIG. 5 is a flowchart illustrating a third embodiment of a method for updating an FPGA test program according to the present invention;
fig. 6 is a block diagram of the first embodiment of the FPGA test program updating apparatus according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the electronic device may include: a processor 1001, such as a Central Processing Unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., a WIreless-FIdelity (WI-FI) interface). The Memory 1005 may be a Random Access Memory (RAM) Memory, or may be a Non-Volatile Memory (NVM), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration shown in fig. 1 does not constitute a limitation of the electronic device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a storage medium, may include therein an operating system, a network communication module, a user interface module, and an FPGA test program update program.
In the electronic apparatus shown in fig. 1, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the electronic device of the present invention may be arranged in the electronic device, and the electronic device calls the FPGA test program update program stored in the memory 1005 through the processor 1001 and executes the FPGA test program update method provided in the embodiment of the present invention.
An embodiment of the present invention provides an FPGA test program updating method, and referring to fig. 2, fig. 2 is a schematic flow diagram of a first embodiment of the FPGA test program updating method according to the present invention.
It should be noted that, with reference to fig. 3, the FPGA verification system used in this embodiment includes: the upper computer and the FPGA are interconnected through a Joint Test Action Group (JTAG) interface, a Universal Asynchronous Receiver/Transmitter (UART) interface and other interfaces. The upper computer is responsible for generating the FPGA bit stream, updating the test program bit stream and configuring the FPGA.
The FPGA verification module performs verification on the FPGA, and the verification system mainly comprises the FPGA verification module, an instruction memory, a data memory, a bus and a URAT. The instruction memory is used for storing a test program. The data memory is used for storing data generated by executing the process. The bus is used for connection and communication of the modules. The UART is used to communicate with the host and debug.
It should be noted that, because the method adopted by the present invention avoids reading and writing the Flash chip, there is no need to read and write the Flash chip, and there is no need to set a Serial Peripheral Interface (SPI) controller (used for communicating with various Peripheral devices in a Serial manner to exchange information) in the system. The program is executed directly from the instruction memory, and therefore, a BOOTROM (diskless boot ROM interface) may not be used.
In this embodiment, the method for updating the FPGA test program includes the following steps:
step S10: and acquiring the FPGA bit stream to be updated, and acquiring an update test file according to the test task.
It should be noted that the execution main body of the embodiment is an FPGA test program updating device, the FPGA test program updating device may be an upper computer, and for FPGA verification of the processor core, a large number of test cases need to be run to verify the functional correctness of the processor core and perform performance evaluation. Therefore, the test program needs to be constantly updated.
It is easy to understand that, in the prior art, a program is updated through a processor core, a test program is first programmed into a Flash chip by an upper computer, then the processor copies the test program into an instruction memory from the Flash chip, and then the test program is executed from the instruction memory; or initializing the test program into the instruction memory, generating an FPGA bit stream comprehensively by an Electronic Design Automation (EDA) tool, wherein the bit stream contains the test program, programming the bit stream into the Flash chip by the upper computer, copying the test program into the instruction memory from the Flash chip by the processor, and executing the test program from the instruction memory.
It should be understood that in the prior art, a Flash chip needs to be programmed, the programming of the Flash chip takes a long time, a large amount of test programs need to be run for processor core verification, and a large amount of time is consumed for reading and writing the Flash chip in the test program updating process.
It should be noted that, in the present invention, the test program is merged into the FPGA bitstream, and first, the FPGA bitstream of the processor core verification system is generated as the FPGA bitstream to be updated, and the test program required by the test is obtained, where the test program is the test program required by the next test and can be used as an update test file.
Step S20: and updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file.
It is easy to understand that, in the present application, the to-be-updated FPGA bitstream is updated by updating the test file, specifically, the test program corresponding to the updated test file is stored in the instruction memory in the to-be-updated FPGA bitstream to generate a new bitstream, that is, the updated FPGA bitstream.
It should be understood that in other embodiments of the present invention, if there is no content in the instruction memory of the bit stream to be updated, the update file is directly filled into the instruction memory; and if the instruction memory of the bit stream to be updated has the initial test program, replacing the initial test program with the updated test file.
Step S30: and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program.
It should be understood that, after the updated FPGA bitstream is updated, the updated FPGA bitstream includes an updated test file, the updated FPGA bitstream is downloaded into an instruction memory of the FPGA, and further, the updated FPGA bitstream is configured through the updated FPGA bitstream and stored into the instruction memory of the FPGA verification module, so as to update the test program.
Further, step S30 is followed by: and sending a test instruction to the FPGA verification module so that a processor core of the FPGA verification module obtains a test program according to the configured updated FPGA bit stream and tests according to the test program.
It is easy to understand that after the FPGA verification module configures the bit stream, the FPGA verification module can automatically run through the reset of the processor core so as to test; or after the FPGA verification module configures the bit stream, the testing can be started through a testing instruction sent by the upper computer, and the processor core of the FPGA verification module starts to execute the testing program from the instruction memory. And if the test is finished, returning the test result. If all the test programs are finished, finishing the test, and if not, returning to the step S10, and updating again to obtain a new test file for testing.
The method comprises the steps of obtaining an FPGA bit stream to be updated, and obtaining an update test file according to a test task; updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file; and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program. By the method, the test program is merged into the FPGA bit stream, so that the FPGA design is prevented from being re-integrated. Compared with Flash programming and re-synthesis, the replacement mode takes much less time, and improves the test efficiency. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
Referring to fig. 4, fig. 4 is a flowchart illustrating a method for updating an FPGA test program according to a second embodiment of the present invention. Based on the first embodiment, in step S10, the method for updating the FPGA test program of this embodiment specifically includes:
step S101: and acquiring an FPGA bit stream to be updated, wherein the FPGA bit stream to be updated does not comprise a test program.
It should be noted that, an FPGA bitstream to be updated is generated, and an instruction memory in the FPGA bitstream to be updated may have no content. In specific implementation, when a test is started, an FPGA bit stream to be updated is generated first, wherein the content of the FPGA bit stream is nothing.
Step S103: and generating a corresponding updated test file according to the test task.
It is easy to understand that, in the specific implementation of the test task, the setting is performed according to different test requirements, and this embodiment does not limit this. And compiling the test program according to the test task to generate a binary executable file corresponding to the test program, namely, the updated test file. At this step, the test program may also be batch compiled by script.
Further, the step S20 specifically includes:
step S201: and storing the updating test file in an instruction memory of the FPGA bit stream to be updated so as to obtain an updating FPGA bit stream corresponding to the updating test file.
It should be noted that, an EDA tool (for example, an Update Memory Initialization File of Xilinx) may be used to add an Update test File to the content (in an initial state, the content is none) of the instruction Memory of the FPGA bitstream to be updated, so as to generate a new Update FPGA bitstream corresponding to the test program. At this step, the updated FPGA bit stream containing the test programs may also be generated in batch by a script. The naming and testing procedures of the newly generated updated FPGA bit stream remain consistent for ease of differentiation.
The present embodiment incorporates test programs into the FPGA bitstream, thereby avoiding re-synthesis of the FPGA design. Compared with Flash programming and re-synthesis, the replacement mode takes much less time, and improves the test efficiency. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
Referring to fig. 5, fig. 5 is a schematic flowchart of a third embodiment of an FPGA test program updating method according to the present invention. Based on the first embodiment, in step S10, the method for updating the FPGA test program of this embodiment specifically includes:
step S102: and acquiring an initial test program, and generating an FPGA bit stream to be updated according to the initial test program.
It should be noted that, an FPGA bitstream to be updated is generated, and an instruction memory in the FPGA bitstream to be updated may be initialized to a test program. In a specific implementation, when a test is started, an FPGA bitstream to be updated is generated in which the contents of an instruction memory contain an initial test program.
Step S103: and generating a corresponding updated test file according to the test task.
It is easy to understand that the above steps have been specifically described in the second embodiment, and are not described in detail herein.
Further, the step S20 specifically includes:
step S202: and replacing the initial test file stored in the instruction memory of the FPGA bit stream to be updated with the updated test file to obtain an updated FPGA bit stream corresponding to the updated test file.
It should be noted that, an EDA tool (for example, an Update Memory Initialization File of Xilinx) may be used to replace the content (initial test program) of the instruction Memory of the FPGA bitstream to be updated with an Update test File, so as to generate a new Update FPGA bitstream corresponding to the Update test File. At this step, the updated FPGA bit stream containing the test programs may also be generated in batch by a script. The naming and testing procedures of the newly generated updated FPGA bit stream remain consistent for ease of differentiation.
Further, after the step S102, the method further includes:
and configuring the FPGA verification module according to the FPGA bit stream to be updated so that the FPGA verification module obtains an initial test program according to the configured FPGA bit stream to be updated and tests according to the initial test program.
It is easy to understand that if the instruction memory of the bit stream of the FPGA to be updated is initialized to be a test program, the test program can be directly downloaded to the FPGA for execution, so that a replacement process is saved.
The present embodiment incorporates test programs into the FPGA bitstream, thereby avoiding re-synthesis of the FPGA design. Compared with Flash programming and re-synthesis, the replacement mode takes much less time, and improves the test efficiency. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
Referring to fig. 6, fig. 6 is a block diagram illustrating a first embodiment of an FPGA test program updating apparatus according to the present invention.
It should be noted that, with reference to fig. 3, the FPGA verification system used in this embodiment includes: the upper computer and the FPGA are interconnected through a Joint Test Action Group (JTAG) interface, a Universal Asynchronous Receiver/Transmitter (UART) interface and other interfaces. The upper computer is responsible for generating the FPGA bit stream, updating the test program bit stream and configuring the FPGA.
The FPGA verification module performs verification on the FPGA, and the verification system mainly comprises the FPGA verification module, an instruction memory, a data memory, a bus and a URAT. The instruction memory is used for storing a test program. The data memory is used for storing data generated by executing the process. The bus is used for connection and communication of the modules. The UART is used to communicate with the host and debug.
It should be noted that, because the method adopted by the present invention avoids reading and writing the Flash chip, there is no need to read and write the Flash chip, and there is no need to set a Serial Peripheral Interface (SPI) controller (used for communicating with various Peripheral devices in a Serial manner to exchange information) in the system. The program is executed directly from the instruction memory, and therefore, a BOOTROM (diskless boot ROM interface) may not be used.
In this embodiment, the FPGA test program updating apparatus includes:
and the bit stream obtaining module 10 is configured to obtain a bit stream of the FPGA to be updated, and obtain an update test file according to the test task.
It should be noted that the FPGA test program updating apparatus may be an upper computer, and for FPGA verification of the processor core, a large number of test cases need to be run to verify the functional correctness of the processor core and perform performance evaluation. Therefore, the test program needs to be constantly updated.
It is easy to understand that, in the prior art, a program is updated through a processor core, a test program is first programmed into a Flash chip by an upper computer, then the processor copies the test program into an instruction memory from the Flash chip, and then the test program is executed from the instruction memory; or initializing the test program into the instruction memory, generating an FPGA bit stream comprehensively by an Electronic Design Automation (EDA) tool, wherein the bit stream contains the test program, programming the bit stream into the Flash chip by the upper computer, copying the test program into the instruction memory from the Flash chip by the processor, and executing the test program from the instruction memory.
It should be understood that in the prior art, a Flash chip needs to be programmed, the programming of the Flash chip takes a long time, a large amount of test programs need to be run for processor core verification, and a large amount of time is consumed for reading and writing the Flash chip in the test program updating process.
It should be noted that, in the present invention, the test program is merged into the FPGA bitstream, and first, the FPGA bitstream of the processor core verification system is generated as the FPGA bitstream to be updated, and the test program required by the test is obtained, where the test program is the test program required by the next test and can be used as an update test file.
And a bit stream updating module 20, configured to update the FPGA bit stream to be updated according to the update test file, so as to obtain an update FPGA bit stream corresponding to the update test file.
It is easy to understand that, in the present application, the to-be-updated FPGA bitstream is updated by updating the test file, specifically, the test program corresponding to the updated test file is stored in the instruction memory in the to-be-updated FPGA bitstream to generate a new bitstream, that is, the updated FPGA bitstream.
It should be understood that in other embodiments of the present invention, if there is no content in the instruction memory of the bit stream to be updated, the update file is directly filled into the instruction memory; and if the instruction memory of the bit stream to be updated has the initial test program, replacing the initial test program with the updated test file.
And the program updating module 30 is configured to configure the FPGA verification module according to the updated FPGA bit stream, so as to update the test program.
It should be understood that, after the updated FPGA bitstream is updated, the updated FPGA bitstream includes an updated test file, the updated FPGA bitstream is downloaded into an instruction memory of the FPGA, and further, the updated FPGA bitstream is configured through the updated FPGA bitstream and stored into the instruction memory of the FPGA verification module, so as to update the test program.
The program updating module 30 is further configured to send a test instruction to the FPGA verification module, so that the processor core of the FPGA verification module obtains a test program according to the configured updated FPGA bit stream, and performs a test according to the test program.
It is easy to understand that after the FPGA verification module configures the bit stream, the FPGA verification module can automatically run through the reset of the processor core so as to test; or after the FPGA verification module configures the bit stream, the testing can be started through a testing instruction sent by the upper computer, and the processor core of the FPGA verification module starts to execute the testing program from the instruction memory. And if the test is finished, returning the test result. If all the test programs are finished, finishing the test, and if not, updating again to obtain a new test file for testing.
The method comprises the steps of obtaining an FPGA bit stream to be updated, and obtaining an update test file according to a test task; updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file; and configuring the FPGA verification module according to the updated FPGA bit stream so as to update the test program. The invention incorporates test programs into the FPGA bitstream, thereby avoiding re-synthesis of FPGA designs. Compared with Flash programming and re-synthesis, the replacement mode takes much less time, and improves the test efficiency. On the other hand, different test programs can be used for generating respective bit streams in batches, and the freedom degree and the convenience of testing are improved.
In addition, an embodiment of the present invention further provides a storage medium, where an FPGA test program update program is stored on the storage medium, and the FPGA test program update program is executed by the processor by the steps of the FPGA test program update method described above.
Since the storage medium adopts all technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
It should be understood that the above is only an example, and the technical solution of the present invention is not limited in any way, and in a specific application, a person skilled in the art may set the technical solution as needed, and the present invention is not limited thereto.
It should be noted that the above-described work flows are only exemplary, and do not limit the scope of the present invention, and in practical applications, a person skilled in the art may select some or all of them to achieve the purpose of the solution of the embodiment according to actual needs, and the present invention is not limited herein.
In addition, the technical details that are not described in detail in this embodiment may refer to the method for updating the FPGA test program provided in any embodiment of the present invention, and are not described herein again.
Further, it is to be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention or portions thereof that contribute to the prior art may be embodied in the form of a software product, where the computer software product is stored in a storage medium (e.g. Read Only Memory (ROM)/RAM, magnetic disk, optical disk), and includes several instructions for enabling a terminal device (e.g. a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. An FPGA test program updating method is characterized by comprising the following steps:
acquiring an FPGA bit stream to be updated, and acquiring an update test file according to a test task;
updating the FPGA bit stream to be updated according to the update test file to obtain an update FPGA bit stream corresponding to the update test file;
configuring an FPGA verification module according to the updated FPGA bit stream to update a test program;
wherein the updating the FPGA bit stream to be updated according to the update test file comprises:
and replacing the current content in the instruction memory of the bit stream to be updated with the updating test file.
2. The method for updating the FPGA test program according to claim 1, wherein the step of obtaining the FPGA bit stream to be updated and obtaining the update test file according to the test task specifically comprises:
acquiring an FPGA bit stream to be updated, wherein the FPGA bit stream to be updated does not comprise a test program;
and generating a corresponding updated test file according to the test task.
3. The FPGA test program updating method according to claim 2, wherein the step of updating the FPGA bitstream to be updated according to the update test file to obtain the update FPGA bitstream corresponding to the update test file specifically comprises:
and storing the updating test file in an instruction memory of the FPGA bit stream to be updated so as to obtain an updating FPGA bit stream corresponding to the updating test file.
4. The method for updating the FPGA test program according to claim 1, wherein the step of obtaining the FPGA bit stream to be updated and obtaining the update test file according to the test task specifically comprises:
acquiring an initial test program, and generating an FPGA bit stream to be updated according to the initial test program;
and generating a corresponding updated test file according to the test task.
5. The FPGA test program updating method according to claim 4, wherein said step of updating the FPGA bitstream to be updated according to the update test file to obtain the update FPGA bitstream corresponding to the update test file specifically comprises:
and replacing the initial test file stored in the instruction memory of the FPGA bit stream to be updated with the updated test file to obtain an updated FPGA bit stream corresponding to the updated test file.
6. The FPGA test program updating method of claim 4, wherein after the step of obtaining the initial test program and generating the FPGA bit stream to be updated according to the initial test program, further comprising:
and configuring the FPGA verification module according to the FPGA bit stream to be updated, so that a processor core in the FPGA verification module obtains an initial test program according to the configured FPGA bit stream to be updated, and testing according to the initial test program.
7. The FPGA test program updating method of any one of claims 1 to 6, wherein said step of configuring said FPGA verification module according to said updated FPGA bitstream to implement said test program updating further comprises:
and sending a test instruction to the FPGA verification module so that a processor core of the FPGA verification module obtains a test program according to the configured updated FPGA bit stream and tests according to the test program.
8. An FPGA test program updating device, characterized in that, the device includes:
the bit stream acquisition module is used for acquiring the FPGA bit stream to be updated and acquiring an update test file according to the test task;
the bit stream updating module is used for updating the FPGA bit stream to be updated according to the updating test file so as to obtain an updating FPGA bit stream corresponding to the updating test file;
the program updating module is used for configuring the FPGA verification module according to the updated FPGA bit stream so as to realize test program updating;
the bitstream updating module is specifically configured to replace the current content in the instruction memory of the bitstream to be updated with the update test file.
9. An electronic device, characterized in that the electronic device comprises: a memory, a processor and an FPGA test program update program stored on the memory and executable on the processor, the FPGA test program update program being configured to implement the steps of the FPGA test program update method of any one of claims 1 to 7.
10. A storage medium having stored thereon an FPGA test program update program which, when executed by a processor, implements the steps of the FPGA test program update method of any one of claims 1 to 7.
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| US10262098B1 (en) * | 2015-10-29 | 2019-04-16 | National Technology & Engineering Solutions Of Sandia, Llc | Field programmable gate array bitstream verification |
| CN208873142U (en) * | 2018-07-19 | 2019-05-17 | 广东高云半导体科技股份有限公司 | A kind of FPGA development board |
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| CN110989417B (en) * | 2019-10-29 | 2023-02-03 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Period detection system adaptive to FPGA local reconstruction |
| CN111638444A (en) * | 2020-05-07 | 2020-09-08 | 湖北航天技术研究院计量测试技术研究所 | High-capacity FPGA (field programmable Gate array) testing tool and testing method based on SPI (Serial peripheral interface) configuration mode |
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| US10262098B1 (en) * | 2015-10-29 | 2019-04-16 | National Technology & Engineering Solutions Of Sandia, Llc | Field programmable gate array bitstream verification |
| CN208873142U (en) * | 2018-07-19 | 2019-05-17 | 广东高云半导体科技股份有限公司 | A kind of FPGA development board |
| CN109858195A (en) * | 2019-03-22 | 2019-06-07 | 中国科学院光电技术研究所 | The on-line simulation system of necessary position single-particle inversion failure on a kind of SRAM type FPGA |
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