CN112505971A

CN112505971A - Electronic device and method for manufacturing the same

Info

Publication number: CN112505971A
Application number: CN201910871259.6A
Authority: CN
Inventors: 蔡宗翰
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2019-09-16
Filing date: 2019-09-16
Publication date: 2021-03-16
Also published as: US20210083351A1; US20230387562A1; US11749872B2

Abstract

The present invention provides an electronic device, comprising: the liquid crystal display panel comprises a first substrate, a plurality of phase-shifting electrodes, a second substrate, a plurality of patches, a common electrode layer, a dielectric layer and a liquid crystal layer; the phase-shifting electrodes are arranged on the first substrate, the second substrate is provided with an inner side facing the first substrate, the patches are arranged on the inner side of the second substrate, and the dielectric layer is arranged between the common electrode layer and the second substrate and arranged on the patches; and the liquid crystal layer is arranged between the plurality of phase-shifting electrodes and the common electrode layer. The invention also provides a manufacturing method of the electronic device.

Description

Electronic device and method for manufacturing the same

Technical Field

The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to an antenna device and a method for manufacturing the same.

Background

Electronic products have become indispensable necessities in modern society. With the explosion of such electronic products, consumers have a high expectation on the quality, function or price of these products.

Some electronic products are further equipped with communication capabilities, such as antenna devices, but are not yet satisfactory in every aspect. Therefore, developing a structure design that can further improve the performance or operation reliability of the electronic product or the electronic device is still one of the subjects of the present research.

Disclosure of Invention

According to some embodiments of the present invention, there is provided an electronic apparatus, including: the liquid crystal display panel comprises a first substrate, a plurality of phase-shifting electrodes, a second substrate, a plurality of patches, a common electrode layer, a dielectric layer and a liquid crystal layer. The phase-shifting electrodes are arranged on the first substrate, the second substrate is provided with an inner side facing the first substrate, the patches are arranged on the inner side of the second substrate, and the dielectric layer is arranged between the common electrode layer and the second substrate and arranged on the patches. And the liquid crystal layer is arranged between the plurality of phase-shifting electrodes and the common electrode layer.

According to some embodiments of the present invention, there is provided an electronic apparatus, including: the liquid crystal display device comprises a first substrate, a plurality of phase-shifting electrodes, a dielectric layer, a plurality of patches, a common electrode layer, a liquid crystal layer, a first alignment layer and a second alignment layer. The phase-shifting electrodes are arranged on the first substrate, the dielectric layer is arranged on the phase-shifting electrodes, the patches are arranged on the dielectric layer, and the common electrode layer is arranged between the dielectric layer and the first substrate. The liquid crystal layer is arranged between the plurality of phase-shifting electrodes and the dielectric layer, the first alignment layer is arranged between the plurality of phase-shifting electrodes and the liquid crystal layer, and the second alignment layer is arranged between the common electrode layer and the liquid crystal layer.

According to some embodiments of the present invention, there is provided a method of manufacturing an electronic device, including: providing a first substrate; forming a plurality of phase shift electrodes on a first substrate; providing a second substrate; forming a plurality of patches on a second substrate; forming a dielectric layer on the plurality of patches; forming a common electrode layer on the dielectric layer, wherein the dielectric layer is located between the common electrode layer and the second substrate; the first substrate and the second substrate are paired, and the plurality of patches are positioned on the inner side of the second substrate, wherein the inner side faces the first substrate; and forming a liquid crystal layer between the first substrate and the second substrate, wherein the liquid crystal layer is positioned between the plurality of phase shift electrodes and the common electrode layer.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic top view of an electronic device according to some embodiments of the invention;

FIG. 2 is a perspective view of a portion of an electronic device according to some embodiments of the invention;

FIG. 3 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 4 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 5 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 6 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 7 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 8 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 9 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIG. 10 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;

FIGS. 11A-11H are schematic cross-sectional views illustrating an electronic device at an intermediate stage of processing according to some embodiments of the present invention;

fig. 12A-12F are schematic cross-sectional views of an electronic device at an intermediate stage of processing according to some embodiments of the present invention.

Description of the symbols

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10K electronic devices;

a 100A modulation unit;

102a first substrate;

102a inside;

102b outside;

104 a phase shifting electrode;

106 a first buffer layer;

108 a first alignment layer;

202a second substrate;

202a inside;

202b outside;

202r is concave;

203 a coplanar waveguide;

204 a patch;

204t top surface;

206a dielectric layer;

206a inside;

206b outside;

a 206e hole;

206p is opened;

206r are concave;

208 a common electrode layer;

208p is opened;

210 a second buffer layer;

210p opening;

212 a second alignment layer;

214 a protective layer;

214t top surface;

216 a cap layer;

300 a liquid crystal layer;

a 400 feed-in structure;

a 400A feed source;

feeding a wire 400B;

A-A' section line;

d₁a first distance;

d₂a second distance;

D_pa diameter;

T₁a first thickness;

T₂a second thickness;

T₃a third thickness;

T_3athickness;

T_3bthickness;

W₁a first width;

W₂a second width;

W₃a third width;

W₄a fourth width;

W₅and a fifth width.

Detailed Description

The electronic device and the method for manufacturing the same according to the embodiments of the present invention are described in detail below. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting. Moreover, similar and/or corresponding elements may be labeled with similar and/or corresponding reference numerals in different embodiments in order to clearly describe the invention. However, the use of such like and/or corresponding reference numerals is merely for simplicity and clarity in describing some embodiments of the invention and does not represent any correlation between the various embodiments and/or structures discussed.

It should be understood that the elements of the drawings or devices may exist in various forms well known to those skilled in the art. In addition, relative terms, such as "lower" or "bottom" or "upper" or "top," may be used in relation to one element of the figures to describe the relative relationship of one element to another. It will be understood that if the device of the drawings is turned over with its top and bottom portions reversed, the elements described as being on the "lower" side will be turned over to those on the "higher" side. The embodiments of the present invention can be understood together with the accompanying drawings, which are also to be considered part of the description of the invention. It is to be understood that the drawings of the present invention are not to scale and that in fact any enlargement or reduction of the dimensions of the elements is possible in order to clearly show the nature of the invention.

Further, when a first material layer is referred to as being on or over a second material layer, the first material layer may be directly in contact with the second material layer, or one or more other material layers may be interposed therebetween, in which case the first material layer may not be directly in contact with the second material layer.

Further, it should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, or sections, these elements, components, or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

As used herein, the terms "about", "approximately", "substantially" and "approximately" generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The given numbers are approximate numbers, i.e., the meaning of "about", "substantially", "approximately" can be implied without specification to "about", "approximately", "substantially". Moreover, the terms "range from a first value to a second value," and "range between a first value and a second value," mean that the range includes the first value, the second value, and other values therebetween.

In some embodiments of the present invention, terms concerning bonding, connecting, such as "connected," "interconnected," and the like, may refer to two structures as being in direct contact, or alternatively, may refer to two structures as being not in direct contact, unless otherwise specified, with other structures being interposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed. In addition, the term "coupled" encompasses any direct and indirect electrical connection.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

According to some embodiments of the present invention, the method for manufacturing an electronic device can form the patches and the common electrodes on the same side (single side) of the substrate, so that the risk of degradation of the modulation material or cracking of the substrate due to the process temperature can be reduced or the process can be further simplified as compared with the process of forming metal layers on both sides of the substrate, but the method is not limited thereto. Furthermore, according to some embodiments of the present invention, the electronic device formed by the foregoing manufacturing method can reduce the dielectric loss of electromagnetic waves or improve the reliability of operation.

According to some embodiments of the present invention, an electronic device may include, but is not limited to, an antenna device, a liquid crystal display device, a sensing device, a light-emitting device, a splicing device, other suitable devices, or a combination thereof. The electronic device can be a bendable or flexible electronic device. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, an antenna splicing device, but is not limited thereto. It should be understood that the electronic device can be any permutation and combination of the foregoing, but the invention is not limited thereto.

Referring to fig. 1, fig. 1 is a schematic top view illustrating an electronic device 10A according to some embodiments of the invention. It should be understood that, for clarity of illustration, some elements are omitted in the figures, and only the modulation unit 100A of a part of the electronic device 10A is schematically illustrated. In addition, fig. 1 also omits a part of the coplanar waveguide 203, and the coplanar waveguide 203 may overlap with one end (e.g., near the feed-in line 400B) of the phase-shift electrode 104 in the normal direction (e.g., Z direction) of the first substrate 102. For example, the coplanar waveguide 203 may be disposed on the second substrate 202 (shown in fig. 2), but is not limited thereto. In the present invention, unless otherwise specified, "overlap" may include "overlap" and "partial overlap". In various embodiments, the number of the modulation units 100A of the electronic device 10A may be adjusted according to actual requirements. Furthermore, it should be understood that additional features may be added to the electronic device 10A described below, according to some embodiments. In other embodiments, some of the features of the electronic device 10A described below may be replaced or omitted.

As shown in fig. 1, the electronic device 10A may include a first substrate 102 and a plurality of modulation units 100A disposed on the first substrate 102. In some embodiments, the electronic device 10A may be an antenna device, and the modulation unit 100A may be an antenna unit for modulating electromagnetic waves (e.g., radio frequency or microwave).

In some embodiments, the material of the first substrate 102 may include glass, quartz, sapphire (sapphire), ceramic, Polyimide (PI), Liquid Crystal Polymer (LCP) material, Polycarbonate (PC), photosensitive polyimide (PSPI), polyethylene terephthalate (PET), other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the first substrate 102 may include a Printed Circuit Board (PCB). In some embodiments, the first substrate 102 may include a flexible substrate, a rigid substrate, or a combination thereof.

Furthermore, as shown in fig. 1, according to some embodiments, the electronic device 10A may include a feeding structure (feeding structure)400, and the feeding structure 400 may be disposed on the first substrate 102 for transmitting electromagnetic wave signals. In some embodiments, the feed structure 400 has a feed source 400A and a feed line 400B, and the feed line 400B may be coupled with the feed source 400A, and the feed source 400A may provide an initial feed wave (feeding wave). In an embodiment, one feed line 400B may be coupled with a plurality of feeds 400A, but is not limited thereto. In another embodiment, multiple feed lines 400B may be coupled to one feed source 400A, but is not limited thereto. In some embodiments, the feed structure 400 has a plurality of feeds 400A coupled to a plurality of feed lines 400B, but is not limited thereto. In some embodiments, the initial feed wave may be a high frequency electromagnetic wave, but is not limited thereto. In addition, in some embodiments, the feeding structure 400 may be further coupled to a signal processor, a signal modulator, or a combination thereof (not shown).

In some embodiments, the feeding structure 400 may include a conductive material, e.g., a metallic conductive material. In some embodiments, the metallic conductive material may include copper (Cu), silver (Ag), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), copper alloy, silver alloy, tin alloy, aluminum alloy, molybdenum alloy, tungsten alloy, gold alloy, chromium alloy, nickel alloy, platinum alloy, titanium alloy, other suitable conductive material, or a combination of the foregoing, but is not limited thereto.

In addition, the electronic device 10A may include a plurality of phase-shift electrodes 104 (or referred to as microstrip lines), and the phase-shift electrodes 104 may be disposed on the first substrate 102. Phase-shifting electrode 104 may be adjacent to feed structure 400, and phase-shifting electrode 104 may have a spiral shape or a loop shape, but is not limited thereto. At least one of the phase-shifting electrodes 104 can be configured to receive an electromagnetic wave signal from the feeding structure 400, for example, the feeding structure 400 can couple the electromagnetic wave signal to the phase-shifting electrode 104 through the coplanar waveguide 203 by way of the feeding line 400B in a current-induced manner. However, in other embodiments, the phase-shift electrode 104 may also be used to feed out the processed or modulated electromagnetic wave signal, for example, to the feed-in line 400B. In detail, the electric potential of the phase-shift electrode 104 is changed to change the electric field or the magnetic field between the phase-shift electrode 104 and the common electrode layer 208, so as to modulate the refractive index of the modulating material located above or around the phase-shift electrode 104, thereby changing the phase difference of the passing electromagnetic wave. In another embodiment, the capacitance can be changed by changing the electric potential of the phase-shift electrode 104 to change the electric or magnetic field between the phase-shift electrode 104 and the common electrode layer 208 to modulate the dielectric constant of the modulating material over or around the phase-shift electrode 104.

In some embodiments, the material of phase-shifting electrode 104 may comprise a metallic conductive material, a transparent conductive material, or a combination of the foregoing. The metal conductive material is similar to the metal conductive material of the feeding structure 400, and is not described in detail herein. The transparent conductive material may include a Transparent Conductive Oxide (TCO). For example, the transparent conductive oxide may include Indium Tin Oxide (ITO), tin oxide (SnO), zinc oxide (ZnO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), other suitable transparent conductive materials, or a combination thereof, but is not limited thereto.

In addition, according to some embodiments, the phase-shift electrode 104 may be further electrically connected to a driving element (not shown). In some embodiments, the drive elements may include active drive elements (e.g., thin-film transistors (TFTs)), passive drive elements, or a combination of the foregoing. Specifically, in some embodiments, the phase-shift electrodes 104 may be electrically connected to thin film transistors, and the thin film transistors may be further electrically connected to data lines and/or scan lines (gate lines). In some embodiments, phase-shifting electrodes 104 may be electrically connected to an Integrated Circuit (IC) and/or a digital-to-analog converter.

Furthermore, the electronic device 10A may include a patch (patch)204, and the patch 204 may be disposed on the phase-shift electrode 104. In some embodiments, patch 204 may partially overlap phase-shifting electrode 104 in a direction normal to first substrate 102 (e.g., the Z direction). Further, in some embodiments, patch 204 may overlap with an end of phase-shifting electrode 104 in a normal direction (e.g., Z direction) of first substrate 102, but is not limited thereto. In another embodiment, patch 204 may not overlap the end of phase-shifting electrode 104, but may overlap other portions of phase-shifting electrode 104. In some embodiments, the patch 204 may be electrically floating (floated), coupled to a fixed potential (e.g., ground), or other functional circuitry, although the invention is not limited thereto.

In some embodiments, the material of the patch 204 may comprise a metallic conductive material, a transparent conductive material, or a combination of the foregoing. The metal conductive material and the transparent conductive material are similar to the material of the phase-shift electrode 104, and are not described herein again.

Next, referring to fig. 2, fig. 2 is a schematic perspective view illustrating a partial structure of an electronic device 10A according to some embodiments of the present disclosure. It should be understood that fig. 2 only shows some elements of the modulation unit 100A of fig. 1 for clarity of illustration. As shown in fig. 2, in some embodiments, the modulation unit 100A may include a first substrate 102, and a feed line 400B and a phase-shift electrode 104 disposed on the first substrate 102. In some embodiments, as shown in FIG. 2, an end of the feed line 400B may correspond to an end of the phase-shifting electrode 104, but the invention is not limited thereto.

Furthermore, in some embodiments, the modulation unit 100A may further include a second substrate 202, a patch 204, and a common electrode layer 208, the second substrate 202 may be disposed opposite to the first substrate 102, and the common electrode layer 208 and the patch 204 may be disposed between the first substrate 102 and the second substrate 202.

In some embodiments, the material of the second substrate 202 may be similar to the material of the first substrate 102, and is not repeated herein. In addition, the material of the second substrate 202 may be the same as or different from the material of the first substrate 102.

In addition, according to some embodiments, the first substrate 102 and the second substrate 202 may be flexible substrates, so as to improve the overall flexibility or plasticity of the electronic device 10A, and facilitate the mounting on the surface of various articles, such as an automobile, a locomotive, an airplane, a ship, a building, or other suitable articles, but the invention is not limited thereto.

Furthermore, as shown in fig. 2, the common electrode layer 208 may have an opening 208p, and the patch 204 partially overlaps the opening 208p in the normal direction Z of the first substrate 102. Furthermore, in some embodiments, the end of phase-shifting electrode 104 may overlap opening 208p, but is not limited thereto. According to some embodiments, the transmission direction or other parameters of the electromagnetic wave signals passing through the opening 208p and the patch 204 can be controlled by applying different electric fields to the modulating material (e.g., the liquid crystal layer 300 in subsequent figures) in the modulating unit 100A to adjust the capacitance and/or phase difference. The detailed structure of the electronic device 10A is further described below.

Referring to fig. 3, fig. 3 is a cross-sectional view of an electronic device 10A according to some embodiments of the invention, and particularly, fig. 3 is a cross-sectional view of a modulation unit 100A along a sectional line a-a' in fig. 1. In light of the foregoing, the electronic device 10A includes the first substrate 102 and the second substrate 202. In detail, the first substrate 102 is disposed opposite to the second substrate 202, the first substrate 102 has an inner side 102a facing the second substrate 202 and an outer side 102b opposite to the inner side 102a, and similarly, the second substrate 202 has an inner side 202a facing the first substrate 102 and an outer side 202b opposite to the inner side 202 a.

Furthermore, the first substrate 102 may have a first thickness T₁The second substrate 202 may have a second thickness T₂. In some embodiments, the first thickness T of the first substrate 102₁May be greater than or equal to the second thickness T of the second substrate 202₂. Notably, according to some embodiments, the second thickness T₂May be less than the first thickness T₁Since the second substrate 202 is the main substrate through which the electromagnetic wave signal passes, the dielectric loss of the electromagnetic wave radiated from the patch 204 to the outside or the electromagnetic wave going into the patch 204 from the outside can be reduced, but not limited thereto.

Furthermore, according to the embodiment of the present invention, the first thickness T of the first substrate 102₁And a second thickness T of the second substrate 202₂Respectively, the maximum thickness of the first substrate 102 and the second substrate 202 in the normal direction Z of the first substrate 102.

In addition, according to the embodiments of the present invention, the thickness, width, or distance between elements may be measured using an Optical Microscope (OM), a Scanning Electron Microscope (SEM), a thin film thickness profile (α -step), an ellipsometer, or other suitable means. In detail, in some embodiments, after removing the liquid crystal layer 300, any cross-sectional image of the structure may be obtained by using a scanning electron microscope, and the thickness, width or distance between the elements in the image may be measured.

In some embodiments, as shown in FIGS. 2 and 3, phase-shifting electrodes 104 can be disposed on the inner side 102a of the first substrate 102. In some embodiments, the patches 204 may be disposed on the inner side 202a of the second substrate 202. In light of the foregoing, in some embodiments, patch 204 may overlap phase-shifting electrode 104 in a normal direction Z of first substrate 102.

In addition, the electronic device 10A may include a dielectric layer 206 and a common electrode layer 208 disposed between the first substrate 102 and the second substrate 202. As shown in fig. 3, the dielectric layer 206 may be disposed between the common electrode layer 208 and the second substrate 202 and disposed on the patch 204. For example, the patch 204 may be disposed between the second substrate 202 and the dielectric layer 206. Specifically, the dielectric layer 206 may be disposed adjacent to the second substrate 202, and the dielectric layer 206 has an inner side 206a facing the first substrate 102 and an outer side 206b opposite the inner side 206 a. In some embodiments, patch 204 may be adjacent to outer side 206b of dielectric layer 206 and common electrode layer 208 may be adjacent to inner side 206a of dielectric layer 206, and dielectric layer 206 may separate patch 204 and common electrode layer 208 from each other.

In some embodiments, the material of the dielectric layer 206 may include an organic material, an inorganic material, or a combination of the foregoing materials, but is not limited thereto. In some embodiments, the organic material may include Polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), liquid-crystal polymer (LCP) material, Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), isoprene (isoprene), phenol-formaldehyde resin (phenol-formaldehyde resin), benzocyclobutene (BCB), Perfluorocyclobutane (PECB), other suitable materials, or a combination thereof. In some embodiments, the inorganic material may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, other suitable materials, or a combination thereof, but is not limited thereto.

As shown in fig. 3, in some embodiments, the dielectric layer 206 may have a single-layer structure. However, in other embodiments, the dielectric layer 206 may have a multi-layer structure. Specifically, according to some embodiments, the number of the multi-layered structure of the dielectric layer 206 may be between 2 and 50 layers (2 and 50), between 2 and 40 layers, between 3 and 30 layers, between 4 and 20 layers, or between 5 and 15 layers, such as, but not limited to, 6 layers, 7 layers, 8 layers, 9 layers, 10 layers, 11 layers, 12 layers, 13 layers, or 14 layers. In some embodiments, each level of the dielectric layer 206 having a multi-layer structure may be formed of the same or different material, or may be formed of partially the same and partially different layers. Furthermore, in some embodiments, the dielectric layer 206 may comprise at least one polyimide film, but is not limited thereto.

According to some embodiments, the dielectric layer 206 may have a multi-layer structure, and the material of the layer closest to the common electrode layer 208 (or the layer in contact with the common electrode layer 208) may include silicon oxide, silicon nitride, other suitable materials, or a combination of the foregoing materials, but is not limited thereto. In these embodiments, the difference in Coefficient of Thermal Expansion (CTE) between the dielectric layer 206 and the common electrode layer 208 can be reduced, thereby improving the warpage problem of the second substrate 202.

Furthermore, the dielectric layer 206 may have a third thickness T₃. In some embodiments, the third thickness T of the dielectric layer 206₃May be greater than or equal to 5 micrometers (μm) and less than or equal to the second thickness T of the second substrate 202₂(i.e., 5 μm ≦ third thickness T₃A second thickness T ≦₂). In some embodiments, the third thickness T of the dielectric layer 206₃Can be greater than or equal to 0.01 times and less than or equal to 1 times of the wavelength λ of the electromagnetic wave modulated by the electronic device 10A (i.e., 0.01 λ ≦ the third thickness T₃≦ λ), such as 0.05 λ, 0.1 λ, 0.3 λ, 0.5 λ, 0.7 λ, or 0.9 λ, for example, the third thickness T₃Can be between 0.02 times and 0.5 times of the wavelength λ of the electromagnetic wave modulated by the electronic device 10A (0.02 λ ≦ T₃≦0.5λ)。

It should be understood that if the third thickness T of the dielectric layer 206 is provided₃Too small (e.g., less than 5 μm or 0.01 times λ), it may result in too small a distance between the patch 204 and the common electrode layer 208, resulting in a decrease in the radiation efficiency of electromagnetic waves; on the other hand, if the third thickness T of the dielectric layer 206 is smaller than the first thickness T₃Is too large (e.g., greater than the second thickness T)₂Or 1 x lambda), the strength of the induced electromagnetic field may be insufficient to achieve radiation.

Furthermore, according to the embodiment of the present invention, the "third thickness T" of the dielectric layer 206₃"refers to the maximum thickness of the dielectric layer 206 in the normal direction Z of the first substrate 102.

In light of the foregoing, the electronic device 10A includes the common electrode layer 208, and as shown in fig. 3, the common electrode layer 208 may be patterned to have an opening 208p, which may expose a portion of the inner side 206a of the dielectric layer 206. Furthermore, the opening 208p may correspond to the patch 204, for example, the patch 204 may overlap the opening 208p in the normal direction Z of the first substrate 102. In addition, in some embodiments, the common electrode layer 208 may be electrically grounded. In one embodiment, common electrode layer 208 may be patterned at the end of the corresponding phase-shifting electrode 104 to form coplanar waveguide 203 (shown in FIG. 1).

In some embodiments, the material of the common electrode layer 208 may include a metallic conductive material, a transparent conductive material, or a combination of the foregoing. The metal conductive material and the transparent conductive material may be similar to the material of the phase-shift electrode 104, and are not described herein again.

As shown in FIG. 3, in some embodiments, the patch 204 may have a first width W₁The opening 208p of the common electrode layer 208 may have a second width W₂. In some embodiments, in the first direction (e.g., the X direction), the second width W of the opening 208p₂May be greater than or equal to the first width W of the patch 204₁(ii) a In a second direction (e.g., the Y direction), the width of the opening 208p may be less than or equal to the width W of the patch 204, thereby facilitating the passage of electromagnetic wave signals through the opening 208p and to the patch 204. The first direction may be different from the second direction, for example, the first direction may be substantially perpendicular to the second direction.

It is understood that the first direction may be an extending direction of the opening 208p according to some embodiments of the present invention, but is not limited thereto. In addition, the first direction may be a length direction of the opening 208p, but is not limited thereto. According to some embodiments of the invention, the "lengthwise direction" refers to a direction along or substantially parallel to the long axis of the object. While the long axis may be closest to its maximum dimension in the longitudinal direction (length). For objects that do not have a definite long axis, the long axis may represent the long side of the smallest rectangle that may surround the object.

As shown in fig. 3, according to some embodiments, the patches 204 and the common electrode layer 208 may be disposed on the inner side 202a of the second substrate 202, in other words, the patches 204 and the common electrode layer 208 are disposed on the same side of the second substrate 202, but not limited thereto.

It is noted that in the electronic device having the patches 204 and the common electrode layer 208 respectively disposed on two sides of the second substrate 202, a long time of high temperature metal plating process (such as a back plating process) is required, which may increase the risks of degradation of the modulation material or substrate cracking due to the high temperature process. According to some embodiments of the present invention, the patches 204 and the common electrode layer 208 disposed on a single side of the second substrate 202 can reduce the risks of degradation of the modulation material or substrate cracking due to high temperature processes. A detailed manufacturing method of the electronic device 10A will be described later.

In addition, referring to FIG. 3, the electronic device 10A includes a liquid crystal layer 300, wherein the liquid crystal layer 300 is disposed between the first substrate 102 and the second substrate 202, and the liquid crystal layer 300 is disposed between the phase-shifting electrode 104 and the common electrode layer 208. As mentioned above, according to some embodiments, the transmission direction of the electromagnetic signal passing through the opening 208p and the patch element 204 can be controlled by applying different electric fields to the liquid crystal layer 300 to adjust the capacitance and the phase difference.

In some embodiments, the material of the liquid crystal layer 300 may include nematic (nematic) liquid crystal, smectic (cholesteric) liquid crystal, cholesteric (cholesteric) liquid crystal, blue-phase (blue-phase) liquid crystal, other suitable liquid crystal material, or a combination of the foregoing materials, but is not limited thereto. However, according to other embodiments, a material having a property that the refractive index can be modulated may be used instead of the liquid crystal layer 300, for example, a transition metal nitride, an electro-optic material (electro-optic material), or a combination of the foregoing, but is not limited thereto. For example, the photovoltaic material may comprise lithium niobate (LiNbO)₃) Lithium tantalate (LiTaO)₃) Cadmium telluride (CdTe), ammonium dihydrogen phosphate (NH)₄H₂PO₄) Potassium dihydrogen phosphate (KH)₂PO₄) Potassium tantalate niobate (KTN), lead zirconate titanate (PZT), transition metal nitrides such as TiN, HfN, TaN, or ZrN, or combinations of the foregoing, but not limited thereto. In one embodiment, the liquid crystal layer 300 may include isothiocyanate, or other high polarity functional groups, but is not limited thereto.

Referring to fig. 3, in some embodiments, the electronic device 10A may further include a first buffer layer 106, and the first buffer layer 106 may be disposed between the first substrate 102 and the phase-shift electrode 104. For example, in some embodiments, the first buffer layer 106 may be in contact with the inner side 102a of the first substrate 102 and the phase-shift electrode 104. The first buffer layer 106 can reduce the difference in thermal expansion coefficient between the first substrate 102 and the phase-shift electrode 104, thereby improving the warpage problem of the first substrate 102.

In some embodiments, the electronic device 10A may further include a second buffer layer 210, and the second buffer layer 210 may be disposed between the second substrate 202 and the patch 204. In some embodiments, the second buffer layer 210 may be in contact with the inner side 202a of the second substrate 202, the patches 204, and the dielectric layer 206. The second buffer layer 210 can reduce the difference in thermal expansion coefficient between the second substrate 202 and the patches 204, thereby improving the warpage problem of the second substrate 202.

In some embodiments, the first buffer layer 106 and the second buffer layer 210 may include an insulating material. In some embodiments, the materials of the first buffer layer 106 and the second buffer layer 210 may include organic materials, inorganic materials, or a combination of the foregoing, but are not limited thereto. In some embodiments, the organic material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), isoprene (isopene), phenol-formaldehyde resin (phenol-formaldehyde resin), benzocyclobutene (BCB), Perfluorocyclobutane (PECB), or a combination thereof, but is not limited thereto. In some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide (AlOx), titanium oxide (TiOx), or a combination thereof, but is not limited thereto. Furthermore, the material of the first buffer layer 106 may be the same as or different from the material of the second buffer layer 210.

Furthermore, the first buffer layer 106 and the second buffer layer 210 may have a single-layer structure or a multi-layer structure, and may include a plurality of sub-layers (sublayers), for example. In embodiments where the first buffer layer 106 or the second buffer layer 210 includes multiple sub-layers, the materials of the sub-layers may be the same or different.

In addition, in some embodiments, the electronic device 10A may further include a circuit layer 110 (see fig. 11F), and the circuit layer 110 may be disposed between the first substrate 102 and the phase-shift electrode 104. In some embodiments, the circuit layer 110 may include a driving device (e.g., a thin film transistor), a signal line electrically connected to the driving device, and the like. The signal lines may include data lines, scanning lines (gate lines), and the like.

With continued reference to FIG. 3, in some embodiments, the electronic device 10A may further include a first alignment layer 108, and the first alignment layer 108 may be disposed between the phase-shift electrode 104 and the liquid crystal layer 300. In some embodiments, the first alignment layer 108 may be disposed between the first buffer layer 106 and the liquid crystal layer 300. In some embodiments, as shown in FIG. 3, the first alignment layer 108 may be conformally (conformally) formed on the first buffer layer 106 and the phase-shift electrode 104, but is not limited thereto.

Furthermore, in some embodiments, the electronic device 10A may further include a second alignment layer 212, and the second alignment layer 212 may be disposed between the common electrode layer 208 and the liquid crystal layer 300. In some embodiments, the second alignment layer 212 may be disposed between the dielectric layer 206 and the liquid crystal layer 300. As shown in fig. 3, in some embodiments, the second alignment layer 212 may be conformably (conformamally) formed on the common electrode layer 208 and the dielectric layer 206, but is not limited thereto. In some embodiments, the second alignment layer 212 may also extend (or be disposed) in the opening 208 p.

In some embodiments, the first alignment layer 108 and the second alignment layer 212 may assist in controlling the alignment direction of the liquid crystal molecules in the liquid crystal layer 300. In some embodiments, the materials of the first alignment layer 108 and the second alignment layer 212 may comprise organic materials, inorganic materials, or a combination thereof. For example, the organic material may include Polyimide (PI), a photoreactive polymer material, or a combination thereof, but is not limited thereto. The aforementioned inorganic material may comprise, for example, silicon dioxide (SiO)₂) Other materials with alignment function, or combinations of the foregoing, but not limited thereto. In other embodiments, at least one of the first alignment layer 108 and the second alignment layer 212 may be omitted, but is not limited thereto.

Next, referring to fig. 4, fig. 4 is a schematic cross-sectional view illustrating an electronic device 10B according to another embodiment of the invention. It should be understood that the same or similar components or elements are denoted by the same or similar reference numerals, and the same or similar materials, manufacturing methods and functions are the same or similar to those described above, so that the detailed description thereof will not be repeated.

The electronic device 10B shown in fig. 4 is substantially similar to the electronic device 10A shown in fig. 3, and the difference is that in the electronic device 10B, the second substrate 202 may be locally thinned. Specifically, in this embodiment, the second substrate 202 may have a recess 202r, and the recess 202r may correspond to the patch 204. In some embodiments, the recess 202r may overlap the patch 204 in the normal direction Z of the first substrate 102.

In some embodiments, the recess 202r may be recessed from the outer side 202b of the second substrate 202 toward the inner side 202a by a first distance d₁A first distance d₁Which may be considered the depth of the recess 202 r. In some embodiments, the first distance d₁May be smaller than the second thickness T of the second substrate 202₂. In some embodiments, the first distance d₁May be equal to the second thickness T of the second substrate 202₂That is, an opening is formed through the second substrate 202 and exposes the second buffer layer 210 or the dielectric layer 206.

Furthermore, the recess 202r may have a third width W₃. In some embodiments, the third width W of the recess 202r₃May be greater than or equal to the first width W of the patch 204₁. According to some embodiments of the invention, the third width W₃Refers to the maximum width of the recess 202r in the X direction on any cross section. Also, in some embodiments, the area of the recess 202r may be greater than or equal to the area of the patch 204. According to some embodiments of the present invention, the aforementioned areas refer to the bottom areas of the recess 202r and the patch 204.

It is noted that according to some embodiments, the second substrate 202 having a smaller thickness at the position corresponding to the patch 204 can further reduce the dielectric loss of the electromagnetic wave. Furthermore, it should be understood that although the drawings only illustrate the second substrate 202 as being partially thinned, the second substrate 202 may be thinned entirely according to other embodiments.

In addition, as shown in fig. 4, in some embodiments, the electronic device 10B may further include a protection layer 214, and the protection layer 214 may be disposed (or filled) in the recess 202 r. In some embodiments, the top surface 214t of the protective layer 214 may be lower than the outer side 202b of the second substrate 202. In other embodiments, the top surface 214t of the protective layer 214 may be substantially flush with the outer side 202b of the second substrate 202. In one embodiment, the dielectric constant of the protection layer 214 may be different from the dielectric constant of the second substrate 202, for example, the dielectric constant of the protection layer 214 is smaller than or equal to the dielectric constant of the second substrate 202. When the dielectric constant of the protection layer 214 is less than or equal to that of the second substrate, the dielectric loss of the electromagnetic wave can be reduced, but is not limited thereto.

In some embodiments, the material of the protection layer 214 may include Polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), liquid-crystal polymer (LCP) material, Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), isoprene (isoprene), phenol-formaldehyde resin (phenol-formaldehyde resin), benzocyclobutene (BCB), Perfluorocyclobutane (PECB), or a combination thereof, but is not limited thereto.

Referring to fig. 5, fig. 5 is a schematic cross-sectional view of an electronic device 10C according to another embodiment of the invention. The electronic device 10C shown in fig. 5 is substantially similar to the electronic device 10A shown in fig. 3, except that the electronic device 10C may not have the second substrate 202. In this embodiment, the electronic device 10C may not have the second buffer layer 210. In other words, in this embodiment, the outer side 206b of the dielectric layer 206 and the top surface 204t of the patch 204 may be exposed to the environment.

In detail, in this embodiment, the electronic device 10C includes the first substrate 102, the phase-shift electrode 104, the dielectric layer 206, the patch 204, the common electrode layer 208, the liquid crystal layer 300, the first alignment layer 108, and the second alignment layer 212. Furthermore, phase-shift electrodes 104 may be disposed on first substrate 102, dielectric layer 206 may be disposed on phase-shift electrodes 104, patches 204 may be disposed in dielectric layer 206, and common electrode layer 208 may be disposed between dielectric layer 206 and first substrate 102. In addition, the liquid crystal layer 300 may be disposed between the phase-shift electrode 104 and the dielectric layer 206, the first alignment layer 108 may be disposed between the phase-shift electrode 104 and the liquid crystal layer 300, and the second alignment layer 212 may be disposed between the common electrode layer 208 and the liquid crystal layer 300.

According to some embodiments, the electronic device 10C without the second substrate 202 can reduce the thickness of the whole structure. Furthermore, in some embodiments, the electronic device 10C may not have the first substrate 102, and a protection layer may be optionally disposed below the first buffer layer 106. Thus, the electronic device 10C may be more flexible or plastic, facilitating mounting on various surfaces of devices.

Referring to fig. 6, fig. 6 is a schematic cross-sectional view of an electronic device 10D according to another embodiment of the invention. The electronic device 10D shown in fig. 6 is substantially similar to the electronic device 10C shown in fig. 5, except that the electronic device 10D may further include a cover layer 216, and the cover layer 216 may be in contact with the patch 204. The dielectric layer 206 may be disposed between the cap layer 216 and the common electrode layer 208. In this embodiment, a cover layer 216 may be disposed on the outer side 206b of the dielectric layer 206 to provide protection for the patch 204.

In some embodiments, the material of the cap layer 216 may be similar to the material of the protection layer 214, and is not described herein again.

Referring to fig. 7, fig. 7 is a schematic cross-sectional view of an electronic device 10E according to another embodiment of the invention. The electronic device 10E shown in fig. 7 is substantially similar to the electronic device 10A shown in fig. 3, with the difference that the dielectric layer 206 may be locally thinned in the electronic device 10E. Specifically, in this embodiment, the dielectric layer 206 may further include a recess 206r, and the recess 206r may correspond to the patch 204. In some embodiments, the recess 206r may overlap the patch 204 in the normal direction Z of the first substrate 102.

In some embodiments, the recess 206r may be recessed from the inner side 206a toward the outer side 206b of the dielectric layer 206. In some embodimentsThe thinned dielectric layer 206 (corresponding to the dielectric layer 206 at the recess 206 r) may have a thickness T_3a. In some embodiments, the thickness T_3aIs less than the third thickness T of the dielectric layer 206₃. Furthermore, according to embodiments of the present invention, the "thickness T" is_3a"refers to the minimum thickness in the normal direction Z of the first substrate 102 in the thinned region of the dielectric layer 206. In one embodiment, the thickness T_3aMay be a minimum thickness where there is no overlap with the patch 204.

Furthermore, the recess 206r may have a fourth width W₄. In some embodiments, the fourth width W of the recess 206r₄May be greater than or equal to the first width W of the patch 204₁. According to some embodiments of the invention, the fourth width W₄May refer to the maximum width of the recess 206r in any cross-section parallel to the recess direction of the opening 208p (e.g., the X direction as shown in the figure, but also refer to fig. 2). Furthermore, in some embodiments, the area of the recess 206r may be greater than or equal to the area of the patch 204. According to some embodiments of the present invention, the aforementioned areas refer to the top or bottom areas of the recess 206r and the patch 204.

It is noted that, according to some embodiments, the dielectric layer 206 having the recess 206r at a location corresponding to the patch 204 may improve electromagnetic radiation signals in the electronic device 10E.

Furthermore, as shown in FIG. 7, in some embodiments, the second width W of the opening 208p of the common electrode layer 208₂May be greater than the fourth width W of the recess 206r₄. In some embodiments, the recess 206r may also overlap the opening 208p in the normal direction Z of the first substrate 102. In some embodiments, the opening 208p and the recess 206r may form a stepped recess structure. In some embodiments, the second alignment layer 212 may conformably extend into the opening 208p and the recess 206r, forming the second alignment layer 212 with a step-like structure. In these embodiments, the stepped recess structure formed by the opening 208p and the recess 206r can reduce the probability of the second alignment layer 212 being damaged or deteriorated.

Referring to fig. 8, fig. 8 is a schematic cross-sectional view of an electronic device 10F according to another embodiment of the invention. The electronic device 10F shown in fig. 8 is substantially similar to the electronic device 10E shown in fig. 7, except that in the electronic device 10F, the dielectric layer 206 may be locally thinned to expose at least a portion of the patch 204. Specifically, in this embodiment, the dielectric layer 206 may include an opening 206p, and the opening 206p may correspond to the patch 204. In some embodiments, the opening 206p may overlap the patch 204 in the normal direction Z of the first substrate 102. Further, in this embodiment, the opening 206p may expose at least a portion of the patch 204.

In some embodiments, the opening 206p may extend from the inner side 206a of the dielectric layer 206 in a direction toward the outer side 206 b. In some embodiments, the thinned dielectric layer 206 (corresponding to the dielectric layer 206 at the opening 206p) may have a thickness T_3b. In some embodiments, the thickness T_3bMay be less than the third thickness T of the dielectric layer 206₃. In this embodiment, the thickness T_3bSubstantially equal to the thickness (not labeled) of the patch 204. Furthermore, according to embodiments of the present invention, the "thickness T" is_3b"refers to the minimum thickness of the thinned region of the dielectric layer 206 in the normal direction Z of the first substrate 102. In one embodiment, the thickness T_3bMay be a minimum thickness where there is no overlap with the patch 204.

In addition, the opening 206p may have a fifth width W₅. In some embodiments, the fifth width W of the opening 206p₅May be greater than or equal to the first width W of the patch 204₁. According to some embodiments of the invention, the fifth width W₅May be the maximum width of the opening 206p in any cross-section parallel to the extending direction of the opening 208p (e.g., the X-direction as shown in the figure, see also fig. 2). Also, in some embodiments, the area of the opening 206p may be greater than or equal to the area of the patch 204. According to some embodiments of the present invention, the aforementioned areas refer to the top or bottom areas of the finger opening 206p and the patch 204.

It is noted that, according to some embodiments, having the opening 206p of the dielectric layer 206 at a location corresponding to the patch 204 may improve electromagnetic radiation signals in the electronic device 10F.

Further, as shown in FIG. 8, in some embodiments, allWith the second width W of the opening 208p of the electrode layer 208₂May be greater than the fifth width W of the opening 206p₅. In some embodiments, the opening 206p may also overlap with the opening 208p in the normal direction Z of the first substrate 102. In some embodiments, the

openings

208p and 206p may form a stepped recess structure. In some embodiments, the second alignment layer 212 may conformably extend into the

openings

208p and 206p, forming a second alignment layer 212 with a stepped structure.

Next, referring to fig. 9, fig. 9 is a schematic cross-sectional view of an electronic device 10G according to another embodiment of the invention. The electronic device 10G shown in fig. 9 is substantially similar to the electronic device 10A shown in fig. 3, except that in the electronic device 10G, a portion of the second buffer layer 210 is removed to form an opening 210p, and the patch 204 may be disposed in the opening 210 p. In detail, in this embodiment, the opening 210p may overlap with the patch 204 in the normal direction Z of the first substrate 102. Furthermore, in this embodiment, the second buffer layer 210 may not overlap with the patch 204 in the normal direction Z of the first substrate 102. In this embodiment, the patch 204 may be in contact with the inner side 202a of the second substrate 202.

As shown in fig. 9, the second buffer layer 210 is spaced apart from the patch 204 by a second distance d₂. In some embodiments the second distance d₂Can range from 1 μm to 100 μm (1 μm ≦ second distance d₂≦ 100 μm), or between 2 μm and 50 μm, for example 5 μm, 10 μm, 20 μm, 40 μm, 60 μm, or 80 μm. It will be appreciated that if the second distance d is provided₂If the size is too large, the coverage rate of the buffer layer 210 is low, and the difference between the expansion coefficients is difficult to reduce; on the contrary, if the second distance d₂Too small, the patch 204 is not easily disposed within the opening 210 p.

It is noted that, according to some embodiments, the second buffer layer 210 may not be disposed at a position corresponding to the patch 204, thereby improving electromagnetic radiation signals in the electronic device 10G.

Referring to fig. 10, fig. 10 is a schematic cross-sectional view of an electronic device 10H according to another embodiment of the invention. The electronic device 10H shown in fig. 10 is substantially similar to the electronic device 10A shown in fig. 3, except that in the electronic device 10H, the dielectric layer 206 may further include a plurality of holes 206e disposed therein. In this embodiment, the dielectric layer 206 may include holes 206e, and the holes 206e may be used to accommodate gases generated by the electronic device 10H in a high temperature operating environment, thereby improving the operational reliability of the electronic device 10H.

Specifically, aperture 206e may have a diameter D_p. In some embodiments, diameter D_pCan range from 0.1 μm to 100 μm (1 μm ≦ diameter D_p≦ 100 μm), between 0.5 μm and 90 μm, between 5 μm and 80 μm, or between 10 μm and 70 μm, for example 10 μm, 25 μm, 40 μm, or 60 μm. According to some embodiments of the invention, diameter D_pMay refer to the maximum width of the hole 206e in any cross-section parallel to the extending direction of the opening 208p (e.g., the X-direction as shown in the figure, see also fig. 2).

Referring to fig. 11A to 11H, fig. 11A to 11H are schematic cross-sectional views of an electronic device 10A at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure. It should be understood that additional operational steps may be provided before, during, and/or after the fabrication process for the electronic device 10A, according to some embodiments. According to some embodiments, some of the described operational steps may be replaced or deleted. According to some embodiments, the order of the operational steps is interchangeable.

First, referring to fig. 11A, a first substrate 102 is provided, and then a phase-shift electrode 104 is formed on the first substrate 102. In detail, in some embodiments, the phase-shifting electrode 104 may be formed by first forming a conductive material on the first substrate 102 and then removing a portion of the conductive material to pattern the conductive material.

In some embodiments, the phase-shifting electrode 104 may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. The physical vapor deposition process may include, but is not limited to, a sputtering process, an evaporation process, or a pulsed laser deposition. The chemical vapor deposition process may include, but is not limited to, a low pressure chemical vapor deposition process (LPCVD), a low temperature chemical vapor deposition process (LTCVD), a rapid thermal chemical vapor deposition process (RTCVD), a plasma enhanced chemical vapor deposition Process (PECVD), or an atomic layer deposition process (ALD).

In some embodiments, a portion of the conductive material may be removed by a patterning process to form phase-shifting electrodes 104. In some embodiments, the patterning process may include a photolithography process and an etching process. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include, but is not limited to, a dry etching process or a wet etching process.

As shown in FIG. 11A, in some embodiments, a first buffer layer 106 may be further formed on the first substrate 102 before forming the phase-shifting electrode 104 on the first substrate 102, and the first buffer layer 106 may be in contact with the first substrate 102.

In some embodiments, the first buffer layer 106 may be formed by the above-mentioned physical vapor deposition process, the above-mentioned chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

Furthermore, in some embodiments, the circuit layer 110 may be formed on the first buffer layer 106 before the phase-shift electrode 104 is formed on the first substrate 102. As shown in FIG. 11A, a circuit layer 110 can be formed between the first substrate 102 and the phase-shift electrode 104.

In some embodiments, the circuit layer 110 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the circuit layer 110 may be patterned by one or more photolithography processes and etching processes.

As shown in FIG. 11A, in some embodiments, after forming phase-shift electrode 104 on first substrate 102, a first alignment layer 108 can be further formed on phase-shift electrode 104. In some embodiments, the first alignment layer 108 may be conformally formed on the phase-shift electrode 104.

In some embodiments, the first alignment layer 108 may be formed by the above-mentioned pvd process, the above-mentioned cvd process, a coating process, a printing process, other suitable processes, or a combination thereof.

Next, referring to fig. 11B, a second substrate 202 is provided, and a patch 204 is formed on the second substrate 202. In detail, in some embodiments, the conductive material may be formed on the second substrate 202, and then a portion of the conductive material is removed to pattern the conductive material to form the patch 204.

In some embodiments, the patch 204 may be formed by a physical vapor deposition process, a chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Further, the patch 204 may be patterned by one or more photolithography processes and etching processes. In some embodiments, the photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. In some embodiments, the etching process may include, but is not limited to, a dry etching process or a wet etching process.

As shown in fig. 11B, in some embodiments, a second buffer layer 210 may be further formed on the second substrate 202 before the patches 204 are formed on the second substrate 202, and the second buffer layer 210 may be in contact with the second substrate 202.

In some embodiments, the second buffer layer 210 may be formed by the above-mentioned physical vapor deposition process, the above-mentioned chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

Next, referring to fig. 11C, a dielectric layer 206 is formed on the patch 204, and the dielectric layer 206 is also formed on the second substrate 202. As shown in fig. 11C, in some embodiments, the dielectric layer 206 may be in contact with the patch 204 and the second buffer layer 210.

In some embodiments, the dielectric layer 206 may be formed by a physical vapor deposition process, a chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

Next, referring to fig. 11D, a common electrode layer 208 is formed on the dielectric layer 206, and the dielectric layer 206 is located between the common electrode layer 208 and the second substrate 202. Specifically, in some embodiments, the common electrode layer 208 may be patterned to have openings 208 p. As mentioned above, the patch 204 may have a first width W₁The opening 208p of the common electrode layer 208 may have a second width W₂In some embodiments, the second width W₂May be greater than or equal to the first width W₁。

In some embodiments, the common electrode layer 208 may be formed by the aforementioned physical vapor deposition process, the aforementioned chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the common electrode layer 208 may be patterned by one or more photolithography processes and etching processes.

Next, referring to fig. 11E, in some embodiments, after forming the common electrode layer 208 on the dielectric layer 206, a second alignment layer 212 may be further formed on the common electrode layer 208. In some embodiments, the second alignment layer 212 may be conformally formed on the common electrode layer 208 and conformally extend (or be disposed) in the opening 208 p.

In some embodiments, the second alignment layer 212 may be formed by the above-mentioned physical vapor deposition process, the above-mentioned chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

Next, referring to fig. 11F, the first substrate 102 and the second substrate 202 are combined, so that the patches 204 are located on the inner side 202a of the second substrate 202, and the inner side 202a faces the first substrate 102. Furthermore, a liquid crystal layer 300 is formed between the first substrate 102 and the second substrate 202, and the liquid crystal layer 300 can be located between the phase-shift electrode 104 and the common electrode layer 208.

In some embodiments, the liquid crystal layer 300 may be formed by One Drop Filling (ODF) before the first substrate 102 and the second substrate 202 are assembled, or the liquid crystal may be filled by vacuum filling after the assembly, but the invention is not limited thereto.

Next, referring to fig. 11G and 11H, in some embodiments, after the liquid crystal layer 300 is formed between the first substrate 102 and the second substrate 202, the second substrate 202 may be selectively removed to form the electronic device 10K. In some embodiments, the second buffer layer 210 may be exposed to the environment after removing the second substrate 202. In some embodiments, the second buffer layer 210 may also be removed. In addition, after removing the second substrate 202 and/or the second buffer layer 210, a protection layer (not shown) may be formed on the patch 204 and the dielectric layer 206.

Referring to fig. 12A to 12F, fig. 12A to 12F are schematic cross-sectional views illustrating an electronic device 10E at an intermediate stage of a manufacturing process according to other embodiments of the present disclosure.

Fig. 12A and 12B are similar to fig. 11A and 12B, and are not repeated herein. Next, referring to fig. 12C, a dielectric layer 206 is formed on the patch 204, and the dielectric layer 206 is also formed on the second substrate 202. As shown in fig. 11C, in some embodiments, the dielectric layer 206 may be in contact with the patch 204 and the second buffer layer 210. In some embodiments, after forming the dielectric layer 206 on the patch 204, a portion of the dielectric layer 206 may be removed, and the removed portion of the dielectric layer 206 may correspond to the patch 204.

Specifically, in some embodiments, after forming the dielectric layer 206 on the patch 204, a portion of the dielectric layer 206 may be removed to form the recess 206 r. For example, the recess 206r may be formed after the development etching step by exposing through a halftone dot mask (half-tone mask) or a gray scale mask (gray tone mask). In some embodiments, the recess 206r may overlap the patch 204 in the normal direction Z of the first substrate 102. In addition, following the foregoing, the recess 206r may have a fourth width W₄. In some embodiments, the fourth width W of the recess 206r₄May be greater than or equal to the first width W of the patch 204₁。

In some embodiments, the dielectric layer 206 may be formed by a physical vapor deposition process, a chemical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof. Further, the dielectric layer 206 may be patterned by one or more photolithography processes and etching processes to form the recess 206 r. In other embodiments, instead of the recess 206r, an opening 206p as shown in fig. 8 may be formed to expose at least a portion of the patch 204.

Next, referring to fig. 12D, a common electrode layer 208 is formed on the dielectric layer 206, and the dielectric layer 206 is located between the common electrode layer 208 and the second substrate 202. Specifically, in some embodiments, the common electrode layer 208 may be patterned to have openings 208 p. In some embodiments, the second width W of the opening 208p of the common electrode layer 208₂May be greater than or equal to the first width W of the patch 204₁. Furthermore, in some embodiments, the second width W of the opening 208p₂May be greater than or equal to the fourth width W of the recess 206r₄. In other embodiments, the opening 208p and the recess 206r (or the opening 206p) may be formed sequentially after the dielectric layer 206 and the common electrode layer 208 are formed, but not limited thereto.

It is noted that, in some embodiments, the second width W of the opening 208p₂Is greater than the fourth width W of the recess 206r₄The

openings

208p and 206p are thus formed as a stepped recess structure, thereby reducing the risk of filling the common electrode layer 108 into the openings 206p due to process tolerance, or reducing the process difficulty.

In some embodiments, the common electrode layer 208 may be formed by the aforementioned physical vapor deposition process, the aforementioned chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable methods, or a combination thereof. Furthermore, the common electrode layer 208 may be patterned by one or more photolithography processes and etching processes to form the opening 208 p.

Next, referring to fig. 12E, in some embodiments, after forming the common electrode layer 208 on the dielectric layer 206, a second alignment layer 212 may be further formed on the common electrode layer 208. In some embodiments, the second alignment layer 212 may be conformally formed on the common electrode layer 208 and conformally extend (or is disposed) in the recess 206r and the opening 208 p.

Next, referring to fig. 12F, the first substrate 102 and the second substrate 202 are combined, so that the patches 204 are located on the inner side 202a of the second substrate 202, and the inner side 202a faces the first substrate 102. Furthermore, a liquid crystal layer 300 is formed between the first substrate 102 and the second substrate 202, and the liquid crystal layer 300 is located between the phase-shifting electrode 104 and the common electrode layer 208.

In summary, according to some embodiments of the present invention, the method for manufacturing the electronic device can form the patches and the common electrodes on the same side (single side) of the substrate, so as to reduce the risks of degradation of the modulation material or cracking of the substrate due to the process temperature, or further simplify the process compared to the process of forming metal layers on both sides of the substrate, but not limited thereto. Furthermore, according to some embodiments of the present invention, the electronic device formed by the foregoing manufacturing method can reduce the dielectric loss of electromagnetic waves or improve the reliability of operation.

Although embodiments of the present invention and their advantages have been disclosed, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Features of the embodiments of the invention may be combined and matched as desired without departing from the spirit or conflict of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but it is to be understood that any process, machine, manufacture, composition of matter, means, method and steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present application. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, one claim constitutes a separate embodiment, and the scope of protection of the present invention also includes a combination of each claim and the embodiment. The protection scope of the present invention is subject to the claims. It is not necessary for any embodiment or claim of the invention to achieve all of the objects, advantages, and features disclosed herein.

Claims

1. An electronic device, comprising:

a first substrate;

a plurality of phase shift electrodes disposed on the first substrate;

a second substrate having an inner side facing the first substrate;

a plurality of patches disposed on the inner side of the second substrate;

a common electrode layer;

a dielectric layer disposed between the common electrode layer and the second substrate and disposed on the plurality of patches; and

and the liquid crystal layer is arranged between the phase shift electrodes and the common electrode layer.

2. The electronic device of claim 1, wherein a thickness of the dielectric layer is greater than or equal to 5 microns and less than or equal to a thickness of the second substrate.

3. The electronic device of claim 1, wherein the dielectric layer is a multilayer structure.

4. The electronic device of claim 1, wherein the dielectric layer comprises at least one polyimide film.

5. The electronic device of claim 1, wherein the dielectric layer comprises a recess corresponding to at least one of the plurality of patches.

6. The electronic device of claim 1, wherein the dielectric layer comprises an opening corresponding to at least one of the plurality of patches.

7. The electronic device of claim 6, wherein the opening exposes a portion of the at least one of the plurality of patches.

8. The electronic device of claim 1, wherein the second substrate comprises a recess corresponding to at least one of the plurality of patches.

9. An electronic device, comprising:

a first substrate;

a plurality of phase shift electrodes disposed on the first substrate;

a dielectric layer disposed on the plurality of phase-shifting electrodes;

a plurality of patches disposed on the dielectric layer;

a common electrode layer disposed between the dielectric layer and the first substrate;

a liquid crystal layer disposed between the plurality of phase-shifting electrodes and the dielectric layer;

a first alignment layer disposed between the plurality of phase-shifting electrodes and the liquid crystal layer; and

and the second alignment layer is arranged between the common electrode layer and the liquid crystal layer.

10. The electronic device of claim 9, further comprising: a cover layer disposed on the dielectric layer and in contact with the plurality of patches.

11. A method of manufacturing an electronic device, comprising:

providing a first substrate;

forming a plurality of phase shift electrodes on the first substrate;

providing a second substrate;

forming a plurality of patches on the second substrate;

forming a dielectric layer on the multiple patches;

forming a common electrode layer on the dielectric layer, wherein the dielectric layer is located between the common electrode layer and the second substrate;

the first substrate and the second substrate are paired, and a plurality of patches are positioned on one inner side of the second substrate, wherein the inner side faces the first substrate; and

and forming a liquid crystal layer between the first substrate and the second substrate, wherein the liquid crystal layer is positioned between the phase shift electrodes and the common electrode layer.