CN112492473B

CN112492473B - Signal processing circuit and signal processing method of MEMS microphone

Info

Publication number: CN112492473B
Application number: CN202011217343.5A
Authority: CN
Inventors: 周延青; 潘华兵; 郑泉智; 胡铁刚
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2020-11-04
Filing date: 2020-11-04
Publication date: 2022-09-09
Anticipated expiration: 2040-11-04
Also published as: CN112492473A

Abstract

The application discloses a signal processing circuit and a signal processing method of an MEMS microphone. The signal processing circuit includes: the pre-processing module is used for carrying out pre-quantization and signal shaping on the input signal provided by the MEMS microphone based on a plurality of threshold value ranges so as to obtain high-effective-bit data and a shaped signal; the main analog-digital converter is connected with the preprocessing module to obtain the shaping signal, and the shaping signal is subjected to quantization sampling to obtain low significant bit data; and the digital processor is connected with the preprocessing module to obtain the high-effective bit data, is connected with the main analog-digital converter to obtain the low-effective bit data, and combines and encodes the high-effective bit data and the low-effective bit data so as to obtain the digital signal of the MEMS microphone. The signal processing circuit adopts a signal preprocessing mode to improve the effective digit of the system.

Description

Signal processing circuit and signal processing method of MEMS microphone

Technical Field

The present invention relates to a MEMS microphone, and more particularly, to a signal processing circuit and a signal processing method of a MEMS microphone.

Background

The MEMS microphone is a MEMS (Micro-Electro-Mechanical System) device manufactured by using a Micro-machining process. Due to the advantages of small volume, high sensitivity and good compatibility with the existing semiconductor technology, the MEMS microphone is more and more widely applied to mobile terminals such as mobile phones. The structure of the MEMS microphone includes a diaphragm and a backplate electrode that are opposed to each other, and both are connected to the respective electrodes via leads, respectively. A cavity is formed between the diaphragm and the back electrode plate electrode to provide a vibration space required for the diaphragm.

The MEMS microphone and the signal processing circuit together constitute a digital microphone system. The signal processing circuit performs a series of signal processing on the input signal provided by the MEMS microphone to generate a digital signal, including impedance conversion, single-ended to double-ended signal conversion, signal amplification, analog-to-digital conversion, and digital noise shaping. The digital microphone system has high signal-to-noise ratio and strong anti-interference capability, and can flexibly adjust sensitivity and response frequency band according to application. In digital microphone systems, the number of significant bits (ENOB) of a digital signal is an important performance parameter, related to internal parameters of the signal processing circuitry of the MEMS microphone.

In order to increase the effective number of digital signals, the signal processing circuit of the MEMS microphone needs to increase the dynamic range of the amplifier and increase the resolution of the analog-to-digital converter. However, the signal processing circuit of the existing MEMS microphone not only generates additional quantization noise but also causes circuit design complexity and circuit cost to be excessively high while increasing the effective number of digital signals.

Disclosure of Invention

The invention aims to provide a signal processing circuit and a signal processing method of an MEMS microphone, wherein an analog signal of the MEMS microphone is subjected to signal preprocessing to reduce quantization noise of a digital signal and improve the effective digit of the digital signal.

According to an aspect of the present invention, there is provided a signal processing circuit of a MEMS microphone, including:

the pre-processing module is used for carrying out pre-quantization and signal shaping on the input signal provided by the MEMS microphone based on a plurality of threshold value ranges so as to obtain high-effective-bit data and a shaped signal;

the main analog-digital converter is connected with the preprocessing module to obtain the shaping signal, and the shaping signal is subjected to quantization sampling to obtain low significant bit data; and

the digital processor is connected with the preprocessing module to obtain the high-significance data, is connected with the main analog-digital converter to obtain the low-significance data, and combines and encodes the high-significance data and the low-significance data to obtain the digital signal of the MEMS microphone.

Optionally, the preprocessing module comprises:

a quantizer for performing preliminary quantization scaling on an input signal according to the plurality of threshold value ranges to obtain the high significant bit data; and

and the shaping module is used for respectively superposing corresponding direct current offsets according to the threshold ranges so as to obtain the shaping signal.

Optionally, the threshold range includes a plurality of positive polarity ranges divided by N (Vref _ P-Vref _ N), and a plurality of negative polarity ranges divided by N (Vref _ N-Vref _ P), where Vref _ P and Vref _ N respectively represent an upper offset signal and a lower offset signal, and Vref _ P is greater than Vref _ N, and N represents a natural number.

Optionally, the shaping module superimposes a dc offset on the input signal equal to-N (Vref _ P-Vref _ N) for positive polarity ranges of N (Vref _ P-Vref _ N) and (N +1) (Vref _ P-Vref _ N).

Optionally, for a negative polarity range of N (Vref _ N-Vref _ P) and (N +1) (Vref _ N-Vref _ P), the shaping module superimposes a dc offset on the input signal equal to + N (Vref _ P-Vref _ N).

Optionally, the shaping module is an adder-subtractor.

Optionally, the shaping module comprises an operational amplifier, an inverting input of the operational amplifier receiving the input signal via a first path and the upper and lower offset signals via at least one third path, a non-inverting input of the operational amplifier receiving the upper and lower offset signals via a second path to ground and via at least one fourth path, the shaped signal being provided between a non-inverting output and an inverting output of the operational amplifier,

wherein the first path, the second path, the at least one third path, and the at least one fourth path each comprise a switched capacitor network.

Optionally, the first path includes:

a first capacitor;

a first switch having a first terminal receiving the input signal and a second terminal connected to the first capacitor, and a second switch connected between the first capacitor and an inverting input terminal of the operational amplifier; and

and the third switch and the fourth switch are respectively connected between the first end and the second end of the first capacitor and the ground.

Optionally, the at least one third path respectively includes:

a second end of the third capacitor is connected to a middle node of the first capacitor and the second switch;

a ninth switch and a tenth switch, a first terminal of the ninth switch receiving the up-shift signal, a first terminal of the tenth switch receiving the down-shift signal, second terminals of the ninth switch and the tenth switch being commonly connected to a first terminal of the third capacitor; and

and the eleventh switch and the twelfth switch are respectively connected between the first end and the second end of the third capacitor and the ground.

Optionally, the second path comprises:

a second capacitor;

a fifth switch having a first terminal connected to ground and a second terminal connected to the second capacitor, and a sixth switch connected between the second capacitor and a non-inverting input terminal of the operational amplifier; and

and the seventh switch and the eighth switch are respectively connected between the first end and the second end of the second capacitor and the ground.

Optionally, the at least one fourth path respectively comprises:

a second end of the fourth capacitor is connected to a middle node of the second capacitor and the sixth switch;

a thirteenth switch and a fourteenth switch, a first terminal of the thirteenth switch receiving the upper offset signal, a first terminal of the fourteenth switch receiving the lower offset signal, and second terminals of the thirteenth switch and the fourteenth switch being commonly connected to a first terminal of the fourth capacitor; and

and the fifteenth switch and the sixteenth switch are respectively connected between the first end and the second end of the fourth capacitor and the ground.

Optionally, the shaping module further comprises:

a fifth capacitor and a seventeenth switch connected in parallel between the inverting input terminal and the non-inverting output terminal of the operational amplifier; and

and the sixth capacitor and the eighteenth switch are connected in parallel between the non-inverting input end and the inverting output end of the operational amplifier.

Optionally, the input signal is a single-ended signal, and the shaped signal is a double-ended signal.

Optionally, the digital processor performs a logic operation on the high significant bit data and two non-overlapping clock signals to generate a plurality of switch control signals of the shaping module.

Optionally, the quantizer is an analog-to-digital converter adopting any one of the following structures: a single bit successive approximation structure, a fully parallel structure, a pipelined structure, or a Sigma-Delta structure.

According to another aspect of the present invention, there is provided a signal processing method of a MEMS microphone, including:

pre-quantizing and signal shaping an input signal provided by the MEMS microphone based on a plurality of threshold value ranges to obtain high significance data and a shaped signal;

performing quantization sampling on the shaped signal to obtain low significant bit data; and

combining and encoding the more significant bit data and the less significant bit data to obtain a digital signal of the MEMS microphone.

Optionally, the pre-quantizing comprises preliminary quantizing scaling of the input signal according to the plurality of threshold ranges to obtain the high significant bit data.

Optionally, the signal shaping includes superimposing corresponding dc offsets according to the plurality of threshold ranges, respectively, to obtain the shaped signal.

Optionally, the threshold range includes a plurality of positive polarity ranges divided by N (Vref _ P-Vref _ N), and a plurality of negative polarity ranges divided by N (Vref _ N-Vref _ P), where Vref _ P and Vref _ N represent an upper offset signal and a lower offset signal, respectively, and Vref _ P is greater than Vref _ N, and N represents a natural number.

Optionally, the method further comprises: and performing logic operation on the high effective bit data and two phases of non-overlapped clock signals to generate a plurality of switch control signals for shaping the signals.

According to the signal processing circuit and the signal processing method of the MEMS microphone, the design difficulty of the main analog-digital converter can be reduced by adopting a signal preprocessing mode, the swing amplitude of an operational amplifier in the module is reduced, and meanwhile through the integration of a subsequent digital signal processing module, the effective digit of a digital signal output by the signal processing circuit can be 1-2Bits higher than that of the main analog-digital converter, so that the effective digit of the whole signal processing circuit can be improved, or the design index of the main analog-digital converter can be effectively reduced under the condition that the effective digit of a system is unchanged.

Furthermore, the signal processing circuit adds corresponding direct current offsets to analog signals in a plurality of threshold ranges respectively to compress a dynamic range, and limits the analog signals in the plurality of threshold ranges within a set interval. The digital microphone system reduces the quantization noise of the system by compressing the amplitude of the analog signal in a signal path, thereby reducing the Total Harmonic Distortion (THD), improving the Acoustic Overload Point (AOP) and increasing application scenes.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a digital microphone system according to a first embodiment of the present invention.

Fig. 2a and 2b show different schematic circuit diagrams of buffers in the digital microphone system shown in fig. 1, respectively.

Fig. 3 shows a schematic circuit diagram of a quantizer of the pre-processing module in the digital microphone system shown in fig. 1.

Fig. 4 shows the relationship between the high significant bit data generated by the quantizer shown in fig. 3 and the voltage interval of the input signal.

Fig. 5 shows a schematic circuit diagram of a shaping module of the pre-processing module in the digital microphone system shown in fig. 1.

Fig. 6 shows waveforms of two phase non-overlapping clock signals in the shaping module shown in fig. 5.

Fig. 7 and 8 are waveform diagrams illustrating dc offsets of the ramp signal and the sine wave signal, respectively, by the shaping module shown in fig. 5.

Fig. 9 shows a schematic circuit diagram of a quantizer of a pre-processing module in a digital microphone system according to a second embodiment of the present invention.

Fig. 10 shows a schematic circuit diagram of a shaping module of a pre-processing module in a digital microphone system according to a second embodiment of the present invention.

Fig. 11 and 12 are waveform diagrams illustrating dc offsets of the ramp signal and the sine wave signal, respectively, by the shaping module shown in fig. 10.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

In this application, the term "total harmonic distortion" (i.e., THD) refers to the additional harmonic component of the output signal that is more than the input signal when the signal source is input, resulting from the system's incomplete linearity, and the total harmonic distortion at a particular frequency is used as the indicator. The term "acoustic overload point" (i.e., AOP) is an important quality indicator for MEMS microphones, and represents the magnitude of sound pressure when the total harmonic distortion is equal to 10%. An input signal at a sound pressure higher than the AOP will cause a severe distortion of the output signal.

Unless defined otherwise, all techniques and terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

It should be understood that the steps in the flowcharts of the present application are shown in sequence as indicated by the arrows, but the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

The present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic block diagram of a digital microphone system according to a first embodiment of the present invention. The digital microphone system 100 includes a MEMS microphone 101 and a signal processing circuit 102. The MEMS microphone 101 supplies an input signal as an input signal Vin to the signal processing circuit 102, and the signal processing circuit 102 performs impedance conversion, shaping processing, and analog-to-digital conversion on the input signal Vin to obtain digital signals Sa and Sb.

Signal processing circuit 102 includes buffer 110, pre-processing module 120, master analog-to-digital converter (ADC)130, charge pump 150, bias supply module 160, and oscillator 170.

The buffer 110 converts the high impedance input signal Vin provided by the MEMS microphone 101 into a low impedance input signal V0. In this application, the high impedance input signal Vin and the low impedance input signal V0 of the MEMS microphone 101 are collectively referred to as the input signals provided by the MEMS microphone 101. The pre-processing module 120 performs pre-quantization and signal shaping on the input signal provided by the MEMS microphone 101 to obtain the high significant bit data Sa and the shaped signal V1. The main analog-to-digital converter 130 performs quantization sampling on the reshaped signal V1 to obtain the low significant bit data Sb. The digital processor 140 combines and encodes the high significant bit data Sa and the low significant bit data Sb, thereby obtaining a digital signal of the MEMS microphone 101. Further, the charge pump 150 is used to provide a bias voltage required for the operation of the MEMS microphone 101, the bias supply module 160 is used to provide a current reference and a voltage bias, and the oscillator 170 is used to provide a clock reference.

The digital processor 140 also performs control functions of the internal blocks of the signal processing circuit 102. After receiving the high significant bit data Sa, the digital processor 140 generates the switching signal SW of the shaping module 122 and the clock signal CLK of the main adc 130 according to the result of the high significant bit data Sa. Preferably, the digital processor 140 further integrates electronic fuses (efuses) and the like to trim the output signal amplitude of the buffer 110 or trim the output voltage of the charge pump 150.

In the signal processing circuit 102, the pre-processing module 120 includes a quantizer 121 and a shaping module 122. The quantizer 121 is, for example, a low resolution analog-to-digital converter, and is configured to obtain the high effective bit data Sa of the digital signal of the MEMS microphone. The quantizer 121 may adopt any one of the following structures: a single bit SAR (successive approximation) structure, a FLASH (full parallel) structure, a Pipeline structure, or a Sigma-Delta structure. Preferably, the quantizer 121 employs a FLASH (full parallel) architecture. The shaping module 122 is used for adding corresponding dc offsets (i.e., partition offsets) to the analog signals of the threshold ranges, respectively, and converting the single-ended analog signals generated by the MEMS microphone into double-ended analog signals. The shaping module 12 performs addition and subtraction arithmetic operation on the input signal by using an amplifier, for example, and may use any one of the following amplifiers: the gain of the operational amplifier and the charge amplifier with the switched capacitor structure is usually configured to be 0-12dB according to requirements. Preferably, the amplifier is a charge amplifier.

The main analog-to-digital converter 130 is, for example, a high resolution analog-to-digital converter, and may adopt any one of the following structures: a single bit SAR (successive approximation) structure, a FLASH (full parallel) structure, a Pipeline structure, or a Sigma-Delta structure. Preferably, master adc 130 employs a Sigma-Delta architecture. Compared with an analog-to-digital converter with a FLASH structure, the analog-to-digital converter with the Sigma-Delta structure has higher requirement on the system clock rate in order to meet a certain oversampling rate.

According to the digital microphone system of the above embodiment, the pre-processing module 120 in the signal processing circuit 102 pre-quantizes and shapes the input signal provided by the MEMS microphone based on a plurality of threshold ranges. For example, the quantizer 121 performs preliminary quantization classification on the input signal according to a plurality of threshold ranges to obtain the high significant bit data Sa, and the shaping module 122 superimposes corresponding dc offsets V1 (i.e., partition offsets) according to the plurality of threshold ranges, respectively, to obtain the shaped signal V1.

For example, the threshold range includes a plurality of positive polarity ranges divided by N × (Vref _ P-Vref _ N), and a plurality of negative polarity ranges divided by N × (Vref _ N-Vref _ P), where Vref _ P and Vref _ N represent an upper offset signal and a lower offset signal, respectively, and N represents a natural number. For positive polarity ranges of N (Vref _ P-Vref _ N) and (N +1) (Vref _ P-Vref _ N), the shaping module superimposes a dc offset on the input signal equal to-N (Vref _ P-Vref _ N). For negative polarity ranges of N (Vref _ N-Vref _ P) and (N +1) (Vref _ N-Vref _ P), the shaping module superimposes a dc offset on the input signal equal to + N (Vref _ P-Vref _ N).

Thus, the pre-processing module 120 of the signal processing circuit 102 may compress the dynamic range of the amplifier, thereby reducing quantization noise of the digital microphone system. Further, the main adc 130 of the signal processing circuit 102 converts the shaped signal V1 of the preprocessing module 120 to obtain the low significant bit data Sb, and the digital processor 140 combines and encodes the high significant bit data Sa and the low significant bit data Sb to obtain the digital signal of the MEMS microphone 101. The signal processing circuit 102 may increase the effective number of Bits, e.g., 1-2Bits, of the digital signal of the MEMS microphone 101. The pre-processing module 120 of the signal processing circuit 102 and the main adc 130 generate the digital signal of the MEMS microphone, so that the accuracy and resolution of the digital signal can be improved. The digital microphone system reduces the quantization noise of the system by compressing the amplitude of the analog signal in a signal path, thereby reducing the Total Harmonic Distortion (THD), improving the Acoustic Overload Point (AOP) and increasing application scenes.

As shown in fig. 2a, the buffer 110 includes a current source IS0 and a transistor Q0 connected in series between a power supply terminal VDD and a ground terminal.

The transistor Q0 is, for example, a P-type MOSFET (metal oxide semiconductor field effect transistor). The gate of transistor Q0 receives the input signal provided by MEMS microphone 101 as a high impedance input signal Vin, and the intermediate node of transistor Q0 and current source IS0 provides a low impedance input signal V0. The transistor Q0 operates in saturation with a gain of, for example, 0dB, to realize the conversion from the high impedance input signal Vin to the low impedance input signal V0. The low impedance input signal V0 is the gate-source voltage Vgs of transistor Q0, which is a value related to tape-out processes, typically between 0.6V-1.2V.

As shown in fig. 2b, the buffer 210 includes a current source IS1 and a transistor Q1 connected in series between the power supply terminal VDD and the ground terminal, a current source IS2 and a transistor Q2 connected in series between the power supply terminal VDD and the ground terminal, and an operational amplifier U1.

The current sources IS1 and IS2 are current sources arranged in mirror image with each other, and supply a first current and a second current equal to each other. The transistors Q1 and Q2 are transistors arranged in mirror image of each other, such as P-type MOSFETs (metal oxide semiconductor field effect transistors) that are equal in size to each other. The non-inverting input of the operational amplifier U1 IS connected to the intermediate node of the current source IS1 and the transistor Q1, the inverting input IS connected to the intermediate node of the current source IS2 and the transistor Q2, and the output IS connected to the gate of the transistor Q2. The operational amplifier U1 provides a negative feedback signal such that the dc levels of the gates of transistors Q1 and Q2 are equal. Thus, the gate of transistor Q1 receives the input signal provided by MEMS microphone 101 as a high impedance input signal Vin, and the gate of transistor Q2 provides a low impedance input signal V0 as an output.

The electrical parameters and the structural layout of the current sources IS1 and IS2 and the transistors Q1 and Q2 of the buffer 210 are all designed symmetrically to reduce signal mismatch and signal offset (offset).

Fig. 3 shows a schematic circuit diagram of a quantizer of the pre-processing module in the digital microphone system shown in fig. 1. In this embodiment, the quantizer 121 is an analog-to-digital converter of FLASH (full parallel) architecture, comprising comparators U11 and U12.

The comparator U11 has a non-inverting input receiving the input signal V0, an inverting input receiving the threshold voltage (Vref _ P-Vref _ N), and an output providing the logic signal D11. The comparator U12 has an inverting input receiving the input signal V0, a non-inverting input receiving the threshold voltage (Vref _ N-Vref _ P), and an output providing the logic signal D12. In this embodiment, Vref _ P represents an up-shift signal, Vref _ N represents a down-shift signal, and Vref _ P > Vref _ N. For example, (Vref _ P-Vref _ N) ═ V0_ full × 1/6, where V0_ full represents the full amplitude of the input signal V0. The full amplitude of the input signal V0 corresponds to the voltage value of the input signal V0 at the sound pressure overload point AOP of the microphone.

The comparators U11 and U12 perform a high significant bit quantization of the input signal V0. In the range of 2(Vref _ N-Vref _ P) < V0<2(Vref _ P-Vref _ N), 3 voltage intervals a to C are divided in total, as shown in fig. 4.

Referring to table 1, the logic signals D11 and D12 of the comparators U11 and U12 correspond to the voltage intervals a to C of the input signal V0. The logic signals D11 and D12 of the comparators U11 and U12 are combined into the upper significant bit data Sa of the input signal V0. For example, the digital value 00 indicates that the input signal Vo is located in the voltage interval B.

TABLE 1 relationship between logic signal and voltage interval of quantizer

Voltage interval	V0	D11	D12
				A	Vref_P-Vref_N<V0<2(Vref_P-Vref_N)	1	0
B	Vref_N-Vref_P<V0<Vref_P-Vref_N	0	0
				C	2(Vref_N-Vref_P)<V0<Vref_N-Vref_P	0	1

Fig. 5 shows a schematic circuit diagram of a shaping module of the pre-processing module in the digital microphone system shown in fig. 1. In this embodiment, shaping module 122 is a charge amplifier of switched capacitor construction, e.g., shaping module 122 includes an operational amplifier U2.

The inverting input of the operational amplifier U2 receives the input signal V0 via a first path and the offset signals Vref _ P and Vref _ N via a third path. The first path and the third path each include a switched capacitor network.

The first path includes a capacitor C11, a switch S11 connected to a first terminal of the capacitor C11, a switch S12 connected between a second terminal of the capacitor C11 and an inverting input terminal of the operational amplifier U2, a switch S13 connected between a first terminal of the capacitor C11 and ground, and a switch S14 connected between a second terminal of the capacitor C11 and ground. The switch S11 has a first terminal receiving the input signal V0 and a second terminal connected to the capacitor C11.

The third path includes a capacitor C12, switches S15 and S16 connected to a first terminal of the capacitor C12, a switch S17 connected between a first terminal of the capacitor C12 and ground, and a switch S18 connected between a second terminal of the capacitor C12 and ground. A first terminal of the switch S15 receives the bias signal Vref _ P, a first terminal of the switch S16 receives the bias signal Vref _ N, and second terminals of the switches S15 and S16 are commonly connected to the capacitor C12.

The non-inverting input terminal of the operational amplifier U2 is grounded via a second path and receives the offset signals Vref _ P and Vref _ N via a fourth path. The second path and the fourth path each include a switched capacitor network.

The second path includes a capacitor C21, a switch S21 connected to the first terminal of the capacitor C21, a switch S22 connected between the second terminal of the capacitor C21 and the non-inverting input terminal of the operational amplifier U2, a switch S23 connected between the first terminal of the capacitor C21 and ground, and a switch S24 connected between the second terminal of the capacitor C21 and ground. The switch S21 has a first terminal connected to ground and a second terminal connected to the capacitor C21.

The fourth path includes a capacitor C22, switches S25 and S26 connected to a first terminal of the capacitor C22, a switch S27 connected between the first terminal of the capacitor C22 and ground, and a switch S28 connected between a second terminal of the capacitor C22 and ground. A first terminal of the switch S25 receives the bias signal Vref _ N, a first terminal of the switch S26 receives the bias signal Vref _ P, and second terminals of the switches S25 and S26 are commonly connected to the capacitor C22.

The shaping module 122 also includes a capacitor C13 and a switch S19 connected in parallel between the inverting input and the non-inverting output of the operational amplifier U2, and a capacitor C23 and a switch S29 connected in parallel between the non-inverting input and the inverting output of the operational amplifier U2. A shaped signal V1 is provided between the non-inverting and inverting outputs of the operational amplifier U2.

In the shaping module 122, the capacitances of the capacitors C11, C13, C21, and C23 are equal to C, and the capacitances of the capacitors C12 and C22 are equal to 2 × C, respectively. The magnitude of the capacitance C needs to be quantified in terms of circuit noise figure, typically of the order of pF. The ground terminals of the individual elements are ac grounds and may be connected, for example, to a suitable common mode voltage bias.

The digital processor 140 provides two phase non-overlapping clock signals CLK1 and CLK2 as shown in fig. 6. The clock signals CLK1 and CLK2 are logically operated with the high significant bit data Sa, and the switching control signals of the switches S11 to S19 and the switches S21 to S29 are obtained. Thus, the switch control signals of the switches S11 to S19 and the switches S21 to S29 are selected to be one of the clock signals CLK1, CLK2 or turned off according to the voltage intervals a to C of the input signal V0, see table 2. The clock signals CLK1 and CLK2 are clock signals that do not overlap with each other. Two-phase non-overlapping clock signals are often used in the switched capacitor circuit, and because a phase difference exists between rising edges of the two clock signals and a phase difference exists between falling edges of the two clock signals, the two groups of switches work according to different phases under the control of the two-phase non-overlapping clock signals, so that the two groups of switches can be prevented from being turned on or turned off at the same moment.

TABLE 2 relationship between switch control signal and voltage interval

In different voltage intervals, the clock signals of the switches S11 to S14 on the first path and the switches S17 and 18 on the third path, the switches S21 to S24 on the second path and the switches S27 and 28 on the fourth path of the shaping module 122 remain unchanged. That is, the switches S11, S14 on the first path, the switches S17, S18 on the third path, the switches S21, S24 on the second path, and the switches S27, S28 on the fourth path always receive the clock signal CLK1 as the switch control signals, and the switches S12, S13 on the first path and the switches S22, S23 on the second path always receive the clock signal CLK2 as the switch control signals.

In different voltage intervals, the switches S15 and S16 on the third path and the switches S25 and S26 on the fifth path are in different states according to the voltage intervals.

In the voltage interval a, the switch control signals of the switch S15 on the third path and the switch S25 on the fifth path are the clock signal CLK2, the switch S16 on the third path and the switch S26 on the fifth path are turned off, and the operational amplifier U2 superimposes the dc offset of-1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1.

In the voltage interval B, the switches S15 and S16 in the third path and the switches S25 and S26 in the fifth path are all turned off, the shaping signal V1 of the operational amplifier U2 is the same as the input signal V0, and the amplifier U2 does not superimpose any dc offset on the input signal V0.

In the voltage interval C, the switch S15 on the third path and the switch S25 on the fifth path are turned off, the switch control signals of the switch S16 on the third path and the switch S26 on the fifth path are the clock signal CLK2, and the operational amplifier U2 superimposes the dc offset +1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaping model V1.

Thus, the operational amplifier U2 performs different operational functions at different voltage intervals, adding corresponding dc offsets (i.e., partition offsets) for the analog signals for multiple threshold ranges, respectively, see table 3.

TABLE 3 relationship between amplifier operational function and voltage interval

Voltage interval	D11	D12	Operational function of amplifier
				A	1	0	V0-1*(Vref_P-Vref_N)
B	0	0	V0
				C
	0	1	V0+1*(Vref_P-Vref_N)

Referring to fig. 1, the main adc 130 performs quantization sampling on the reshaped signal V1 to obtain lower significant bit data Sb, and the digital processor 140 combines and encodes the higher significant bit data Sa and the lower significant bit data Sb to obtain a digital signal of the MEMS microphone 101.

In this embodiment, the digital signal DIG _ MIC of the MEMS microphone 101 is represented as:

DIG_MIC＝ADC_dig+(D11-D12)*K， (3)

wherein, ADC _ dig represents the binary digital value of the quantized integer signal by the main ADC 130, D11 and D12 represent the binary digital value of the input signal quantized by the quantizer 121 of the pre-processing module 120 with high order, and K is a constant.

K in the above formula is represented by the following formula:

K＝(Vref_P-Vref_N)/LSB， (4)

where LSB represents the minimum quantization step size of the main analog-to-digital converter 130.

In the voltage interval a, the amplifier U1 of the shaping module 122 superimposes a dc offset of-1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1. In the voltage interval C, the amplifier U1 of the shaping module 122 superimposes a dc offset +1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1. In voltage interval B, the amplifier U1 of the shaping module 122 does not superimpose any dc offset on the input signal V0.

As shown in fig. 7, in the case that the input signal V0 is a ramp signal, the quantizer 121 quantizes the input signal V0 to obtain the high significant bit data Sa, and the shaping module 122 adds a corresponding dc offset to the input signal V0 to obtain a segmented ramp signal in the range of (Vref _ N-Vref _ P) to (Vref _ P-Vref _ N).

As shown in fig. 8, in the case that the input signal V0 is a sine wave signal, the quantizer 121 quantizes the input signal V0 to obtain the high significant bit data Sa, and the shaping module 122 adds a corresponding dc offset to the input signal V0 to obtain a segmented sine wave signal in the range from Vref _ N-Vref _ P to Vref _ P-Vref _ N.

Fig. 9 shows a schematic circuit diagram of a quantizer of a pre-processing module in a digital microphone system according to a second embodiment of the present invention. In this embodiment, the quantizer 221 is a FLASH (full parallel) architecture analog-to-digital converter including comparators U11, U12, U21, and U22.

The comparator U11 has a non-inverting input receiving the input signal V0, an inverting input receiving the threshold voltage Vref _ P-Vref _ N, and an output providing the logic signal D11. The comparator U21 has a non-inverting input receiving the input signal V0, an inverting input receiving the threshold voltage 2 x (Vref _ P-Vref _ N), and an output providing the logic signal D21. The comparator U12 has an inverting input receiving the input signal V0, a non-inverting input receiving the threshold voltage Vref _ N-Vref _ P, and an output providing the logic signal D12. The comparator U22 has an inverting input receiving the input signal V0, a non-inverting input receiving the threshold voltage 2 x (Vref _ N-Vref _ P), and an output providing the logic signal D22. In this embodiment, Vref _ P represents an up-shift signal, Vref _ N represents a down-shift signal, and Vref _ P > Vref _ N. For example, Vref _ P-Vref _ N is V0_ full 1/6, where V0_ full represents the full amplitude of the input signal V0. The full amplitude signal of the input signal V0 corresponds to the voltage value of the input signal V0 of the microphone at the sound pressure overload point AOP.

The comparators U11, U12, U21, and U22 perform a high significant bit quantization on the input signal V0. In the range of 3(Vref _ N-Vref _ P) < V0<3(Vref _ P-Vref _ N), 5 voltage intervals a to E are divided in total.

Referring to table 3, the logic signals D11, D12, D21, and D22 of the comparators U11, U12, U21, and U22 correspond to the voltage intervals a to E of the input signal V0. Logic signals D11, D12, D21 and D22 of the comparators U11, U12, U21 and U22 are combined into the high significant bit data Sa of the input signal V0. For example, the digital value 0100 indicates that the input signal Vo is in the voltage interval B.

TABLE 3 relationship between logic signal and voltage interval of quantizer

Fig. 10 shows a schematic circuit diagram of a shaping module of a pre-processing module in a digital microphone system according to a second embodiment of the present invention. In this embodiment, shaping module 222 is a charge amplifier of switched capacitor construction, e.g., shaping module 222 includes an operational amplifier U3.

The inverting input of the operational amplifier U3 receives the input signal V0 via a first path, the offset signals Vref _ P and Vref _ N via a third path, and the offset signals Vref _ P and Vref _ N via a fourth path. The first path, the third path, and the fourth path each include a switched capacitor network.

The first path includes a capacitor C11, a switch S11 connected to a first terminal of the capacitor C11, a switch S12 connected between a second terminal of the capacitor C11 and an inverting input terminal of the operational amplifier U3, a switch S13 connected between a first terminal of the capacitor C11 and ground, and a switch S14 connected between a second terminal of the capacitor C11 and ground. The switch S11 has a first terminal receiving the input signal V0 and a second terminal connected to the capacitor C11.

The fourth path includes a capacitor C32, switches S35 and S36 connected to a first terminal of the capacitor C32, a switch S37 connected between a first terminal of the capacitor C32 and ground, and a switch S38 connected between a second terminal of the capacitor C32 and ground. A first terminal of the switch S35 receives the bias signal Vref _ P, a first terminal of the switch S36 receives the bias signal Vref _ N, and second terminals of the switches S35 and S36 are commonly connected to the capacitor C32.

The non-inverting input of the operational amplifier U3 is grounded via a second path, receives the offset signals Vref _ P and Vref _ N via a fifth path, and receives the offset signals Vref _ P and Vref _ N via a sixth path. The second, fifth and sixth paths each include a switched capacitor network.

The second path includes a capacitor C21, a switch S21 connected at a first end of the capacitor C21, a switch S22 connected between a second end of the capacitor C21 and a non-inverting input of the operational amplifier U3, a switch S23 connected between a first end of the capacitor C21 and ground, and a switch S24 connected between a second end of the capacitor C21 and ground. The switch S21 has a first terminal connected to ground and a second terminal connected to the capacitor C21.

The fifth path includes a capacitor C22, switches S25 and S26 connected to a first terminal of the capacitor C22, a switch S27 connected between a first terminal of the capacitor C22 and ground, and a switch S28 connected between a second terminal of the capacitor C22 and ground. A first terminal of the switch S25 receives the bias signal Vref _ N, a first terminal of the switch S26 receives the bias signal Vref _ P, and second terminals of the switches S25 and S26 are commonly connected to the capacitor C22.

The sixth path includes a capacitor C42, switches S45 and S46 connected to a first terminal of the capacitor C42, a switch S47 connected between a first terminal of the capacitor C42 and ground, and a switch S48 connected between a second terminal of the capacitor C42 and ground. A first terminal of the switch S45 receives the bias signal Vref _ N, a first terminal of the switch S46 receives the bias signal Vref _ P, and second terminals of the switches S45 and S46 are commonly connected to the capacitor C42.

The shaping module 222 also includes a capacitor C13 and a switch S19 connected in parallel between the inverting input and the non-inverting output of the operational amplifier U3, and a capacitor C23 and a switch S29 connected in parallel between the non-inverting input and the inverting output of the operational amplifier U3. A shaped signal V1 is provided between the non-inverting and inverting outputs of the operational amplifier U3.

In the shaping module 222, the capacitance values of the capacitors C11, C13, C21 and C23 are respectively equal to C, and the capacitance values of the capacitors C12, C22, C32 and C42 are respectively equal to 2 × C. The magnitude of the capacitance C needs to be quantified in terms of the circuit noise figure, typically in the order of pF. The ground terminals of the individual elements are ac grounds and may be connected, for example, to a suitable common mode voltage bias.

The digital processor 140 provides two phase non-overlapping clock signals CLK1 and CLK2 as shown in fig. 6. The clock signals CLK1 and CLK2 are logically operated with the high significant bit data Sa to obtain switching control signals for the switches S11 to S19, the switches S21 to S29, the switches S45 to S48, and the switches S35 to S38. Thus, the switching control signals of the switches S11 to S19, the switches S21 to S29, the switches S37 and S38, and the switches S47 and S48 are selected to be one of the clock signals CLK1, CLK2, or turned off, according to the voltage sections a to E of the input signal V0, see tables 4-1 and 4-2. As described above, the clock signals CLK1 and CLK2 are clock signals that do not overlap with each other.

TABLE 4-1 relationship between switch control signal and voltage interval

Voltage interval	S15,S25	S35,S45	S36,S46	S16,S26	S38,S48
						A	CLK2	CLK2		0	0	CLK2
B
		0	CLK2	0	0	0
C							0	0	0	0	0
	D	0	0	CLK2	0	0
E							0	0	CLK2	CLK2	CLK2

TABLE 4-2 relationship of switch control signals to Voltage intervals

In different voltage intervals, the clock signals of the switches S11 to S14 on the first path and the switches S21 to S24 on the second path of the shaping module 222 are maintained unchanged. That is, the switches S11, S12 on the first path, the switches S21, S22 on the second path always receive the clock signal CLK1 as the switch control signals, and the switches S13, S14 on the first path, the switches S23, S24 on the second path, and the switches S19 and S29 always receive the clock signal CLK2 as the switch control signals.

In different voltage intervals, the switches S15 to S18 on the third path, the switches S25 to S28 on the fifth path, the switches S35 to S38 on the fourth path, and the switches S45 to S48 on the sixth path are in different states according to the voltage intervals.

In the voltage interval a, the switch control signals of the switch S15 on the third path, the switch S25 on the fifth path, the switch S35 on the fourth path, and the switch S45 on the sixth path are the clock signal CLK2, the switch S16 on the third path, the switch S26 on the fifth path, the switch S36 on the fourth path, and the switch S46 on the sixth path are turned off, and the operational amplifier U3 superimposes the dc offset-2 (Vref _ P-Vref _ N) on the input signal V0 to obtain the model shaping V1.

In the voltage interval B, the switch control signals of the switch S35 on the fourth path and the switch S45 on the sixth path are the clock signal CLK2, the switches S15 and S16 on the third path, the switches S25 and S26 on the fifth path, the switch S36 on the fourth path, and the switch S46 on the sixth path are turned off, and the operational amplifier U3 superimposes the dc offset-1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaping model V1.

In the voltage interval C, the switches S15 and S16 in the third path, the switches S25 and S26 in the fifth path, the switches S35 and S36 in the fourth path, and the switches S45 and S46 in the sixth path are all turned off, the shaping signal V1 of the operational amplifier U3 is the same as the input signal V0, and no dc offset is superimposed on the input signal V0 by the operational amplifier U3.

In the voltage interval D, the switch control signals of the switch S36 on the fourth path and the switch S46 on the sixth path are the clock signal CLK2, the switches S15 and S16 on the third path, the switches S25 and S26 on the fifth path, the switch S35 on the fourth path, and the switch S45 on the sixth path are turned off, and the operational amplifier U3 superimposes the dc offset 1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaping model V1.

In the voltage interval E, the switch control signals of the switch S16 on the third path, the switch S26 on the fifth path, the switch S36 on the fourth path, and the switch S46 on the sixth path are the clock signal CLK2, the switch S15 on the third path, the switch S25 on the fifth path, the switch S35 on the fourth path, and the switch S45 on the sixth path are turned off, and the operational amplifier U3 superimposes the dc offset 2(Vref _ P-Vref _ N) on the input signal V0 to obtain the shaping model V1.

Thus, the operational amplifier U3 performs different operational functions at different voltage intervals, adding corresponding dc offsets (i.e., partition offsets) for the analog signals for multiple threshold ranges, respectively, see table 5.

TABLE 5 relationship between amplifier operational function and voltage range

Voltage interval	D21	D11	D12	D22	Operational function of amplifier
						A	1	1	1	1	V0-2*(Vref_P-Vref_N)
B	0	1	1	1	V0-1*(Vref_P-Vref_N)
						C	0	0	1	1	V0
D
		0	0	0	1	V0+1*(Vref_P-Vref_N)
E							0	0	0	0	V0+2*(Vref_P-Vref_N)

DIG_MIC＝ADC_dig+(D21-D22+D11-D12)*K， (5)

wherein, ADC _ dig represents a binary digital value of the quantized integer signal by the main ADC 130, D11, D12, D21 and D22 represent a binary digital value of the input signal quantized by the quantizer 221 of the preprocessing module at a high order, and K is a constant.

K in the above formula is represented by the following formula:

K＝(Vref_P-Vref_N)/LSB， (6)

Fig. 11 and 12 are waveform diagrams illustrating dc offsets of the ramp signal and the sine wave signal by the shaping module shown in fig. 10, respectively.

As shown in fig. 11, in the case that the input signal V0 is a ramp signal, the quantizer 121 quantizes the input signal V0 to obtain the high significant bit data Sa, and the shaping module 122 adds a corresponding dc offset to the input signal V0 to obtain a segmented ramp signal in the range of (Vref _ N-Vref _ P) to (Vref _ P-Vref _ N).

As shown in fig. 12, in the case that the input signal V0 is a sine wave signal, the quantizer 121 quantizes the input signal V0 to obtain the high effective bit data Sa, and the shaping module 122 adds a corresponding dc offset to the input signal V0 to obtain a segmented sine wave signal in the range from Vref _ N-Vref _ P to Vref _ P-Vref _ N.

The number of segments of the segmented ramp signal for shaping the ramp signal in the range of 3 × Vref _ N-Vref _ P to 3 × Vref _ P-Vref _ N into the segmented ramp signal in the range of (Vref _ N-Vref _ P) to (Vref _ P-Vref _ N) is 5, and the number of segments of the sine wave signal in the range of 3 × Vref _ N-Vref _ P to 3 × Vref _ P-Vref _ N into the segmented sine wave signal in the range of (Vref _ N-Vref _ P) to (Vref _ P-Vref _ N) is 9, and is 5 in two

half cycles

501 and 502, respectively. Specifically, in the voltage interval a, the amplifier U3 of the shaping module 222 superimposes a dc offset of-2 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1. In the voltage interval B, the amplifier U3 of the shaping module 222 superimposes a dc offset of-1 (Vref _ P-Vref _ N) on the input signal V0. In the voltage interval D, the amplifier U3 of the shaping module 222 superimposes a dc offset +1 (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1. In the voltage interval E, the amplifier U3 of the shaping module 222 superimposes a dc offset +2 x (Vref _ P-Vref _ N) on the input signal V0 to obtain the shaped model V1. In voltage interval C, amplifier U3 of shaping module 222 does not superimpose any dc offset on input signal V0.

The present application describes a specific embodiment of dividing the input signal V0 into 3 voltage intervals and 5 voltage intervals, but the present invention is not limited to this, and the present invention can be specifically configured according to actual requirements, for example, the input signal generated by the MEMS microphone can be divided into 7 voltage intervals, 9 voltage intervals, and the like.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.

Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A signal processing circuit of a MEMS microphone, comprising:

a digital processor connected to the pre-processing module to obtain the more significant data, connected to the main ADC to obtain the less significant data, and combining and encoding the more significant data and the less significant data to obtain a digital signal of the MEMS microphone, wherein,

the shaped signal is obtained from a superposition of the input signal and a dc offset,

the superposition of the input signal and the dc offset is performed by an operational amplifier, and the input signal and the dc offset are provided to the operational amplifier by a switched capacitor network.

2. The signal processing circuit of claim 1, wherein the pre-processing module comprises:

3. The signal processing circuit of claim 2, wherein the threshold ranges comprise a plurality of positive polarity ranges divided by N x (Vref _ P-Vref _ N), and a plurality of negative polarity ranges divided by N x (Vref _ N-Vref _ P), wherein Vref _ P and Vref _ N represent an up-offset signal and a down-offset signal, respectively, and Vref _ P is greater than Vref _ N, N representing a natural number.

4. The signal processing circuit of claim 3, wherein the shaping module superimposes a DC offset on the input signal equal to-N (Vref _ P-Vref _ N) for positive polarity ranges of N (Vref _ P-Vref _ N) and (N +1) (Vref _ P-Vref _ N).

5. The signal processing circuit of claim 4, wherein the shaping module superimposes a DC offset on the input signal equal to + N (Vref _ P-Vref _ N) for negative polarity ranges of N (Vref _ N-Vref _ P) and (N +1) (Vref _ N-Vref _ P).

6. The signal processing circuit of claim 5, wherein the shaping module is an adder-subtractor.

7. The signal processing circuit of claim 5, wherein the shaping module comprises an operational amplifier having an inverting input to receive the input signal via a first path and to receive the up-offset signal and the down-offset signal via at least one third path, a non-inverting input to the operational amplifier being grounded via a second path and to receive the up-offset signal and the down-offset signal via at least one fourth path, the shaped signal being provided between a non-inverting output and an inverting output of the operational amplifier,

8. The signal processing circuit of claim 7, wherein the first path comprises:

a first capacitor;

9. The signal processing circuit of claim 8, wherein the at least one third path respectively comprises:

a ninth switch and a tenth switch, a first terminal of the ninth switch receiving the up-shift signal, a first terminal of the tenth switch receiving the down-shift signal, and second terminals of the ninth switch and the tenth switch being commonly connected to a first terminal of the third capacitor; and

10. The signal processing circuit of claim 7, wherein the second path comprises:

a second capacitor;

11. The signal processing circuit of claim 10, wherein the at least one fourth path respectively comprises:

12. The signal processing circuit of claim 7, wherein the shaping module further comprises:

13. The signal processing circuit of claim 7, wherein the input signal is a single-ended signal and the shaped signal is a double-ended signal.

14. The signal processing circuit of claim 2 wherein the digital processor logically operates the high significance data with two non-overlapping clock signals to generate the plurality of switch control signals for the shaping module.

15. The signal processing circuit of claim 2, wherein the quantizer is an analog-to-digital converter that employs any one of the following structures: a single bit successive approximation structure, a fully parallel structure, a pipelined structure, or a Sigma-Delta structure.

16. A method of signal processing for a MEMS microphone, comprising:

pre-quantizing and signal shaping an input signal provided by the MEMS microphone based on a plurality of threshold ranges to obtain high significance data and a shaped signal;

combining and encoding the more significant bit data and the less significant bit data to obtain a digital signal of the MEMS microphone, wherein,

17. The signal processing method of claim 16, wherein the pre-quantizing includes preliminarily quantizing an input signal according to the plurality of threshold ranges to obtain the high significant bit data.

18. The signal processing method of claim 17, wherein the signal shaping comprises superimposing corresponding dc offsets according to the plurality of threshold ranges, respectively, to obtain the shaped signal.

19. The signal processing method of claim 18, wherein the threshold range comprises a plurality of positive polarity ranges divided by N x (Vref _ P-Vref _ N), and a plurality of negative polarity ranges divided by N x (Vref _ N-Vref _ P), wherein Vref _ P and Vref _ N represent an upper offset signal and a lower offset signal, respectively, and Vref _ P is greater than Vref _ N, N represents a natural number.

20. The signal processing method of claim 19, wherein the dc offset superimposed on the input signal is equal to-N (Vref _ P-Vref _ N) for positive polarity ranges of N (Vref _ P-Vref _ N) and (N +1) (Vref _ P-Vref _ N).

21. The signal processing method of claim 20, wherein the dc offset superimposed on the input signal is equal to + N (Vref _ P-Vref _ N) for negative polarity ranges of N (Vref _ N-Vref _ P) and (N +1) (Vref _ N-Vref _ P).

22. The signal processing method of claim 18, wherein the input signal is a single-ended signal and the shaped signal is a double-ended signal.

23. The signal processing method of claim 18, further comprising: and performing logic operation on the high effective bit data and two phases of non-overlapped clock signals to generate a plurality of switch control signals for shaping the signals.