CN112491680A - Novel middle-layer FPGA (field programmable Gate array) bus arbitration mechanism and implementation method thereof - Google Patents
Novel middle-layer FPGA (field programmable Gate array) bus arbitration mechanism and implementation method thereof Download PDFInfo
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- CN112491680A CN112491680A CN202011436211.1A CN202011436211A CN112491680A CN 112491680 A CN112491680 A CN 112491680A CN 202011436211 A CN202011436211 A CN 202011436211A CN 112491680 A CN112491680 A CN 112491680A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
- H04L12/40084—Bus arbitration
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Abstract
The invention discloses a novel middle-layer FPGA bus arbitration mechanism and an implementation method thereof, and relates to a bus arbitration mechanism. The bus of the invention is provided with a plurality of nodes which are interconnected, each node is provided with a bus control application signal line (output) and an application success signal line (input), each node needs to apply bus control power to a bus arbitration module before initiating bus communication, the bus arbitration module distributes the bus control power according to a time priority principle and sends an application success signal to the node, the node carries out 1-time data transmission after obtaining the control power, in order to prevent the node from occupying the bus for a long time, the data transmission of each time is regulated to be 1 data frame (maximum 1KB), and the bus control power is released (the bus control application signal is withdrawn) after the transmission is finished. The arbitration module performs time-limited control on each transmission to prevent the bus from being occupied for a long time when the node communication fails.
Description
Technical Field
The invention relates to a bus arbitration mechanism, in particular to a novel intermediate layer FPGA bus arbitration mechanism and an implementation method thereof.
Background
In the integrated system, BLVDS bus communication adopts multipoint connection and half-duplex communication, and the bus width is 4 bit data lines and 1 bit clock line; the frequency of the clock is 20 MHz. The bus adopts a many-to-many communication mode to realize multi-master communication, so a bus arbitration mechanism is required. Any node needs to initiate one-time transmission, the bus control right must be obtained first, the master control node immediately gives up the bus control right after sending 1 data frame, the node still needs to send data, the bus control right needs to be reapplied, and the mechanism ensures the communication real-time performance of each node.
In summary, the present invention designs a novel intermediate layer FPGA bus arbitration mechanism and an implementation method thereof.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a novel intermediate layer FPGA bus arbitration mechanism and an implementation method thereof.A bus arbitration module distributes bus control right according to a time priority principle and sends a signal of successful application to a node, the node performs 1 time of data transmission after obtaining the control right, in order to prevent the node from occupying the bus for a long time, the data transmission at each time is regulated to be 1 data frame (maximum 1KB), and the bus control right is released (the bus control application signal is withdrawn) after the transmission is finished. The arbitration module performs time-limited control on each transmission to prevent the bus from being occupied for a long time when the node communication fails.
In order to achieve the purpose, the invention is realized by the following technical scheme: the utility model provides a novel intermediate level FPGA bus arbitration mechanism, includes external signal filtering module, counter module and arbitration module, and external signal filtering module is connected with arbitration module, and arbitration module embeds for the overtime counter module who judges and provide data.
An implementation method of a novel intermediate layer FPGA bus arbitration mechanism comprises the following flow of arbitration mechanism:
(1) scanning all application lines once, if all the application lines are invalid, continuing to scan, and if not all the application lines are invalid, entering a sequential scanning program;
(2) when the request is scanned to be effective, the effective request is stored in the forefront of the priority list, effective response is output, and the current response path is timed. During this period, rescanning continues;
(3) judging whether the scanning is finished or not, if not, continuing the scanning, and if the scanning is finished, judging whether the application is all valid or not;
(4) if all applications are effectively stored in the priority list, monitoring whether the priority list has a request to cancel or not, if the request has the request to cancel, updating the priority list in time, deleting cancelled bits, sequentially moving the subsequent paths forward by one bit, and then entering step 5;
(5) if the request is not cancelled and the scanning is finished, entering the step 5;
(6) judging whether the bus is overtime or not, if yes, moving all the lists forward by one bit, clearing the current responded bus, and then returning to an overtime judgment state; if not, entering the next step;
(7) judging whether the current scanning path is effective or not, if not, continuously judging whether the invalid path is in the priority list, if not, entering the step 5, and if so, entering the step 4, and monitoring the request revocation condition;
(8) if the current scanning path is effective, judging whether the path is in the priority list;
(9) if the valid path exists in the list, the valid path is not stored in the list, repeated application is avoided, whether the valid path is overtime is judged, if the valid path is overtime, the list is moved forward by one bit, the current responded bus is cleared, and the step 5 is carried out; if not, directly entering step 5;
(10) if the effective path does not exist in the list, storing the path in the tail of the priority list, judging whether the path is overtime, if the path is overtime, moving all the paths in the list forward by one bit, clearing the current responded bus, and entering the step 5; if not, entering the next step;
(11) judging whether the priority list is full, entering a step 4 if the priority list is full, and entering a step 5 if the priority list is not full;
(12) otherwise, step 1 is entered.
The invention has the beneficial effects that: the bus of the invention is provided with a plurality of nodes which are interconnected, each node is provided with a bus control application signal line (output) and an application success signal line (input), each node needs to apply bus control power to a bus arbitration module before initiating bus communication, the bus arbitration module distributes the bus control power according to a time priority principle and sends an application success signal to the node, the node carries out 1-time data transmission after obtaining the control power, in order to prevent the node from occupying the bus for a long time, the data transmission of each time is regulated to be 1 data frame (maximum 1KB), and the bus control power is released (the bus control application signal is withdrawn) after the transmission is finished. The arbitration module performs time-limited control on each transmission to prevent the bus from being occupied for a long time when the node communication fails.
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The invention is described in detail below with reference to the drawings and the detailed description;
FIG. 1 is a schematic diagram of a BLVDS bus arbitration module according to the present invention;
FIG. 2 is a schematic diagram of an arbitration mechanism FPGA component module according to the present invention;
FIG. 3 is a flow chart of the arbitration mechanism of the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
Referring to fig. 1 to 3, the following technical solutions are adopted in the present embodiment: the utility model provides a novel intermediate level FPGA bus arbitration mechanism, includes external signal filtering module, counter module and arbitration module, and external signal filtering module is connected with arbitration module, and arbitration module embeds for the overtime counter module who judges and provide data. Because the request signal is an external signal, filtering is required to be performed first, so as to avoid glitches.
An implementation method of a novel intermediate layer FPGA bus arbitration mechanism comprises the following flow of arbitration mechanism:
(1) scanning all application lines once, if all the application lines are invalid, continuing to scan, and if not all the application lines are invalid, entering a sequential scanning program;
(2) when the request is scanned to be effective, the effective request is stored in the forefront of the priority list, effective response is output, and the current response path is timed. During this period, rescanning continues;
(3) judging whether the scanning is finished or not, if not, continuing the scanning, and if the scanning is finished, judging whether the application is all valid or not;
(4) if all applications are effectively stored in the priority list, monitoring whether the priority list has a request to cancel or not, if the request has the request to cancel, updating the priority list in time, deleting the cancelled bit, sequentially moving the subsequent path number forward by one bit, and then entering the step (5);
(5) if the request is not cancelled and the scanning is finished, entering the step (5);
(6) judging whether the bus is overtime or not, if yes, moving all the lists forward by one bit, clearing the current responded bus, and then returning to an overtime judgment state; if not, entering the next step;
(7) judging whether the current scanning path is effective or not, if not, continuously judging whether the invalid path is in the priority list, if not, entering the step (5), and if so, entering the step (4) and monitoring the request revocation condition;
(8) if the current scanning path is effective, judging whether the path is in the priority list;
(9) if the valid path exists in the list, the valid path is not stored in the list, repeated application is avoided, whether the valid path is overtime or not is judged, if the valid path is overtime, all the lists are moved forward by one bit, the current responded bus is cleared, and the step (5) is carried out; if not, directly entering the step (5);
(10) if the effective path does not exist in the list, storing the path in the queue tail of the priority list, judging whether the path is overtime, if the path is overtime, moving all the paths in the list forward by one bit, clearing the current responded bus, and entering the step (5); if not, entering the next step;
(11) judging whether the priority list is full, entering a step (4) if the priority list is full, and entering a step (5) if the priority list is not full;
(12) otherwise, the process proceeds to step (1).
In the arbitration simulation of the present embodiment, a high-speed clock (50MHz) is used to scan the request lines (REQ #) of all nodes, and the node numbers are stored in the priority sequence FIFO according to the order of signals, and if there are multiple request signals at the same time, the priority ordering is performed from small to large according to the node numbers. And the arbitration output module determines to output a corresponding application success signal (ACK #) according to the node number stored in the priority sequence FIFO. When a node relinquishes bus control (deasserts the REQ # signal), the arbitration module is triggered to clear the tag of the node in the priority queue FIFO and perform the next arbitration.
The FPGA interface list of the arbitration module is shown in table 1.
TABLE 1 arbitration module interface List
In this embodiment, the bus arbitration module allocates the bus control right according to the time-first principle, and sends the application success signal to the node, and the node performs 1 data transmission after obtaining the control right, and in order to prevent the node from occupying the bus for a long time, it is specified that each data transmission is 1 data frame (maximum 1KB), and the bus control right is released (bus control application signal is cancelled) after the transmission is completed. The arbitration module performs time-limited control on each transmission to prevent the bus from being occupied for a long time when the node communication fails.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (2)
1. The utility model provides a novel intermediate level FPGA bus arbitration mechanism, its characterized in that includes external signal filtering module, counter module and arbitration module, and external signal filtering module is connected with arbitration module, and arbitration module embeds the counter module that provides data for overtime judgement.
2. The novel intermediate layer FPGA bus arbitration mechanism and the implementation method thereof as claimed in claim 1, wherein the flow of the arbitration mechanism is as follows:
(1) scanning all application lines once, if all the application lines are invalid, continuing to scan, and if not all the application lines are invalid, entering a sequential scanning program;
(2) when the request is scanned to be effective, the effective request is stored in the forefront of the priority list, effective response is output, and the current response path is timed; during this period, rescanning continues;
(3) judging whether the scanning is finished or not, if not, continuing the scanning, and if the scanning is finished, judging whether the application is all valid or not;
(4) if all applications are effectively stored in the priority list, monitoring whether the priority list has a request to cancel or not, if the request has the request to cancel, updating the priority list in time, deleting the cancelled bit, sequentially moving the subsequent path number forward by one bit, and then entering the step (5);
(5) if the request is not cancelled and the scanning is finished, entering the step (5);
(6) judging whether the bus is overtime or not, if yes, moving all the lists forward by one bit, clearing the current responded bus, and then returning to an overtime judgment state; if not, entering the next step;
(7) judging whether the current scanning path is effective or not, if not, continuously judging whether the invalid path is in the priority list, if not, entering the step (5), and if so, entering the step (4) and monitoring the request revocation condition;
(8) if the current scanning path is effective, judging whether the path is in the priority list;
(9) if the valid path exists in the list, the valid path is not stored in the list, repeated application is avoided, whether the valid path is overtime or not is judged, if the valid path is overtime, all the lists are moved forward by one bit, the current responded bus is cleared, and the step (5) is carried out; if not, directly entering the step (5);
(10) if the effective path does not exist in the list, storing the path in the queue tail of the priority list, judging whether the path is overtime, if the path is overtime, moving all the paths in the list forward by one bit, clearing the current responded bus, and entering the step (5); if not, entering the next step;
(11) judging whether the priority list is full, entering a step (4) if the priority list is full, and entering a step (5) if the priority list is not full;
(12) otherwise, the process proceeds to step (1).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113722069A (en) * | 2021-09-06 | 2021-11-30 | 北京左江科技股份有限公司 | Novel bus polling scheduling method and system based on FPGA |
| CN114090493A (en) * | 2021-11-29 | 2022-02-25 | 深圳市科中云技术有限公司 | Data transmission control method based on RS485 bus and related device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114090493B (en) * | 2021-11-29 | 2024-09-17 | 深圳市科中云技术有限公司 | Data transmission control method based on RS485 bus and related device |
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Application publication date: 20210312 |