CN112491496B - Synchronous serial port multi-level cache receiving and forwarding method based on FPGA - Google Patents
Synchronous serial port multi-level cache receiving and forwarding method based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0002—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission rate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
- H04L1/0016—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy involving special memory structures, e.g. look-up tables
Abstract
The invention discloses a synchronous serial port multi-level cache receiving and forwarding method based on FPGA, which comprises the steps of judging cache capacity and identifiers through a first-level cache, calculating and judging checksums, optionally supplementing calculation and judging checksums through a second-level cache, and balancing data flow rates of a sender and a receiver through a last-level cache. The invention adopts a multi-level cache structure, can effectively solve the problems of wrong data, missing data, majority data and the like in the synchronous serial port, effectively solves the problem of mismatching of the transmission rate of which the sending data rate is greater than the receiving data rate in part of time periods, and has high data packet receiving density and high utilization rate of storage resources.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a synchronous serial port multi-level cache receiving and forwarding method based on an FPGA.
Background
The synchronous serial port is a signal transmission form that two signal lines transmit signals, one transmits data and the other transmits a clock associated with the channel. Compared with asynchronous serial single-wire transmission, the synchronous serial occupies twice as much resources on a transmission line as an asynchronous serial, but because of a channel associated clock, the synchronous serial has higher transmission data rate and transmission capacity which can reach 5 to 10 times of that of the asynchronous serial, so the synchronous serial single-wire transmission method is widely applied to signal transmission in the fields of radar, communication, control and the like. An FPGA (field programmable gate array) is widely applied to scenes such as logic binding in the fields of radar, communication, control and the like due to flexible programmable characteristics and strong computing power. The logic binding refers to the behavior that different information is input and processed by utilizing the programmable characteristic of the FPGA and then forwarded to other operation nodes. The processing can include zero to several items in the processing modes of analysis, caching, checking, modification, increase and decrease and the like. Because the application field of the FPGA is overlapped with the application field of the synchronous serial port, the application requirement that the FPGA receives data through the synchronous serial port and then forwards the data exists.
The synchronous serial port protocol is the design basis of the synchronous serial port receiving and forwarding method. The synchronous serial port protocol with complete functions is characterized in that each data packet consists of a packet header, an identifier (optional), a length, effective data, a checksum and a packet tail (optional). The packet head and the packet tail are used for judging whether the packet has the data error problems of a majority, a minority and the like, and the packet tail can be selected under the conditions of the packet head, the length and the checksum. The identifier is used for judging whether the data of the packet needs to be processed or not, and can be discarded if the data does not need to be processed, and the identifier can be selected in a non-broadcast mode. The length is used for judging whether the buffer space is enough or not, and whether the data packet has the data error problems of a majority, a minority and the like can be judged by matching with the packet header and the checksum. The checksum is used to determine whether the data is erroneous.
The FPGA realizes the synchronous serial port receiving and then forwarding and relates to three processing nodes: the sending party of the synchronous serial data, the FPGA is used as the forwarding party after the synchronous serial data is received, and the receiving party after the synchronous serial data is forwarded. The synchronous serial port receives and forwards the data, and the synchronous serial port comprises two forms of active forwarding and passive forwarding. The active forwarding means that data forwarding is initiated by a forwarding party, the forwarding party is simple to control, and the receiving party is poor in flexibility. The passive forwarding mode refers to that a receiver initiates data forwarding, so that the receiver has greater flexibility in processing data.
Three parties for receiving and forwarding the synchronous serial port are divided into three processors, and signal transmission can be interfered by various factors. The signal transmission may be interfered with packet problems such as lost, majority, and erroneous data. In addition, because the sending party and the receiving party belong to different processors, even if the design can ensure that the transmission rates of the sending party and the receiving party are approximately balanced, the problem of mismatching of the transmission rates of the sending data rate and the receiving data rate can also occur in a part of time period. When a data packet problem occurs, a wrong packet needs to be identified and eliminated, and influence on subsequent processing nodes is avoided. When a problem data packet is processed, influence on other correct data packets needs to be avoided as much as possible. For the problem of mismatching of transmission rate, data packets need to be buffered as much as possible under the condition that storage resources are fixed, so that the influence of the mismatching of transmission rate is reduced, and the utilization efficiency of the storage resources is improved.
For the synchronous serial port received data caching, the existing implementation methods mainly include single-level caching, ping-pong caching and other caching methods. The buffer memory has two main functions, namely, balancing the receiving rate and the forwarding rate on one hand, and ensuring that other normal data packets are not influenced when the data packets are in problem.
Specifically, for a single level cache, there are two problems: one is that only one packet of incoming wave data is cached in a single-level cache, if the next packet of data arrives and the cache still has data, the cache is reset and emptied, the advantage is that the processing flow cannot be blocked, and the disadvantage is that the cache is reset when the data in the cache is forwarded for half, so that the data packet which is being read out is wrong. The other method is that multiple packets of incoming wave data are cached in a single-level cache, once the residual capacity in the cache is lower than the data length of the current arrival packet, the data of the current arrival packet data can be lost, so that the subsequent processing is influenced.
For ping-pong cache, the data problems of error, leakage, majority, etc. can be handled. The ping-pong buffer has the defects of weak capability and low resource utilization rate in solving the problem of mismatching of the transmission rate of which the sending data rate is greater than the receiving data rate in a part of time period. For ping-pong cache, at most two serial port data packets can be stored, the storage quantity is small, and the capability of balancing the receiving rate and the forwarding rate is weak. When the time interval for sending the dense short serial port data packets by the sender and reading the data packets by the receiver is large, the problem of packet loss occurs, the problem cannot be solved by increasing the capacity of a single buffer, and the control is complex while the resource utilization rate is low. If the number of the caches of ping-pong operation is increased, the generalized ping-pong operation that a plurality of caches store data in turn is changed, the problem of low resource utilization rate is further amplified, the control flow is more complicated, and the stability is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a synchronous serial port multi-level cache receiving and forwarding method with high reliability and resource utilization rate, and effectively solve the problem of mismatching of transmission rates of which the sending data rate is greater than the receiving data rate in part of time periods.
In order to solve the technical problem, the invention provides a synchronous serial port multilevel cache receiving and forwarding method based on an FPGA, which comprises the following steps:
step 1, receiving synchronous serial port data
Converting received serial single-bit data into parallel multi-bit data, judging packet header correctness and identifiers, setting a receiving flag to be 1 for data packets needing to be forwarded, and otherwise, setting the receiving flag to be 0;
step 2, storing the synchronous serial port received data into a first-level cache
Under the condition that the checksum needs to be calculated, the checksum is calculated in parallel while the data packet is stored in the first-level cache;
if the time delay of the calculated checksum is long, the intermediate value of the calculated checksum is obtained;
step 3, judging the receiving mark
Judging the receiving mark generated in the step 1, if the mark is 0, resetting and clearing the data of the package by the first-level cache;
if the flag is 1, receiving the packet data; if the checksum needs to be calculated and the time delay of the checksum is long, entering the step 4; if the checksum needs to be calculated and the calculation of the checksum has short delay, the step 5 is carried out; if the checksum does not need to be calculated, the step 6 is carried out;
step 4, storing the synchronous serial port received data into a second level cache
The second-level cache stores the read data of the first-level cache, obtains a middle value for calculating the checksum by using the step 2, and continuously calculates the checksum of the received data packet;
step 5, judging the check sum
Under the condition that the calculation checksum delay is short, comparing the calculated checksum with the received checksum, if the calculated checksum and the received checksum are not equal, determining that the data of the packet is abnormal, and resetting and clearing the data of the packet by the first-level cache;
under the condition of long time delay of the calculated checksum, comparing the calculated checksum with the received checksum, if the checksum is not equal, determining that the data of the packet is abnormal, and resetting and clearing the data of the packet by the second-level cache;
step 6, storing the synchronous serial port received data into the last-level cache
The last-level cache receives and stores read data of the first-level cache or the second-level cache;
step 7, synchronous serial port data forwarding
And the FPGA adopts a passive forwarding mode or an active forwarding mode to forward synchronous serial port data.
Further, the step 2 starts timing after receiving the data packet, if a packet of data is not stored in a specific time, it is determined that a missing number error occurs in the packet, the first-level cache resets and clears the packet of data, and resets and clears the checksum or the intermediate value of the checksum;
the specific time is formed by the receiving time of the longest data packet length in all data packets of the sending party plus a protection time.
Further, the last level cache capacity is larger than the cache gap capacity,
the cache gap capacity calculation method comprises the following steps:
calculating the fastest rate and duration of sending by the sending end to obtain the sending data volume at the moment;
calculating the slowest receiving rate and the same duration time of the receiving end to obtain the current forwarding data volume;
the difference between the sending data volume and the forwarding data volume is the buffer gap capacity.
Further, the step 3 judges whether the last-level cache has enough cache space according to the length of the data packet in the first-level cache, and if the last-level cache space is smaller than the length of the data packet, the first-level cache clears the data packet through resetting.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a receiving and forwarding method for serially and multistage caching incoming information of a synchronous serial port based on an FPGA (field programmable gate array). Compared with a single-level cache structure, the multi-level cache structure can improve the reliability of receiving and forwarding of the synchronous serial port, and for ping-pong cache, the multi-level cache structure can improve the receiving density of the synchronous serial port data packet and improve the utilization efficiency of storage resources. The multi-level cache structure can calculate and judge the checksum through the first-level cache and judging the cache capacity and the identifier, and the selectable second-level cache can supplement the calculation and judge the checksum, and the last-level cache balances the data flow rates of a sender and a receiver. The multi-level cache structure can effectively solve the problems of data error, data leakage, majority and the like in the synchronous serial port, effectively solve the problem that the transmission rate of sending data rate greater than the receiving data rate is not matched in part of time period, and has high receiving density of data packets and high utilization efficiency of storage resources.
Drawings
FIG. 1 is a schematic flow chart of a synchronous serial port multi-level cache receiving and forwarding method;
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention adopts a passive forwarding mode and is compatible with an active forwarding mode. As shown in fig. 1, the method for receiving and forwarding synchronous serial ports based on FPGA provided in the present invention includes the following steps:
step S1, serial-parallel conversion;
specifically, the serial-to-parallel conversion process converts the received serial single-bit data into parallel multi-bit data, and the bit width of the multi-bit data is the data bit width before the data enters the serial port at the sender and is sent. The serial-parallel conversion is the basis for receiving and analyzing the synchronous serial port.
Step S2, judging packet header and identifier;
step S201, determining the packet header
And the FPGA judges the packet header, if the packet header is not the packet header, the FPGA abandons the data and continues to judge the packet header. The step is to shield the input noise signal, the interfered serial port receiving data and the abnormal data which are excessive in the previous data packet, thereby avoiding the influence on the subsequent processing flow and the subsequent processing node.
After the packet header is judged to be correct, the data processing is divided into two parallel paths, one path performs step S202, and the other path performs step S301.
Step S202, judging identifier
The step is an optional step, when the data sent in the serial port is sent by a sender and a receiver in a one-to-one manner, and the sender and the receiver are confirmed to receive the data, the identifier does not exist, and then the receiving flag is set to be 1.
If the sending data is broadcast content, the sender and the receiver send the data one to one, and then the identifier is needed to judge whether the data needs to be forwarded by the forwarding party. And judging the identifier, wherein the identifier shows that the packet data needs to be forwarded by the forwarding party, setting the receiving flag to be 1, and otherwise, setting the receiving flag to be 0.
Step S3, synchronous serial port multilevel cache and analysis;
the method comprises the following steps:
s301, storing the synchronous serial port received data into a first-level cache
And storing the data received after the step S201 into a first-level cache, and judging whether caching is finished by one packet of data or not according to the packet length.
In the case of a checksum that needs to be computed, the checksums are computed in parallel while the packet is stored in the first level cache.
Further, timing is started after the data packet is received, if a packet of data is not stored in a specific time, it is judged that the packet has a missing number error, the first-level cache clears the packet of data through resetting, and resets and clears the checksum or the intermediate value of the checksum. The specific time is composed of a reception time of the longest packet length among all packets of the transmitting side plus a guard time. This determination identifies a missing number error and reduces the impact on the next packet of data.
And entering the next process after the storage of one packet of data is finished.
Step S302, calculating a checksum
The verification and the summation are set by an initiating end of the data, and finally the nodes are used for judgment. For the receiving-end processor, if the processing capacity is limited, the FPGA is expected to shield the data packet with the checksum error so as to reduce the processing load, and the FPGA calculates the checksum at the moment.
Under the condition of short time delay of calculating the checksum, the checksum calculation can be completed in a short time after the data in the data packet is received. The checksum calculation is performed in parallel with step S301, and the checksum result waits for the determination of flow S305.
Under the condition of long checksum calculation delay, checksum calculation cannot be completed in a short time after data in a data packet is received. The checksum may not necessarily be calculated when the data is read from the first level cache. In this case, the checksum is calculated in parallel with step S301, after the level one cache storage of S301 is completed, the intermediate value of the calculated checksum is obtained in step S302, and the calculation of the intermediate value of the calculated checksum is continued in step S304. The checksum result waits for the determination of the flow S305.
Calculating the length and the length of the checksum delay are relative concepts, mainly depend on the data packet transmission density of the synchronous serial port transmitter, if the minimum value of the time interval between the data packets is enough to calculate the checksum, the calculation of the checksum delay is considered to be short, and the checksum can be calculated by the step S302. Otherwise, it is considered that the checksum delay time needs to be calculated, and the checksum calculation is continued in step S304.
Step S303, judging receiving mark
Judging the receiving flag generated in step S202, if the flag is 0; the data of the packet does not need to be processed, and the first-level cache clears the data of the packet through resetting, so that the resource occupation is avoided.
If the flag is 1, receiving the packet data; if the checksum needs to be calculated and the checksum delay time is calculated, the procedure goes to step S304; if the checksum needs to be calculated and the checksum calculation delay is short, go to step S305; if the checksum does not need to be calculated, the step S306 is executed;
further, whether the last-level cache has enough cache space is judged according to the length of the data packet in the first-level cache, and if the last-level cache space is smaller than the length of the data packet, the first-level cache clears the complete data of the packet through resetting. This operation may avoid half-packet data in the last-level cache, which may also affect the next packet of normal data.
Step S304, storing the synchronous serial port receiving data into a second level cache
And if the checksum needs to be calculated and the checksum delay time is calculated, setting a second-level cache.
The second-level cache stores the read data of the first-level cache, and continues to calculate the checksum of the received packet using the intermediate value of the calculated checksum obtained in step S302, and the calculated checksum is determined in flow S305.
Step S305, judging the checksum
If the checksum is calculated, this step is performed.
And under the condition of short time delay of the calculated checksum, comparing the calculated checksum with the received checksum, if the calculated checksum and the received checksum are not equal, determining that the data of the packet is abnormal, and clearing the data of the packet through resetting by the first-level cache.
And under the condition of long time delay of the calculated checksum, comparing the calculated checksum with the received checksum, if the calculated checksum and the received checksum are not equal, determining that the data of the packet is abnormal, and resetting and clearing the data of the packet by the second-level cache.
After the calculation is completed, if the checksum is correct, the read data is transferred to the last-level buffer.
Step S306, the synchronous serial port receiving data is stored in the last-level cache
Specifically, under the condition that the checksum is not judged or the checksum calculation delay is short, the last-level cache receives and stores the read data of the first-level cache, when the read data of the first-level cache is received, if the data is not stored in the cache, the last-level cache non-empty flag is pulled down, and if the data is stored in the cache, the last-level cache non-empty flag is pulled up. After the last-level buffer receives the packet data, an interrupt pulse is issued.
And under the conditions of judging the checksum and calculating the checksum delay time, the last-level cache receives and stores the read data of the second-level cache, when the read data of the second-level cache is received, if the data are not stored in the cache, the non-empty flag of the last-level cache is pulled down, and if the data are stored in the cache, the non-empty flag of the last-level cache is pulled up. After the last-level buffer receives the packet data, an interrupt pulse is issued.
Further, the last-level cache capacity is greater than the cache gap capacity, and the cache gap capacity calculation method includes:
calculating the fastest rate and the duration time of sending by the sending end to obtain the sending data volume at the moment;
calculating the slowest receiving rate and the same duration time of the receiving end to obtain the current forwarding data volume;
the difference value between the sending data volume and the forwarding data volume is the cache gap capacity.
Further, if the storage resource can not meet the requirement of the gap capacity and the data in the last-level cache is read by the first-level cache, judging whether the storage space of the last-level cache is larger than the length of the data packet in the first-level cache before reading, and if the storage space of the last-level cache is smaller than the length of the data packet, the first-level cache clears the complete data of the packet through resetting. This operation may avoid half-packet data in the last-level cache, which may also affect the next packet of normal data.
If the data bit width required by the receiver is different from the data bit width required by the sender, performing bit width conversion in the step, and converting the data bit width required by the receiver into the data bit width required by the sender.
Step S4, synchronous serial port data forwarding
Specifically, synchronous serial port data forwarding is divided into two modes of active forwarding and passive forwarding by the FPGA.
Specifically, in the passive forwarding mode, the FPGA sends the non-empty flag and the interrupt pulse signal generated in step S306 to the data receiving side, and after the data receiving side initiates the data forwarding operation, the FPGA accesses the read enable signal sent from the data receiving side to the last-level cache, reads out the data in the last-level cache, and transmits the data to the data receiving side. When the active forwarding is carried out, the FPGA automatically judges the non-empty mark and the interrupt pulse signal, automatically generates a read enabling signal to be accessed into the last-level cache, reads data in the last-level cache and transmits the data to a data receiving party.
The above-mentioned embodiments are only used for explaining and explaining the technical solution of the present invention, but should not be construed as limiting the scope of the claims. It should be clear to those skilled in the art that any simple modification or replacement based on the technical solution of the present invention will also result in new technical solutions that fall within the scope of the present invention.
Claims (4)
1. A multilevel cache receiving and forwarding method based on an FPGA synchronous serial port is characterized by comprising the following steps:
step 1, receiving synchronous serial port data
Converting received serial single-bit data into parallel multi-bit data, judging packet header correctness and identifiers, setting a receiving flag to be 1 for data packets needing to be forwarded, and otherwise, setting the receiving flag to be 0;
step 2, storing the synchronous serial port received data into a first-level cache
Under the condition that the checksum needs to be calculated, the checksum is calculated in parallel while the data packet is stored in the first-level cache;
under the condition of long time delay of the checksum calculation, namely the minimum value of the time interval between the data packets is not enough to calculate the checksum, obtaining the intermediate value of the calculated checksum;
step 3, judging the receiving mark
Judging the receiving mark generated in the step 1, if the mark is 0, resetting and clearing the data of the package by the first-level cache;
if the flag is 1, receiving the packet data; if the checksum needs to be calculated, and under the condition that the checksum delay time is calculated, entering a step 4; if the checksum needs to be calculated and the time delay of the checksum calculation is short, the step 5 is carried out; if the checksum does not need to be calculated, the step 6 is carried out;
step 4, storing the synchronous serial port received data into a second-level cache
The second-level cache stores the read data of the first-level cache, and continuously calculates the checksum of the received data packet by using the intermediate value of the calculated checksum obtained in the step (2);
step 5, judging the checksum
Under the condition that the calculation checksum delay is short, comparing the calculated checksum with the received checksum, if the calculated checksum and the received checksum are not equal, determining that the data of the packet is abnormal, and resetting and clearing the data of the packet by the first-level cache;
under the condition of calculating the long time delay of the checksum, comparing the calculated checksum with the received checksum, if the checksum is not equal, judging that the data of the packet is abnormal, and resetting and clearing the data of the packet by the secondary cache;
step 6, storing the synchronous serial port received data into the last-level cache
The last-level cache receives and stores read data of the first-level cache or the second-level cache;
step 7, synchronous serial port data forwarding
And the FPGA adopts a passive forwarding mode or an active forwarding mode to forward synchronous serial port data.
2. The method for receiving and forwarding the multi-level cache based on the synchronous serial port of the FPGA according to claim 1, wherein the step 2 is to start timing after receiving the data packet, judge that the packet has a loss error if a packet of data is not stored in a specific time, reset and clear the packet of data by the first-level cache, and reset and clear the checksum or the intermediate value of the checksum;
the specific time is formed by the receiving time of the longest data packet length in all data packets of the sending party plus a protection time.
3. The FPGA-based synchronous serial port multi-level cache receiving and forwarding method according to claim 1 or 2, wherein the last-level cache capacity is larger than the cache gap capacity,
the cache gap capacity calculation method comprises the following steps:
calculating the fastest rate and duration of sending by the sending end to obtain the sending data volume at the moment;
calculating the slowest receiving rate and the same duration time of the receiving end to obtain the current forwarding data volume;
the difference between the sending data volume and the forwarding data volume is the buffer gap capacity.
4. The method according to claim 3, wherein if the storage resources cannot meet the requirement of the gap capacity and the data in the last-level cache is read by the first-level cache, it is determined before the reading in step 6 whether the storage space of the last-level cache is larger than the length of the data packet in the first-level cache, and if the storage space of the last-level cache is smaller than the length of the data packet, the first-level cache clears the data packet by resetting.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6088744A (en) * | 1998-02-13 | 2000-07-11 | Agilent Technologies | Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto |
| CN102331981A (en) * | 2011-09-16 | 2012-01-25 | 国电南瑞科技股份有限公司 | Method for realizing conflict-free real-time data access in FPGA (field programmable gate array) |
| CN108153701A (en) * | 2017-12-26 | 2018-06-12 | 北京航空航天大学 | A kind of synchronous serial big data method for reliable transmission towards intelligent things |
| CN109828943A (en) * | 2019-01-16 | 2019-05-31 | 北京左江科技股份有限公司 | A kind of the raising serial ports transmission rate processing system and method for low rate communication network |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9348783B2 (en) * | 2012-04-19 | 2016-05-24 | Lockheed Martin Corporation | Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory |
-
2019
- 2019-09-12 CN CN201910861520.4A patent/CN112491496B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6088744A (en) * | 1998-02-13 | 2000-07-11 | Agilent Technologies | Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto |
| CN102331981A (en) * | 2011-09-16 | 2012-01-25 | 国电南瑞科技股份有限公司 | Method for realizing conflict-free real-time data access in FPGA (field programmable gate array) |
| CN108153701A (en) * | 2017-12-26 | 2018-06-12 | 北京航空航天大学 | A kind of synchronous serial big data method for reliable transmission towards intelligent things |
| CN109828943A (en) * | 2019-01-16 | 2019-05-31 | 北京左江科技股份有限公司 | A kind of the raising serial ports transmission rate processing system and method for low rate communication network |
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| CN112491496A (en) | 2021-03-12 |
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