CN112491429A - Communication receiving device and clock data recovery method - Google Patents

Communication receiving device and clock data recovery method Download PDF

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Publication number
CN112491429A
CN112491429A CN201910861458.9A CN201910861458A CN112491429A CN 112491429 A CN112491429 A CN 112491429A CN 201910861458 A CN201910861458 A CN 201910861458A CN 112491429 A CN112491429 A CN 112491429A
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CN
China
Prior art keywords
digital signal
signal
equalizer
data recovery
clock data
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CN201910861458.9A
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Chinese (zh)
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CN112491429B (en
Inventor
康文柱
陈昱竹
高洵伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Global Unichip Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference

Abstract

A communication receiving device and a clock data recovery method. The communication receiving device comprises a clock pulse data recovery circuit for generating a clock pulse according to a first digital signal, an analog-digital converter, a channel evaluation circuit, an equalizer and a selector. The analog-to-digital converter is coupled to the clock data recovery circuit and is used for converting the analog signal according to the clock to generate a second digital signal. The channel evaluation circuit is used for analyzing the second digital signal to output a switching signal. The equalizer is coupled to the analog-to-digital converter for equalizing the second digital signal to generate a third digital signal. The selector is coupled between the equalizer and the clock data recovery circuit and is used for outputting the second or third digital signal as the first digital signal according to the switching signal. The clock data recovery method of the communication receiving device can make a proper trade-off between signal delay and signal distortion so as to improve the communication stability.

Description

Communication receiving device and clock data recovery method
Technical Field
The present disclosure relates to a communication receiving device, and more particularly, to a communication receiving device using a clock data recovery method.
Background
As data transmission speeds increase, Inter Symbol Interference (ISI) in signals also increases, and thus clock data recovery also increases. However, inter-symbol interference in the signal makes the clock data recovery operation difficult and inefficient.
Disclosure of Invention
One embodiment of the present disclosure relates to a communication receiving apparatus, which includes a clock data recovery circuit, an analog-to-digital converter, a channel estimation circuit, a first equalizer, and a selector. The clock data recovery circuit is used for generating a clock signal according to the first digital signal. The analog-to-digital converter is coupled to the clock data recovery circuit and is used for converting the first analog signal according to the clock signal to generate a second digital signal. The channel evaluation circuit is used for analyzing the second digital signal to output a switching signal. The first equalizer is coupled to the analog-to-digital converter for equalizing the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer and the clock data recovery circuit and is used for outputting the second digital signal as the first digital signal or outputting the third digital signal as the first digital signal according to the switching signal.
In some embodiments, the first analog signal is associated with a second analog signal transmitted from the channel, and the channel evaluation circuit is further configured to analyze the second digital signal to evaluate a characteristic of the channel.
In some embodiments, the channel evaluation circuit is configured to measure an amplitude of the second digital signal to output the switching signal.
In some embodiments, the channel evaluation circuit is configured to measure a power of the second digital signal to output the switching signal.
In some embodiments, the selector is configured to directly output the second digital signal as the first digital signal when the power is not lower than the predetermined threshold.
In some embodiments, the selector is configured to transmit the third digital signal as the first digital signal when the power is below a predetermined threshold.
In some embodiments, the communication receiving apparatus further includes an amplifier, a second equalizer, and a gain control circuit. The amplifier is used for amplifying the second analog signal into a third analog signal. The second equalizer is coupled between the amplifier and the analog-to-digital converter and used for equalizing the third analog signal to generate a first analog signal. The gain control circuit is coupled to the analog-to-digital converter and the amplifier and used for adjusting the gain multiplying power of the amplifier according to the second digital signal.
In some embodiments, the communication receiver further comprises a third equalizer coupled to the selector for equalizing the first digital signal to generate the output signal, wherein the first equalizer and the third equalizer are feed-forward equalizers.
In some embodiments, the first equalizer equalizes the second digital signal with a delay time that is lower than a delay time of the third equalizer equalizing the first digital signal.
One embodiment of the present disclosure relates to a clock data recovery method, which includes the following operations: performing clock data recovery on the first digital signal through a clock data recovery circuit and outputting a clock signal; converting the first analog signal by a digital-to-analog converter according to the clock pulse signal to generate a second digital signal; and directly outputting the second digital signal or outputting a third digital signal as the first digital signal according to the second digital signal, wherein the third digital signal is obtained by equalizing the second digital signal.
In some embodiments, the second digital signal is output or the third digital signal is output as the first digital signal depending on the amplitude of the second digital signal.
In some embodiments, the second digital signal is output or the third digital signal is output as the first digital signal according to the power of the second digital signal.
In some embodiments, outputting the second digital signal or the third digital signal as the first digital signal according to the power of the second digital signal comprises: when the power is smaller than a preset threshold value, outputting a third digital signal as a first digital signal; and when the power is not less than the predetermined threshold, directly outputting the second digital signal as the first digital signal.
In some embodiments, the clock data recovery method further comprises: calculating, by the channel evaluation circuit, a power of the second digital signal; generating a switching signal according to the power and a preset threshold value; and outputting the second digital signal or the third digital signal as the first digital signal through the selector according to the switching signal.
In some embodiments, the clock data recovery method further comprises equalizing the first digital signal by an equalizer to output an output signal.
In some embodiments, the second digital signal is equalized to a third digital signal by an equalizer. The equalizer equalizes the second digital signal with a delay time that is less than the delay time of the feed-forward equalizer equalizing the first digital signal.
Drawings
The disclosure may be more completely understood in consideration of the following detailed description of exemplary embodiments in connection with the accompanying drawings, in which:
fig. 1 is a schematic diagram of a communication system according to some embodiments of the present disclosure;
fig. 2A is a schematic diagram of a communication receiving device in the communication system of fig. 1 according to some embodiments of the present disclosure;
fig. 2B is a schematic diagram of a communication receiving device in the communication system of fig. 1 according to another embodiment of the present disclosure;
FIG. 3 is a flowchart of a method for the communication receiving device of FIGS. 2A-2B according to some embodiments of the present disclosure;
fig. 4 is a schematic diagram of a communication receiving device in the communication system of fig. 1 according to another embodiment of the present disclosure; and
fig. 5 is a diagram illustrating a communication receiving device in the communication system of fig. 1 according to other embodiments of the present disclosure.
[ notation ] to show
10: communication system
100: communication transmitting device
150: channel
200A, 200B, 400, 500: communication receiver
210. 410, 510: amplifier with a high-frequency amplifier
220. 250, 270, 272, 274, 420, 450, 520, 550: equalizer
230. 430, 530: analog-to-digital converter
240. 440, 540: gain control circuit
280. 480, 580: channel evaluation circuit
290. 490, 590: selector device
260. 460, 560: clock data recovery circuit
Sa1, Sa2, Sa3, Sd1, Sd2, Sd3, Sd4, Sd5, D1, D1 ', CLK, SE, Sout, Sd 1': signal
TH1, TH2, TH 3: threshold value
T, T1, T2, T3: delay time
300: method of producing a composite material
S310, S320, S330, S340, S350, S360, S370: operation of
Detailed Description
The following detailed description of the embodiments is provided in conjunction with the appended drawings, but the embodiments described are merely illustrative of the embodiments and are not intended to limit the scope of the embodiments, and the description of the structural operations is not intended to limit the order of execution, any arrangement of elements that can be rearranged to produce a device with equal efficacy, all of which are intended to cover the scope of the disclosure.
As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or to the mutual operation or action of two or more elements.
As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more active and passive components to process a signal.
Refer to fig. 1. Fig. 1 is a schematic diagram of a communication system 10 according to some embodiments of the present disclosure. As shown in fig. 1, the communication system 10 includes a communication transmitter 100, a channel 150 and a communication receiver 200. The channel 150 is coupled between the communication transmitting device 100 and the communication receiving device 200, but the disclosure is not limited thereto. For example, the communication system 10 further includes connectors (not shown) coupled between the channel 150 and the communication transmitter 100, and coupled between the channel 150 and the communication receiver 200. In some embodiments, communication system 10 may be a serializer/deserializer (SerDes), but is not limited thereto.
In some embodiments, the communication transmitter 100 is configured to output the data signal D1 and transmit the data signal to the communication receiver 200 through the channel 150. The communication receiver 200 is used to receive the data signal D1' transmitted through the channel 150. In some embodiments, the data signal D1 may be an analog signal or a digital signal.
In some embodiments, when the channel 150 has a loss, the data signal D1 output from the communication transmitter 100 has a higher power than the data signal D1' received by the communication receiver 200. In some embodiments, the loss of channel 150 to data signal D1 is related to the frequency (frequency domain) of data signal D1. Generally, the channel 150 generates a higher attenuation to the high frequency component of the data signal D1, so that the loss of the low frequency portion of the data signal D1' is lower than the loss of the high frequency portion after passing through the channel 150. In other words, after the data signal D1 passes through the channel 150, the power of the high frequency and the low frequency are not symmetrical due to the attenuation difference of the high frequency and the low frequency.
In some applications, the data signal D1 has different power losses at high and low frequencies through the channel 150, resulting in signal delay at the subsequent transmission or signal processing. These delayed signals will overlap with the data signals at other time points, and further cause inter-symbol interference (ISI), which distorts the data signal D1'.
Based on the above characteristics, to reduce ISI, the communication receiving device 200 may further amplify the data signal D1 'in at least a portion of the frequency range, so that the received data signal D1' maintains the same power or the same power ratio in the frequency domain as the data signal D1.
In some embodiments, the communication receiver 200 is configured to perform clock data recovery on the data signal D1'. If the data signal D1 'is distorted (i.e., the data signal D1' is affected by the ISI), the accuracy of clock data recovery is affected. Therefore, before and during the clock data recovery, the communication receiving device 200 can determine the power of the data signal D1 'to determine whether the power of the data signal D1' needs to be adjusted. Thus, the accuracy of clock data recovery and the reliability of the communication system 10 can be further improved.
Refer to fig. 2A. Fig. 2A is a schematic diagram of a communication receiving device 200A according to some embodiments of the present disclosure. The communication receiver 200A is an embodiment of the communication receiver 200 in the communication system 10. In some embodiments, the communication receiver 200A includes an amplifier 210, an equalizer 220, an adc 230, a gain control circuit 240, an equalizer 250, a clock data recovery circuit 260, an equalizer 270, a channel estimation circuit 280, and a selector 290.
As shown in fig. 2A, the amplifier 210 is coupled to the equalizer 220. The equalizer 220 is coupled to the adc 230. The adc 230 is coupled to the gain control circuit 240, the equalizer 270, the channel estimation circuit 280, the clock data recovery circuit 260 and the selector 290. The gain control circuit 240 is further coupled to the amplifier 210 and the analog-to-digital converter 230. The clock data recovery circuit 260 is further coupled to a node between the selector 290 and the equalizer 250.
In some embodiments, the amplifier 210 receives the analog signal Sa1 and amplifies the analog signal Sa1 to generate the analog signal Sa 2. In some embodiments, the gain of the amplifier 210 may be adjusted by the gain control circuit 240, and the amplifier 210 may amplify the analog signal Sa1 into the analog signal Sa2 according to the gain. In some embodiments, amplifier 210 is a Variable Gain Amplifier (VGA). In some embodiments, the gain control circuit 240 may be implemented by an Automatic Gain Controller (AGC) to automatically adjust the gain magnification of the amplifier 210 according to the power of the digital signal Sd 2.
In some embodiments, the equalizer 220 is configured to receive the analog signal Sa2 and equalize the analog signal Sa2 to generate the analog signal Sa 3. In some embodiments, the equalizer 220 reduces the power of the low frequency part of the analog signal Sa2 to make the power of the low frequency part of the analog signal Sa2 similar to the power of the high frequency part of the analog signal Sa 2. In other words, the equalizer 220 may be a high pass filter. In some embodiments, the equalizer 220 is a Continuous Time Line Equalizer (CTLE).
In some embodiments, the clock data recovery circuit 260 is configured to receive the digital signal Sd1 and generate the clock signal CLK according to the digital signal Sd 1. The clock data recovery circuit 260 is further configured to transmit the generated clock signal CLK to the adc 230.
In some embodiments, the analog-to-digital converter 230 is configured to receive the analog signal Sa3 and the clock signal CLK, and convert the analog signal Sa3 according to the clock signal CLK to generate the digital signal Sd 2.
In some embodiments, the channel estimation circuit 280 is configured to determine whether the power of the digital signal Sd2 is smaller than a predetermined threshold TH 1. If the power of the digital signal Sd2 is lower than the predetermined threshold TH1, the equalizer 270 equalizes the digital signal Sd2 to output the digital signal Sd3, and outputs the digital signal Sd3 as the digital signal Sd1 through the selector 290. On the contrary, if the power of the digital signal Sd2 is not lower than the predetermined threshold TH1, the selector 290 directly outputs the digital signal Sd2 as the digital signal Sd 1. In some embodiments, the signal equalization performed by the equalizer 270 has a lower delay. Therefore, the overall delay of the system can be reduced, and the ISI problem can be improved through the equalization operation when the loss is high, so as to ensure the operation accuracy of the clock data recovery circuit 260.
In other embodiments, the channel estimation circuit 280 is configured to measure the amplitude of the digital signal Sd2 in the high frequency portion (and/or the low frequency portion). For example, when the amplitude of the digital signal Sd2 in the high frequency section is lower than the predetermined threshold TH1, the equalizer 270 equalizes the digital signal Sd2 to output the digital signal Sd3, and outputs the digital signal Sd3 as the digital signal Sd1 through the selector 290. On the contrary, if the amplitude of the digital signal Sd2 in the high frequency section is not lower than the predetermined threshold TH1, the selector 290 directly outputs the digital signal Sd2 as the digital signal Sd 1.
In some embodiments, the analog signal Sa3 is related to the analog signal Sa1 transmitted from the channel 150, and the evaluation circuit 280 is further configured to analyze the digital signal Sd2 to evaluate the characteristics of the channel 150.
In some embodiments, the equalizer 250 is used to equalize the digital signal Sd1 to generate the output signal Sout. The equalizer 250 is used to improve the ISI problem in the digital signal Sd 1. As shown in fig. 2A, the digital signal Sd1 is input to the equalizer 250 after being recovered to generate the output signal Sout. In some embodiments, the Equalizer 250 is a Feed Forward Equalizer (FFE).
In some embodiments, the adc 230 generates a digital signal Sd2, and transmits the digital signal Sd2 to the selector 290 and the equalizer 270, respectively. The equalizer 270 equalizes the received digital signal Sd2 into a third digital signal Sd3 for transmission to the selector 290.
In some embodiments, the channel estimation circuit 280 is configured to calculate the power of the digital signal Sd2 and generate the switching signal SE according to the power of the digital signal Sd 2. The channel evaluation circuit 280 outputs a switching signal SE to the selector 290. The selector 290 selects the output of the adc 230 or the output of the equalizer 270 to be connected to the clock data recovery circuit 260 according to the switching signal SE. In other words, according to the operation of the selector 290, the digital signal Sd2 is directly outputted as the digital signal Sd1 or the third digital signal Sd3 is outputted as the digital signal Sd1 for clock data recovery.
In other embodiments, the channel estimation circuit 280 is configured to calculate the amplitude of the digital signal Sd2 in the high frequency portion (and/or the low frequency portion), and generate the switching signal SE according to the amplitude of the digital signal Sd2 in the high frequency portion (and/or the low frequency portion). The channel evaluation circuit 280 outputs a switching signal SE to the selector 290. The selector 290 selects the output of the adc 230 or the output of the equalizer 270 to be connected to the clock data recovery circuit 260 according to the switching signal SE. In other words, according to the operation of the selector 290, the digital signal Sd2 is directly outputted as the digital signal Sd1 or the third digital signal Sd3 is outputted as the digital signal Sd1 for clock data recovery.
In some embodiments, the power and/or amplitude of the digital signal Sd2 corresponds to characteristics of the channel 150, e.g., including channel loss. For example, a smaller power and/or amplitude of the digital signal Sd2 represents a larger channel loss.
In some embodiments, the channel estimation circuit 280 may be implemented by a processing circuit that performs fast fourier transform and performs comparison operations, and the processing circuit may be configured to perform fast fourier transform according to the digital signal Sd2 to calculate the corresponding power spectral density of the digital signal Sd2 to obtain the power and/or amplitude of the digital signal Sd 2. The above-described embodiments of the channel estimation circuit 280 are provided for illustration and are not intended to be limiting.
In some embodiments, the equalizer 270 is a feed-forward equalizer. The delay time T1 of the equalizer 270 is lower than the delay time T of the equalizer 250. In some embodiments, the equalizer 270 may be implemented by a simple operation circuit, for example, the equalizer 270 may be implemented by a second-order (second-order) Z-conversion circuit. In some embodiments, the transfer function of the equalizer 270 may be-2-k1+Z-1–2-k2Z-2Wherein k1 and k2 are constants. The above-mentioned transfer function related to the equalizer 270 is used for illustration, but the present disclosure is not limited thereto.
In some embodiments, if the power of the digital signal Sd2 is large enough, the selector 290 directly outputs the digital signal Sd2 as the digital signal Sd1 for clock data recovery. In some embodiments, if the power of the digital signal Sd2 is not large enough, the digital signal Sd2 is equalized into the digital signal Sd3 by the equalizer 270, and then outputted as the digital signal Sd1 by the selector 290 for clock data recovery.
In other embodiments, if the amplitude of the digital signal Sd2 in the high frequency part is large enough, the selector 290 directly outputs the digital signal Sd2 as the digital signal Sd1 for clock data recovery. In some embodiments, if the amplitude of the digital signal Sd2 in the high frequency part is not large enough, the digital signal Sd2 is equalized into the digital signal Sd3 by the equalizer 270, and then outputted into the digital signal Sd1 by the selector 290 for clock data recovery.
In some embodiments, the channel estimation circuit 280 is further configured to compare the power of the digital signal Sd2 with a predetermined threshold TH 1. When the power of the digital signal Sd2 is not less than the predetermined threshold TH1, the channel evaluation circuit 280 transmits a switching signal SE having a first logic value to the selector 290. In response to this first logic value, the selector 290 selects to directly output the digital signal Sd2 as the digital signal Sd 1. On the contrary, when the power of the digital signal Sd2 is less than the predetermined threshold TH1, the channel estimation circuit 280 transmits the switching signal SE having a second logic value to the selector 290. In response to this second logic value, the selector 290 selects to output the digital signal Sd3 as the digital signal Sd 1.
In some embodiments, the power of the digital signal Sd2 is related to the channel 150 in the communication system 10. For example, when the channel 150 is a long channel, the loss of the channel 150 is large relative to the short channel, and therefore, a smaller power is obtained when measuring the power of the digital signal Sd 2. On the contrary, if the channel 150 is a short channel, the loss of the channel 150 is smaller than that of the long channel, so that a larger power is obtained when measuring the power of the digital signal Sd 2. In other words, the predetermined threshold TH1 is set in relation to the loss of the channel 150.
In other embodiments, the amplitude of digital signal Sd2 in the high frequency portion and in the low frequency portion is related to channel 150 in communication system 10. For example, when the channel 150 is a long channel, the loss of the channel 150 is large relative to the short channel, and therefore, a smaller amplitude is obtained when measuring the amplitude of the digital signal Sd 2. On the contrary, if the channel 150 is a short channel, the loss of the channel 150 is smaller than that of the long channel, so that a larger amplitude is obtained when measuring the amplitude of the digital signal Sd 2.
In summary, the communication receiving apparatus 200A has a function of adjusting the signal transmission path according to the power of the digital signal Sd2, so as to improve the accuracy of clock recovery and the delay time of the whole system. Further, the communication receiver 200A has a function of adjusting a path of clock recovery according to the attenuation of the channel 150.
The communication receiver 200A shown in fig. 2A is for illustrative purposes only. Various configurations of the communication receiver 200A are within the scope of the present disclosure. For example, the channel estimation circuit 280 may be integrated into the gain control circuit 240 as a part of the gain control circuit 240. Alternatively, or for example, the channel estimation circuit 280 may be disposed at other locations of the communication receiver 200A, as illustrated in fig. 4 and 5 discussed below.
Refer to fig. 2B. Fig. 2B is a schematic diagram of a communication receiving device 200B according to another embodiment of the disclosure. The communication receiver 200B is an embodiment of the communication receiver 200 in the communication system 10. For ease of understanding, reference numerals for similar elements in FIG. 2B are carried forward to reference numerals in FIG. 2A. In some embodiments, the communication receiver 200B includes an amplifier 210, an equalizer 220, an adc 230, a gain control circuit 240, an equalizer 250, a clock data recovery circuit 260, an equalizer 270, a channel estimation circuit 280, a selector 290, an equalizer 272, and an equalizer 274.
In some embodiments, the amplifier 210, the equalizer 220, the adc 230, the gain control circuit 240, the clock data recovery circuit 260, and the equalizer 250 are configured to perform similar operations as shown in fig. 2A. Similar operations will not be described herein.
Compared to fig. 2A, the communication receiver 200B includes a plurality of equalizers 270, 272, 274, each having a different delay time. The equalizer 270 equalizes the digital signal Sd2 to a digital signal Sd 3. The equalizer 272 equalizes the digital signal Sd2 to a digital signal Sd 4. The equalizer 274 equalizes the digital signal Sd2 into a digital signal Sd 5.
In some embodiments, the channel evaluating circuit 280 is configured to output the switching signal SE according to a plurality of predetermined thresholds TH1, TH2, TH3, and the predetermined thresholds TH1, TH2, TH3 differentiate the digital signals Sd2 with different powers, so that the selector 290 can select the corresponding equalizer 270, 272, 274, etc. to transmit the digital signal Sd2, the digital signal Sd3, the digital signal Sd4, or the digital signal Sd5 as the digital signal Sd1 according to the switching signal SE.
For example, the predetermined threshold TH1 is greater than the predetermined threshold TH2, and the predetermined threshold TH2 is greater than the predetermined threshold TH 3. The gain of equalizer 270 is higher than the gain of equalizer 272 and the gain of equalizer 274 is higher than the gain of equalizer 240B. Under this setting, when the power of the digital signal Sd2 is not smaller than the predetermined threshold TH1, the channel estimation circuit 280 transmits the switching signal SE to the selector 290, so that the selector 290 selects to directly output the digital signal Sd2 as the digital signal Sd 1. When the power of the digital signal Sd2 is less than the predetermined threshold TH1 and not less than the predetermined threshold TH2, the channel evaluation circuit 280 transmits the switching signal SE to the selector 290, so that the selector 290 selects to output the digital signal Sd3 as the digital signal Sd 1. In addition, when the power of the digital signal Sd2 is less than the predetermined threshold TH2 and not less than the predetermined threshold TH3, the channel evaluation circuit 280 transmits the switching signal SE to the selector 290, so that the selector 290 selects to output the digital signal Sd4 as the digital signal Sd 1. And when the power of the digital signal Sd2 is less than the predetermined threshold TH3, the channel evaluation circuit 280 transmits the switching signal SE to the selector 290, so that the selector 290 selects to output the digital signal Sd5 as the digital signal Sd 1. In this case, the delay time T1 of the equalizer 270 is smaller than the delay time T2 of the equalizer 272, and the delay time T2 of the equalizer 272 is smaller than the delay time T3 of the equalizer 274.
In other words, when the power of the digital signal Sd2 is smaller than the predetermined threshold TH1, the equalization process undergone by the digital signal Sd2 with smaller power results in the equalized digital signal Sd1 having less inter-symbol interference loss and longer delay time.
Compared to the communication receiver 200A, the communication receiver 200B has more signal transmission paths for performing clock data recovery.
Therefore, data signals with different losses and intersymbol interference can be transmitted through the communication receiving device 200 according to different signal transmission paths to perform clock data recovery. When the data power loss is not large, the inter-symbol interference of the data signal is small, and the communication receiving apparatus 200 selects the path equalization digital signal Sd2 with a smaller delay time, and then performs the clock data recovery. When the data power loss is large and the inter-symbol interference of the data signal is large, the communication receiving apparatus 200 selects the path with a long delay time to equalize the digital signal Sd2, and then performs the clock data recovery.
Refer to fig. 3. Fig. 3 is a flow chart illustrating a method 300 for the communication receiving device 200 of fig. 2A-2B according to some embodiments of the present disclosure. As shown in fig. 3, the method 300 includes operations S310, S320, S330, S340, S350, S360 and S370. The description of the method 300 refers to fig. 1, 2A, 2B and uses the reference numbers shown in fig. 1, 2A, 2B.
In operation S310, the communication receiving device 200 is enabled. In some embodiments, the communication receiving apparatus 200 is also called a Receiver (RX).
In operation S320, the communication receiving apparatus 200 receives the data signal D1' and determines whether it is a valid signal. If the received data signal D1' is a valid signal, operation S330 is performed. If the received data signal D1' is an invalid signal, operation S310 is performed.
In operation S330, the amplifier 210 transmits the analog signal Sa1 to generate the analog signal Sa2, the equalizer 220 equalizes the analog signal Sa2 to generate the analog signal Sa3, the analog-to-digital converter 230 converts the analog signal Sa3 into the digital signal Sd2, and the channel estimation circuit 280 estimates a characteristic of the digital signal Sd2 corresponding to the channel 150, including calculating the power of the digital signal Sd2 and/or measuring the amplitude of the digital signal Sd 2.
In operation S340, the channel evaluation circuit 280 generates the switching signal SE according to the characteristics of the channel 150, such as the power of the digital signal Sd2, and the predetermined thresholds TH1, TH2, and TH3, and transmits the switching signal SE to the selector 290. The selector 290 selects a corresponding path according to the switching signal to output the digital signal Sd2, the digital signal Sd3, the digital signal Sd4 or the digital signal Sd5 as the digital signal Sd 1.
In operation S350, the clock data recovery circuit 260 performs clock data recovery according to the digital signal Sd1 to generate a clock signal CLK, and transmits the clock signal CLK to the adc 230.
In operation S360, the amplifier 210 is enabled. The amplifier 210 amplifies the analog signal Sa1 to an analog signal Sa 2. In some embodiments, amplifier 210 is a variable gain amplifier.
In operation S370, digital signal processing is performed. The equalizer 220 equalizes the analog signal Sa2 to generate the analog signal Sa3, the clock data recovery circuit 260 performs clock data recovery according to the path selected in operation S340 to generate the clock signal CLK, the analog-to-digital converter 230 converts the analog signal Sa3 into the digital signal Sd2, and the selector 290 directly outputs the digital signal Sd2 into the digital signal Sd1 or outputs the digital signal Sd3 as the digital signal Sd1 according to the path selected in operation S340. In some embodiments, the equalizer 250 will equalize the digital signal Sd1 as the output signal Sout.
The description of method 300 above includes exemplary operations, but the operations of method 300 need not be performed in the order shown. It is within the spirit and scope of the embodiments of the present disclosure that the order of the operations of method 300 be altered or that the operations be performed concurrently, with portions being performed concurrently, or omitted, where appropriate.
Refer to fig. 4. Fig. 4 is a diagram illustrating a communication receiving device 400 according to another embodiment of the disclosure. The communication receiver 400 is an embodiment of the communication receiver 200 in the communication system 10. In some embodiments, the communication receiver 400 includes an amplifier 410, an equalizer 420, an analog-to-digital converter 430, a gain control circuit 440, an equalizer 450, a clock data recovery circuit 460, an equalizer 470, a channel estimation circuit 480, and a selector 490.
As shown in fig. 4, the amplifier 410 is coupled to the equalizer 420. The equalizer 420 is coupled to the adc 430. The adc 430 is coupled to the gain control circuit 440, the equalizer 470, the clock data recovery circuit 460 and the selector 490. The gain control circuit 440 is further coupled to the amplifier 410. The clock data recovery circuit 460 is further coupled to a node between the selector 490 and the equalizer 450. The channel estimation circuit 480 is coupled to the equalizer 450 and the selector 490.
In some embodiments, the amplifier 410, the equalizer 420, the adc 430, the gain control circuit 440, the equalizer 450, the clock data recovery circuit 460, the equalizer 470 and the selector 490 have functions similar to those of corresponding elements in fig. 2A, and thus are not described herein.
Compared to fig. 2A, in some embodiments, the channel evaluation circuit 480 is configured to determine whether the power of the output signal Sout is less than the predetermined threshold TH1, and generate the switching signal SE to be transmitted to the selector 490 according to the determination result. If the power of the output signal Sout is lower than the predetermined threshold TH1, the selector 490 outputs the digital signal Sd3 equalized by the equalizer 470 as the digital signal Sd1 according to the switching signal SE for clock data recovery. On the contrary, if the power of the output signal Sout is not lower than the predetermined threshold TH1, the selector 490 directly outputs the digital signal Sd2 as the digital signal Sd1 according to the switching signal SE for clock data recovery.
In some embodiments, the power of the output signal Sout is related to the channel 150 in the communication system 10. For example, when the channel 150 is a long channel, the loss of the channel 150 is large relative to the short channel, and therefore, a smaller power is obtained when measuring the power of the output signal Sout. On the contrary, if the channel 150 is a short channel, the loss of the channel 150 is smaller than that of the long channel, and thus a larger power is obtained when the power of the output signal Sout is measured. In other words, the predetermined threshold TH1 is set in relation to the loss of the channel 150.
In summary, the communication receiving apparatus 400 has a function of adjusting the signal transmission path according to the power of the output signal Sout, so as to improve the accuracy of clock recovery and the delay time of the whole system. Further, the communication receiver 400 has a function of adjusting the clock recovery path according to the attenuation of the channel 150.
Refer to fig. 5. Fig. 5 is a schematic diagram of a communication receiving device 500 according to another embodiment of the disclosure. The communication receiver 500 is an embodiment of the communication receiver 200 in the communication system 10. In some embodiments, the communication receiver 500 includes an amplifier 510, an equalizer 520, an adc 530, a gain control circuit 540, an equalizer 550, a clock data recovery circuit 560, an equalizer 570, a channel estimation circuit 580, and a selector 590.
As shown in fig. 5, the amplifier 510 is coupled to the equalizer 520. The equalizer 520 is coupled to the adc 530. The adc 530 is coupled to the gain control circuit 540, the equalizer 570, the clock data recovery circuit 560 and the selector 590. The gain control circuit 540 is further coupled to the amplifier 510. The clock data recovery circuit 560 is further coupled to a node between the channel estimation circuit 580 and the equalizer 550. The selector 590 is coupled to the channel evaluation circuit 580.
In some embodiments, the amplifier 510, the equalizer 520, the adc 530, the gain control circuit 540, the equalizer 550, the clock data recovery circuit 560, the equalizer 570 and the selector 590 have functions similar to those of the corresponding elements in fig. 2A, and thus are not described herein again.
Compared to fig. 2A, in some embodiments, the channel evaluation circuit 580 is configured to measure a time-domain response of the digital signal Sd 1' output by the selector 590 to the channel 150, and generate the switching signal SE to be fed back to the selector 590 according to the time-domain response. The channel estimation circuit 580 is used for dynamically adjusting the signal transmission path of the communication receiving apparatus 500. The selector 590 selects the digital signal Sd3 equalized by the equalizer 470 to be output as the digital signal Sd1 'for clock data recovery or directly output the digital signal Sd2 as the digital signal Sd 1' according to the switching signal SE. The digital signal Sd 1' is converted into a digital signal Sd1 by the channel evaluation circuit 580 for clock data recovery. In some embodiments, the channel evaluation circuit 580 is implemented in an adaptive (adaptive) circuit configuration.
In summary, the communication receiving apparatus 500 has a function of adjusting the signal transmission path according to the time domain response of the digital signal Sd 1' to the channel 150, so as to improve the accuracy of clock recovery and the delay time of the whole system.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the present invention.

Claims (16)

1. A communication receiver, comprising:
a clock data recovery circuit for generating a clock signal according to a first digital signal;
an analog-to-digital converter coupled to the clock data recovery circuit for converting a first analog signal according to the clock signal to generate a second digital signal;
a channel evaluation circuit for analyzing the second digital signal to output a switching signal;
a first equalizer coupled to the adc for equalizing the second digital signal to generate a third digital signal; and
and a selector, coupled among the first equalizer, the adc and the clock data recovery circuit, for outputting the second digital signal as the first digital signal or outputting the third digital signal as the first digital signal according to the switching signal.
2. The communication receiver of claim 1, wherein the first analog signal is associated with a second analog signal transmitted from a channel, and the channel evaluation circuit is further configured to analyze the second digital signal to evaluate a characteristic of the channel.
3. The communication receiver of claim 1, wherein the channel estimation circuit is configured to measure an amplitude of the second digital signal to output the switching signal.
4. The communication receiver of claim 1, wherein the channel estimation circuit is configured to measure a power of the second digital signal to output the switching signal.
5. The communication receiver of claim 4, wherein the selector is configured to directly output the second digital signal as the first digital signal when the power is not lower than a predetermined threshold.
6. The communication receiver of claim 4, wherein the selector is configured to transmit the third digital signal as the first digital signal when the power is below a predetermined threshold.
7. The communication receiver according to claim 1, further comprising:
an amplifier for amplifying a second analog signal to a third analog signal;
a second equalizer coupled between the amplifier and the ADC for equalizing the second analog signal to generate the first analog signal; and
and the gain control circuit is coupled with the analog-digital converter and the amplifier and used for adjusting a gain multiplying power of the amplifier according to the second digital signal.
8. The communication receiver according to claim 1, further comprising:
a third equalizer coupled to the selector for equalizing the first digital signal to generate an output signal, wherein the first equalizer and the third equalizer are feed-forward equalizers.
9. The communication receiver of claim 8 wherein a delay time for the first equalizer equalizing the second digital signal is less than a delay time for the third equalizer equalizing the first digital signal.
10. A clock data recovery method, comprising:
executing a clock data recovery on a first digital signal through a clock data recovery circuit and outputting a clock signal;
converting a first analog signal by a digital-to-analog converter according to the clock pulse signal to generate a second digital signal; and
directly outputting the second digital signal or outputting a third digital signal as the first digital signal according to the second digital signal, wherein the third digital signal is equalized from the second digital signal.
11. The clock data recovery method of claim 10, wherein the second digital signal is output or the third digital signal is output as the first digital signal according to an amplitude of the second digital signal.
12. The clock data recovery method according to claim 10, wherein the second digital signal is output or the third digital signal is output as the first digital signal according to a power of the second digital signal.
13. The clock data recovery method of claim 12, wherein outputting the second digital signal or the third digital signal as the first digital signal according to the power of the second digital signal comprises:
when the power is smaller than a preset threshold value, outputting the third digital signal as the first digital signal; and
when the power is not less than the predetermined threshold, the second digital signal is directly output as the first digital signal.
14. The clock data recovery method according to claim 13, further comprising: calculating the power of the second digital signal by a channel evaluation circuit;
generating a switching signal according to the power and the predetermined threshold; and
the second digital signal or the third digital signal is output as the first digital signal through a selector according to the switching signal.
15. The clock data recovery method according to claim 10, further comprising:
the first digital signal is equalized by a feed-forward equalizer to output an output signal.
16. The clock data recovery method according to claim 15, wherein the second digital signal is equalized into the third digital signal by an equalizer, and a delay time for equalizing the second digital signal by the equalizer is shorter than a delay time for equalizing the first digital signal by the feed-forward equalizer.
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Publication number Priority date Publication date Assignee Title
CN101320982A (en) * 2007-06-06 2008-12-10 智原科技股份有限公司 Time sequence reply parameter generation circuit and signal receiving circuit
US20160080178A1 (en) * 2014-09-17 2016-03-17 National Chiao Tung University Phase detecting device and clock data recovery circuit embedded with decision feedback equalizer
CN106685631A (en) * 2015-11-06 2017-05-17 创意电子股份有限公司 Clock data recovery device
TW201909570A (en) * 2017-07-25 2019-03-01 創意電子股份有限公司 Receiving device and signal conversion method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320982A (en) * 2007-06-06 2008-12-10 智原科技股份有限公司 Time sequence reply parameter generation circuit and signal receiving circuit
US20160080178A1 (en) * 2014-09-17 2016-03-17 National Chiao Tung University Phase detecting device and clock data recovery circuit embedded with decision feedback equalizer
CN106685631A (en) * 2015-11-06 2017-05-17 创意电子股份有限公司 Clock data recovery device
TW201909570A (en) * 2017-07-25 2019-03-01 創意電子股份有限公司 Receiving device and signal conversion method

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