CN112489594B

CN112489594B - Control method and control circuit of scanning signal control circuit and display device

Info

Publication number: CN112489594B
Application number: CN202011459945.1A
Authority: CN
Inventors: 李玥; 高娅娜; 周星耀; 张蒙蒙
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2022-12-20
Anticipated expiration: 2040-12-11
Also published as: CN112489594A

Abstract

The embodiment of the invention provides a control method of a scanning signal control circuit, a control circuit and a display device, and solves the technical problem that an embedded touch display screen in the prior art is low in touch performance. In the control method of the scan signal control circuit provided in the embodiment of the present invention, after a first clock signal and a second clock signal are input to a first shift register of a first shift register set, a first shift register of the first shift register set outputs a display scan signal, after a certain time interval (touch detection is performed during the time interval), a third clock signal and a fourth clock signal are respectively input to each second shift register of a second shift register set cascaded with the first shift register set, and the second shift register outputs the display scan signal, so that the display time and the touch time of the display panel can be separated, and no influence is generated on the other side no matter touch or display is performed, and the touch performance is improved.

Description

Control method and control circuit of scanning signal control circuit and display device

[ technical field ] A

The present invention relates to the field of display technologies, and in particular, to a control method and a control circuit for a scan signal control circuit, and a display device.

[ background of the invention ]

With the rapid development of display technologies, touch display screens have gradually spread throughout the lives of people. At present, the touch display screen can be divided into an external hanging type and an embedded type according to the setting position of a touch layer, wherein: the embedded touch display screen mainly comprises an On-cell structure, an In-cell structure and an OGS (One Glass Solution, single-chip touch panel) structure. An OLED (Organic Light-Emitting Diode) display device has the advantages of low driving voltage, high Light-Emitting brightness, high Light-Emitting efficiency, wide Light-Emitting viewing angle, high response speed, ultra-thin property, light weight, compatibility with a flexible substrate, and the like, and occupies an important position in the display field.

The embedded touch display screen is formed by integrating and manufacturing the touch screen and the display screen, the touch screen is embedded in the display screen, and electrodes of the touch screen comprise a plurality of touch driving lines TX arranged transversely and a plurality of touch induction lines RX arranged longitudinally.

In the process of touch point positioning detection, the touch driving lines TX are scanned line by line, signals on all the touch sensing lines RX are read when each touch driving line TX is scanned, and the intersection points of each touch driving line and each touch sensing line can be scanned by scanning the touch sensing lines RX column by column, so that the position of a touch point in the scanning process can be detected.

For display scanning and touch scanning, the display scanning is performed by scanning display scanning lines line by line, the touch driving lines TX are scanned line by line during touch scanning, and the display scanning stage and the touch scanning stage are separated and performed alternately, but because the distance between the touch electrode and the cathode of the light emitting unit is too close, interference to the touch signal is generated when the potential of the cathode is changed, thereby affecting the touch performance.

[ summary of the invention ]

In view of this, embodiments of the present invention provide a control method for a scan signal control circuit, a control circuit, and a display device, which solve the technical problems of the prior art that the display scan signal of an embedded touch display screen interferes with the touch signal and reduces the touch performance.

As an aspect of the present invention, an embodiment of the present invention provides a control method for a scan signal control circuit, where the scan signal control circuit includes: the shift register comprises an initial shift register, at least one first shift register group and at least one second shift register group, wherein the first shift register group comprises M cascaded first shift registers, the second shift register group comprises N cascaded second shift registers, and the initial shift register and a first stage of the first shift register group are cascaded or the initial shift register and a first stage of the second shift register group are cascaded;

the first shift register group and the second shift register group are alternately arranged at intervals and are sequentially cascaded end to end;

the first shift register is connected with the same first clock signal line and the same second clock signal line, and the second shift register is connected with the same third clock signal line and the same fourth clock signal line;

wherein the driving method comprises:

in a first time domain, inputting a first clock signal and a second clock signal corresponding to the first clock signal line and the second clock signal line into each first shift register in the first shift register group, wherein each first shift register outputs a display scanning signal, and the display scanning signal is used for performing display scanning driving on a pixel unit corresponding to the first shift register;

in a third time domain, inputting a third clock signal and a fourth clock signal corresponding to the third clock signal line and the fourth clock signal line into each second shift register of the second shift register group cascaded in the first shift register, respectively, wherein the second shift register outputs a display scanning signal, and the display scanning signal is used for performing display scanning driving on a pixel unit corresponding to the second shift register unit;

an interval period of the first time domain and the third time domain is a second time domain, and touch detection is performed in the second time domain.

As a second aspect of the present invention, an embodiment of the present invention provides a scan signal control circuit, including:

the shift register comprises an initial shift register, at least one first shift register group and at least one second shift register group;

wherein the first shift register group comprises M cascaded first shift registers, the second shift register group comprises N cascaded second shift registers, the initial shift register and the first shift register of the first shift register group are cascaded, or the initial shift register and the second shift register of the first shift register of the second shift register group are cascaded;

the first shift register is connected with the same first clock signal line and the same second clock signal line, and the second shift register is connected with the same third clock signal line and the same fourth clock signal line.

As a third aspect of the present invention, an embodiment of the present invention provides a display device, which includes the scan signal control circuit described above.

In the control method of the scan signal control circuit provided in the embodiment of the present invention, the shift registers are divided into two groups, the first clock signal and the second clock signal are input into each first shift register of the first register group, each first shift register in the first shift register group outputs the display scan signal, after a period of time (touch detection is performed during the interval time), the third clock signal and the fourth clock signal corresponding to the third clock signal line and the fourth clock signal line are respectively input into each second shift register in the second shift register group cascaded with the first shift register group, and the second shift register outputs the display scan signal, so that the display time and the touch time of the display panel can be separated, and no matter touch control or display occurs, the touch control signal cannot be interfered by the display signal, for example, the touch control signal cannot be interfered by the display signal, and the display signal cannot be interfered by the touch control signal, thereby improving the touch performance.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a circuit diagram of a scan signal control circuit according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a scan signal control circuit according to another embodiment of the present invention;

fig. 3 is a circuit diagram of a scan signal control circuit according to another embodiment of the present invention;

fig. 4 is a circuit diagram of a scan signal control circuit according to another embodiment of the present invention;

fig. 5 is a schematic flow chart illustrating a driving method of a scan signal control circuit according to an embodiment of the invention;

fig. 6 is a diagram illustrating pulse signals of a second frame start signal in the driving method illustrated in fig. 5; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of the scanning signal pulse signals output by the first shift register and the second shift register;

fig. 7 is a flowchart illustrating a driving method for driving the scan signal control circuit shown in fig. 4 according to an embodiment of the present invention;

fig. 8 is a diagram illustrating pulse signals of a second frame start signal in the driving method illustrated in fig. 7; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of the scanning signal pulse signals output by the first shift register and the second shift register;

FIG. 9 is a schematic flowchart illustrating another driving method for driving the scan signal control circuit shown in FIG. 4 according to another embodiment of the present invention;

fig. 10 is a diagram illustrating pulse signals of a second frame start signal in the driving method shown in fig. 9; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of the scanning signal pulse signals output by the first shift register and the second shift register;

fig. 11 is a schematic flowchart illustrating another driving method for driving the scan signal control circuit shown in fig. 4 according to another embodiment of the present invention;

fig. 12 is a diagram illustrating pulse signals of a second frame start signal in the driving method illustrated in fig. 11; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and another comparison graph of the scanning signal pulse signals output by the first shift register and the second shift register;

fig. 13 is a flowchart illustrating a driving method for driving the scan signal control circuit shown in fig. 1 according to an embodiment of the invention;

fig. 14 is a diagram illustrating pulse signals of a second frame start signal in the driving method shown in fig. 13; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of scanning signal pulse signals output by the first shift register and the second shift register;

fig. 15 is a schematic flowchart illustrating a driving method for driving the scan signal control circuit shown in fig. 3 according to an embodiment of the invention;

fig. 16 is a diagram illustrating pulse signals of a second frame start signal in the driving method illustrated in fig. 15; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of scanning signal pulse signals output by the first shift register and the second shift register;

FIG. 17 is a diagram showing a comparison of pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal according to an embodiment of the present invention;

FIG. 18 is a diagram showing a comparison of pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal according to another embodiment of the present invention;

fig. 19 is a comparison diagram of pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal according to another embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.

As an aspect of the present invention, an embodiment of the present invention provides a scan signal control circuit, and fig. 1 to 4 are schematic structural diagrams of the scan signal control circuit according to an embodiment of the present invention, and as shown in fig. 1 to 4, the scan signal control circuit includes: an initial shift register S1, at least one first shift register set 100, and at least one second shift register set 200;

the first shift register group 100 and the second shift register group 200 are alternately arranged at intervals and are sequentially cascaded end to end; in which, a set of second shift register sets 200 is disposed between two adjacent sets of first shift register sets 100, as shown in fig. 1. The first shift register group 100 and the second shift register group 200 are sequentially cascaded end to end, that is, when a group of second shift register groups 200 is disposed between two groups of first shift register groups 100, as shown in fig. 1, a last stage first shift register of the first shift register group 100 is connected to a first stage second shift register of the second shift register group 200, and a last stage second shift register of the second shift register group 200 is connected to a first stage first shift register of the second shift register group 100.

The first shift register group 100 includes M cascaded first shift registers, the second shift register group 200 includes N cascaded second shift registers, and the initial shift register and the first-stage first shift register of the first shift register group 100 are cascaded as shown in fig. 1, or the initial shift register and the first-stage second shift register of the second shift register group 200 are cascaded as shown in fig. 2; the number of the first shift registers included in the first shift register group 100 may be three, as shown in fig. 1 to 3, or may be other numbers; the number of the second shift registers included in the second shift register group 200 may be one, that is, the second shift register group 200 includes one second shift register, for example, as shown in fig. 1-2, and the number of the second shift registers included in the second shift register group 200 may also be two, that is, the second shift register group 200 includes two second shift registers, as shown in fig. 3. It should be understood that the present invention is not limited to the number of first shift registers included in the first shift register group 100, and the number of second shift registers included in the second shift register group 200.

The M first shift registers are connected to a same second clock signal line CK and a same second clock signal line XCK, and the N second shift registers are connected to a same third clock signal line CKT and a same fourth clock signal line XCKT.

Fig. 5 is a flowchart illustrating a driving method of a scan signal control circuit according to an embodiment of the invention, and fig. 6 is pulse signals of a first clock signal CK, a second clock signal CKT, a third clock signal XCK, and a fourth clock signal XCKT in the driving method illustrated in fig. 5; and a comparison graph of the display scanning signal pulse signal and the touch scanning signal pulse signal output by the first shift register and the second shift register; as shown in figure 5 and also in figure 6,

the driving method of the scanning signal control circuit comprises the following steps:

step S101: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a first clock signal line CK and a second clock signal line XCK into each first shift register in a first shift register group respectively, wherein each first shift register outputs a display scanning signal respectively, and the display scanning signal is used for performing display scanning driving on a pixel unit corresponding to the first shift register; after each first shift register respectively outputs a display scan signal, the display scan signal scans a row of pixel units corresponding to the first shift register, so that the pixel units emit light, that is, in a first time domain T1, a row of pixel units in the display panel respectively corresponding to each first shift register in the first shift register group 100 displays light. For example, as shown in fig. 1, in a first time domain T1, three first shift registers S2-S4 in one first shift register group 100 respectively output scanning signals, and the scanning signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light.

Step S102: in the second time domain T2, touch detection is performed, i.e., a touch signal is transmitted to at least some of the touch electrodes in the 1 st to 4 th rows to turn on the touch driver.

Step S103: in a third time domain T3, a third clock signal CKT and a fourth clock signal XCKT corresponding to a third clock signal line CKT and a fourth clock signal line XCKT are respectively input to each second shift register in a second shift register group 200 cascaded with the first shift register group 100, the second shift register outputs a display scanning signal, and the display scanning signal is used for performing display scanning driving on a pixel unit corresponding to the second shift register unit; that is, after each second shift register outputs a display scan signal, the display scan signal scans a row of pixel units corresponding to the second shift register, so that the pixel units emit light, that is, in the third time zone T3, a row of pixel units in the display panel corresponding to each second shift register in the second shift register group 200 respectively emit light. By analogy, the display time and the touch time of the display panel can be separated, and no matter touch or display is performed, the display time and the touch time cannot influence each other, for example, the touch signal cannot be interfered by the display signal, and the display signal cannot be interfered by the touch signal, so that the touch performance is improved.

In an embodiment of the present invention, as shown in fig. 7 and 8, before step S101, the method for driving the scan signal control circuit further includes:

step S1010: inputting a second frame start signal STV2 output from the second frame start signal line STV2 into the initial shift register S1;

between step S102 and step S103, the driving method of the scan signal control circuit further includes:

step S1030: a fourth time domain is further included during the interval between the second time domain and the third time domain, and the first frame start signal STV1 output from the first frame start signal line STV1 is input to the first-stage second shift register in the second shift register group 200 in the fourth time domain T4; wherein, the start point of the fourth time domain is the same as the end point of the second time domain, and step S1030 is: and triggering the first-stage second shift register of the second shift register group by adopting a first frame starting signal STV1.

Meanwhile, in the fourth time domain T4, a third effective clock signal (i.e. a signal capable of closing the switching transistor, for example, when the switching transistor is a PMOS transistor, the third effective clock signal is at a low level, as shown in fig. 8) output from the third clock signal line CKT is input into the second shift register, a fourth clock signal XCKT output from the fourth clock signal line XCKT is input into the second shift register, the polarity of the third effective clock signal XCKT is the same as that of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from that of the first frame start signal STV 1;

at this time, step S103 specifically includes:

step S1031: in a third time domain T3, inputting a third effective clock signal output from a third clock signal line CKT into a second shift register, inputting a fourth clock signal XCKT output from a fourth clock signal line XCKT into the second shift register, wherein the polarity of the third effective clock signal is the same as that of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from that of the first frame start signal STV 1; at this time, the second shift register outputs a scan signal, and the pixel units of one row corresponding to the second shift register emit light.

In the driving method provided in the embodiment of the present invention, in a fourth time domain T4 between the second time domain T2 and the third time domain T3, the first frame start signal STV1 is used to trigger the first-stage second shift register of the second shift register group, so that the first-stage second shift register of the second shift register group outputs the display scanning control signal in the third time domain T3.

To better describe the driving method of the scan signal control circuit provided by the embodiment of the present invention, the following describes in detail the driving method of the scan signal control circuit shown in fig. 4 by taking the scan signal control circuit shown in fig. 4 as an example:

as shown in fig. 4, the scan signal control circuit includes: an initial shift register S1, at least one first shift register set 100, and at least one second shift register set 200; the first shift register group 100 and the second shift register group 200 are alternately arranged at intervals and are sequentially cascaded end to end; that is, a group of second shift register sets 200 is disposed between any two adjacent groups of first shift register sets 100, the last first shift register of the first group of first shift register sets 100 is connected to the first second shift register of the second group of second shift register sets 200, and the last second shift register of the second group of second shift register sets 200 is connected to the first shift register of the second group of first shift register sets 100. The first shift register group 100 includes three cascaded first shift registers, the second shift register group 200 includes a cascaded second shift register, the initial shift register is cascaded with the first-stage first shift register of the first shift register group; in a first shift register group 100, except for the 1 st first shift register, the inputs of the other two first shift registers are connected to the output terminal of the first shift register of the previous stage adjacent to the first shift register. The output end of the initial shift register S1 is connected to the input end of the first stage shift register (i.e., S2) in the first shift register group 100 adjacent to the initial shift register S1;

the three first shift registers in the first shift register group 100 are all connected to the second clock signal line CK and the second clock signal line XCK, and the second clock signal line CK and the second clock signal line XCK provide the first clock signal CK and the second clock signal XCK for the three first shift registers in the first shift register group 100;

a third clock signal line CKT and a fourth clock signal line XCKT, wherein a second shift register in the second shift register set 200 is connected to the third clock signal line CKT and the fourth clock signal line XCKT, and the third clock signal line CKT and the fourth clock signal line XCKT provide a third clock signal CKT and a fourth clock signal XCKT for a first shift register in the second shift register set 200;

a second frame start signal line STV2, the second frame start signal line STV2 providing a second frame start STV2 to the initial shift register S1;

at least one first frame start signal line STV1, each first frame start signal line STV1 being connected to the input end of the second shift register in each second shift register group 200 in a one-to-one correspondence; the first frame start signal line STV1 supplies the first frame start signal STV1 to the second shift register corresponding thereto.

Fig. 7 is a schematic flow chart of a driving method of the scan signal control circuit shown in fig. 4, and fig. 8 is a pulse signal of a second frame start signal and a first frame start signal in the driving method shown in fig. 7; pulse signals of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; and a comparison graph of scanning signal pulse signals output by the first shift register and the second shift register; as shown in figure 7 and also in figure 8,

step S101: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a second clock signal line CK and a second clock signal line XCK into each first shift register in the first shift register group 100, where each first shift register outputs a display scan signal for performing display scan driving on a pixel unit corresponding to the first shift register; that is, in the first time domain T1, the three first shift registers S2-S4 in one first shift register group 100 respectively output the scan signals, and the scan signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light, as shown in fig. 8.

Step S102: in the second time domain T2, touch detection is performed, i.e., a touch signal is transmitted to the touch electrodes in the 1 st row to the 4 th row to turn on the touch driver.

Step S1030: inputting the first frame start signal STV1 into the second shift register S5 in the fourth time domain T4; the starting point of the fourth time domain T4 is the same as the ending point of the second time domain T2, and the ending point of the fourth time domain T4 is the same as the starting point of the third time domain T3.

Meanwhile, in the fourth time domain T4, a third effective clock signal (i.e. a signal capable of closing the switching transistor, for example, when the switching transistor is a PMOS transistor, the third effective clock signal is at a low level, as shown in fig. 8) output from the third clock signal line CKT is input into the second shift register S5, and a fourth clock signal XCKT output from the fourth clock signal line XCKT is input into the second shift register S5, where the polarity of the third effective clock signal is the same as that of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from that of the first frame start signal STV 1;

step S1031: in the third time domain T3, inputting a third effective clock signal output from the third clock signal line CKT into the second shift register S5, and inputting a fourth clock signal XCKT output from the fourth clock signal line XCKT into the second shift register S5, wherein the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV 1; at this time, the second shift register S5 outputs a scan signal, and the pixel units of one row corresponding to the second shift register S5 emit light.

As can be seen from fig. 8, after the scan signals are outputted from the three first shift registers (S2-S4) in the first shift register set 100, the second shift register S5 outputs the scan signals after the interval between the second time domain T2 and the third time domain T3, and the second time domain T2 is the touch scan time, i.e. after the pixels in the S1-S4 rows emit light, the pixels in the S5 row emit light after the time T2+ T4, i.e. during the time T4, neither touch scan nor display scan is performed. That is, although the display scanning and the touch scanning interval output can be realized by adopting the driving method shown in fig. 7, the output of the display scanning control signal from the first stage shift register S5 in the second shift register group 200 is delayed by a fourth time period T4, that is, after the touch detection is performed in the second time period T2, the display scanning control signal cannot be immediately output from the first stage shift register S5 in the second shift register group 200.

Therefore, in another embodiment of the present invention, as shown in fig. 9 and 10, the triggering of the first stage second shift register of the second shift register group by using the first frame start signal STV1 occurs in the last time domain of the second time domain T2, that is, the second time domain T2 includes a second sub-time domain T21, and the ending time point of the second sub-time domain T21 is equal to the ending time point of the second time domain T2. That is, step S103 specifically includes:

step S1030: inputting a first frame start signal STV1 to a first-stage second shift register of a second shift register group in a second sub-time domain T21;

in the second sub-time domain T21, the third valid clock signal XCK output from the third clock signal line XCK is input to the second shift register, the fourth clock signal XCKT output from the fourth clock signal line XCKT is input to the second shift register, the polarity of the third valid clock signal is the same as the polarity of the first frame start signal STV1, the polarity of the fourth clock signal is different from the polarity of the first frame start signal STV1, and the end point of the second sub-time domain T21 is the same as the end point of the second sub-time domain T2.

In the driving method in the embodiment of the present invention, the time for triggering the first-stage second shift register of the second shift register group by using the first frame start signal STV1 is set in the second time domain T2, so that, after the touch detection is performed in the second time domain T2, the first-stage shift register in the second shift register group 200 can immediately output the display scan control signal in the third time domain T3, that is, there is no time interval between the third time domain T3 and the second time domain T2.

To better describe the driving method of the scan signal control circuit provided by the embodiment of the present invention, the scan signal control circuit shown in fig. 4 is taken as an example, and another driving method of the scan signal control circuit shown in fig. 4 is described in detail, that is, another driving method of the scan signal control circuit shown in fig. 4 is described in detail below, that is, the scan signal control circuit is taken as an example

Fig. 9 shows another driving method of the scan signal control circuit shown in fig. 4, and fig. 10 shows a pulse diagram of driving each clock signal line of the scan signal control circuit and a scan signal pulse diagram by the driving method shown in fig. 9, wherein the driving method of the scan signal control circuit comprises the following steps:

step S101: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a second clock signal line CK and a second clock signal line XCK into each first shift register in the first shift register group 100, where each first shift register outputs a display scan signal for performing display scan driving on a pixel unit corresponding to the first shift register; that is, in the first time domain T1, the three first shift registers S2-S4 in one first shift register group 100 respectively output the scan signals, and the scan signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light, as shown in fig. 10.

Step S1030: inputting the first frame start signal STV1 to the first-stage second shift register S5 of the second shift register group 200 in the second sub-time domain T21;

meanwhile, in the second sub-time domain T21, the third effective clock signal CKT output from the third clock signal line CKT is input into the second shift register S5, the fourth clock signal XCKT output from the fourth clock signal line XCKT is input into the second shift register S5, the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV1, and the termination point of the second sub-time domain T21 is the same as the termination point of the second sub-time domain T2. That is, the first frame start signal STV1 and the third valid clock signal are input to the second shift register S5 during the last period of time in the second time domain T2.

Step S1031: in a third time domain T3, inputting a third effective clock signal CKT output from a third clock signal line CKT into the second shift register S5, and inputting a fourth clock signal XCKT output from a fourth clock signal line XCKT into the second shift register S5, wherein the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV 1; at this time, the second shift register S5 outputs a scan signal, and the pixel units of one row corresponding to the second shift register S5 emit light.

In the driving method of the present embodiment, the first frame start signal STV1 and the third effective clock signal are input to the second shift register S5 in the last time of the touch stage T2, so that after the touch scanning is completed on the touch electrodes in the rows S1 to S4, the pixel units in the row S5 can be made to emit light immediately, that is, the display stage and the touch stage can be seamlessly connected.

In another embodiment of the present application, no time interval between the third time domain T3 and the second time domain T2 can be implemented by another driving method, that is, triggering the first-stage second shift register of the second shift register group by using the first frame start signal STV1 occurs in the same time domain as the effective scan signal output by the first shift register cascaded one stage on the second shift register, as shown in fig. 11, triggering the first-stage second shift register of the second shift register group occurs in the same time domain as the effective scan signal output by the first shift register cascaded one stage on the second shift register, that is, step S1030 specifically includes:

inputting a first frame start signal STV1 to a first-stage second shift register of the second shift register group 200 in the same time domain as a valid scan signal output from a first shift register cascade-connected to a previous stage of the second shift register; meanwhile, a third effective clock signal output from the third clock signal line XCK is input to the second shift register, and a fourth clock signal output from the fourth clock signal line XCKT is input to the second shift register, where the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, and the polarity of the fourth clock signal is different from the polarity of the first frame start signal STV1.

In the driving method in the embodiment of the present invention, the time for triggering the first-stage second shift register of the second shift register set by using the first frame start signal STV1 is set in the first time domain T1, so that after the touch detection is performed in the second time domain T2, the first-stage shift register in the second shift register set 200 can immediately output the display scanning control signal in the third time domain T3, that is, there is no time interval between the third time domain T3 and the second time domain T2.

To better describe the driving method of the scan signal control circuit according to the embodiment of the present invention, the following takes the scan signal control circuit shown in fig. 4 as an example to describe in detail another driving method of the scan signal control circuit shown in fig. 4, that is, fig. 11 shows another driving method of the scan signal control circuit shown in fig. 4, fig. 12 shows a pulse diagram and a scan signal pulse diagram of each clock signal line of the scan signal control circuit driven by the driving method shown in fig. 11, and as shown in fig. 11 and fig. 12, the driving method of the scan signal control circuit includes the following steps:

step S101: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a second clock signal line CK and a second clock signal line XCK into each first shift register in the first shift register group 100, where each first shift register outputs a display scanning signal, and the display scanning signal is used to perform display scanning driving on a pixel unit corresponding to the first shift register; that is, in the first time domain T1, the three first shift registers S2-S4 in one first shift register group 100 respectively output the scan signals, and the scan signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light.

Step S1030: the first frame start signal STV1 is input to the first-stage second shift register of the second shift register group 200 in a time domain (e.g., T14 in fig. 12) in which the valid scan signal is output in the same time domain as the valid scan signal is output from the first shift register S4 cascaded one stage above the second shift register S5. Meanwhile, a third effective clock signal output by a third clock signal line CKT is input into a second shift register, a fourth clock signal XCKT output by a fourth clock signal line XCKT is input into the second shift register, the polarity of the third effective clock signal is the same as that of the first frame start signal, and the polarity of the fourth clock signal XCKT is different from that of the first frame start signal;

step S102: in the second time domain T2, touch detection is performed, i.e., a touch signal is transmitted to the touch electrodes in the 1 st row to the 4 th row, so as to turn on the touch driver.

Step S1031: in a third time domain T3, inputting a third effective clock signal output from a third clock signal line CKT into a second shift register, and inputting a fourth clock signal XCKT output from a fourth clock signal line XCKT into the second shift register, wherein the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV 1; at this time, the second shift register S5 outputs a scan signal, and the pixel units of one row corresponding to the second shift register S5 emit light.

In the driving method in this embodiment, in the same time domain as the effective scanning signal output by the first shift register cascaded to the previous stage of the second shift register, that is, in the time domain of the scanning signal output by S4, the first frame start signal STV1 is input into the second shift register cascaded to the next stage of the first shift register, so that the display stage and the touch stage can be seamlessly connected.

In another embodiment of the present invention, when the first frame start signal STV1 is input to the second shift register cascaded with the next stage of the first shift register within the same time domain as the valid scan signal output from the first shift register cascaded with the next stage of the second shift register, the first frame start signal STV1 may be directly the valid scan signal output from the first shift register cascaded with the next stage of the second shift register. For example, as shown in fig. 1, the scan signal control circuit is a circuit shown in fig. 1, the input signal of S5 is an effective scan signal output by S4, at this time, in the scan signal control circuit, the input end of the first-stage second shift register in the second shift register group 200 is connected to the output end of the last-stage first shift register in the first-stage first shift register group 100 cascaded with the second shift register group 200, that is, the input end of S5 is connected to the output end of S4, that is, the effective scan signal output by S4 is multiplexed by the first frame start signal STV1 of S5. Fig. 14 shows a pulse pattern of each clock signal line and a scanning signal pulse pattern corresponding to a driving method for driving the scanning signal control circuit. Therefore, the display stage and the touch stage can be seamlessly connected. In addition, when the first-stage shift register in each second shift register group 200 needs to additionally input the first frame start signal STV1, the first-stage shift register in the second shift register group 200 needs to be connected with one first frame start signal line STV1, and how many second shift register groups 200 are in one display panel, that is, how many first frame start signal lines STV1 are needed, which makes the scanning signal control circuit complicated, and the number of signal lines is large, and the occupied space is large, so that it is difficult to implement a narrow frame.

In order to better describe the driving method of the scan signal control circuit of the present invention, two specific scan signal control circuits are taken as examples to describe the driving method of the scan signal control circuit in detail.

In an embodiment of the present invention, as shown in fig. 1, the scan signal control circuit includes:

an initial shift register S1, at least one first shift register group 100 and at least one second shift register group 200; the first shift register group 100 and the second shift register group 200 are alternately arranged at intervals and are sequentially cascaded end to end; that is, a group of second shift register groups 200 is disposed between any two adjacent groups of first shift register groups 100, the last stage of first shift register of the first shift register group 100 is connected to the first stage of second shift register of the group of second shift register groups 200, and the last stage of second shift register of the group of second shift register groups 200 is connected to the first stage of first shift register of the second shift register group 100. The first shift register group 100 includes three cascaded first shift registers, the second shift register group 200 includes a cascaded second shift register, the initial shift register is cascaded with the first-stage first shift register of the first shift register group; in a first shift register group 100, except for the 1 st first shift register, the inputs of the other two first shift registers are connected to the output terminal of the first shift register of the previous stage adjacent to the first shift register. The output end of the initial shift register S1 is connected to the input end of the first stage shift register (i.e., S2) in the first shift register group 100 adjacent to the initial shift register S1; the output end of the first shift register of the last stage in the first shift register group is connected to the input end of the second shift register, that is, the effective scanning signal of the output of the first shift register (e.g., S4) of the last stage in the first shift register group is the first frame start signal STV1 of the second shift register (e.g., S5).

a third clock signal line CKT and a fourth clock signal line XCKT, wherein a second shift register of the second shift register set 200 is connected to the third clock signal line CKT and the fourth clock signal line XCKT, and the third clock signal line CKT and the fourth clock signal line XCKT provide a third clock signal CKT and a fourth clock signal XCKT for a first shift register of the second shift register set 200;

a second frame start signal line STV2, the second frame start signal line STV2 providing a third frame start signal STV2 to the initial shift register S1;

fig. 13 shows a driving method of the scan signal control circuit shown in fig. 1, fig. 14 shows a pulse diagram and a scan signal pulse diagram of each clock signal line of the scan signal control circuit driven by the driving method shown in fig. 13, and as shown in fig. 13 and 14, the driving method of the scan signal control circuit includes the steps of:

as shown in fig. 13, the driving method of the scan signal control circuit shown in fig. 1 includes the steps of:

step S200: inputting a second frame start signal STV2 output from the second frame start signal line STV2 into the initial shift register S1;

step S201: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a second clock signal line CK and a second clock signal line XCK into each first shift register in the first shift register group 100, where each first shift register outputs a display scanning signal, and the display scanning signal is used to perform display scanning driving on a pixel unit corresponding to the first shift register; that is, in the first time domain T1, the three first shift registers S2-S4 in one first shift register group 100 respectively output the scan signals, and the scan signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light, as shown in fig. 13.

Step S202: in the same time domain as the effective scanning signal output by the first shift register S4 cascaded in the last stage of the second shift register, the effective scanning signal output by the first shift register S4 is input into the second shift register S5, wherein the effective scanning signal output by the first shift register S4 is the first frame start signal of the second shift register S5. Meanwhile, a third effective clock signal output by a third clock signal line CKT is input into the second shift register S5, a fourth clock signal XCKT output by a fourth clock signal line XCKT is input into the second shift register S5, the polarity of the third effective clock signal is the same as that of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from that of the first frame start signal STV 1;

step S203: in the second time domain T2, touch detection is performed, i.e., a touch signal is transmitted to the touch electrodes in the 1 st row to the 4 th row, so as to turn on the touch driver.

Step S204: in the third time domain T3, the third effective clock signal output from the third clock signal line CKT is input into the second shift register, the fourth clock signal XCKT output from the fourth clock signal line XCKT is input into the second shift register, the polarity of the third effective clock signal is the same as the polarity of the first frame start signal line STV1 (i.e. the same as the polarity of the effective scan signal output from S4), and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal line STV1 (i.e. the different from the polarity of the effective scan signal output from S4); at this time, the second shift register S5 outputs a scan signal, and the pixel cells of one row corresponding to the second shift register S5 emit light.

Optionally, the periods of the first clock signal CK, the second clock signal XCK, the third clock signal CKT, and the fourth clock signal XCKT may be as follows:

in which the first effective clock signal output from the first clock signal line CK and the second effective clock signal output from the second clock signal line XCK appear alternately, as shown in fig. 14.

Alternatively, when the first shift register group 100 in the scan control circuit includes a second shift register, as shown in fig. 1, and the first frame start signal STV1 can directly output the effective scan signal for the first shift register cascaded with the second shift register at the previous stage, the period of the waveform of the first clock signal CK output by the first clock signal line CK is T ₁ The second clock signal XCK output from the second clock signal line XCK has a waveform period T ₂ Wherein T is ₁ Is equal to T ₂ And the phase of the second effective clock signal is different from the phase of the first effective clock signal by T ₁ /2。

The third clock signal CKT output from the third clock signal line CKT has a waveform period T ₃ Fourth clock output from fourth clock signal line XCKTThe clock signal XCKT has a waveform with a period T ₄ Wherein, T ₃ Is equal to T ₄ 。

Alternatively, as shown in fig. 14, the ratio of the period of the waveform of the third clock signal CKT output from the third clock signal line CKT to the period of the waveform of the first clock signal CK output from the first clock signal line CK is equal to (M + 1). For example, when three first shift registers are included in the first shift register group 100 (i.e., when M is equal to 3), the ratio of the period of the waveform of the third clock signal CKT output from the third clock signal line CKT to the period of the waveform of the first clock signal CK output from the first clock signal line CK is equal to 4, i.e., T is equal to _ckt ＝(3+1)T _ck 。

Similarly, as shown in fig. 14, the period of the first clock signal CK is T ₁ The second clock signal XCK output from the second clock signal line XCK has a waveform period T ₂ Wherein T is ₁ Is equal to T ₂ . The third clock signal CKT output from the third clock signal line CKT has a waveform with a period T ₃ The waveform of the fourth clock signal XCKT output from the fourth clock signal line XCKT has a period T ₄ Wherein, T ₃ Is equal to T ₄ . Then, when three first shift registers are included in the first shift register group 100 (i.e., when M is equal to 3), the ratio of the period of the waveform of the fourth clock signal XCKT output from the fourth clock signal line XCKT to the period of the waveform of the first clock signal XCK output from the second clock signal line XCK is equal to 4, i.e., T _Xckt ＝(3+1)T _Xck 。

In another embodiment of the present invention, as shown in fig. 3, the scan signal control circuit includes: an initial shift register S1, at least one first shift register set 100, and at least one second shift register set 200; the first shift register group 100 and the second shift register group 200 are alternately arranged at intervals and are sequentially cascaded end to end; that is, a group of second shift register groups 200 is disposed between any two adjacent groups of first shift register groups 100, the last stage of first shift register of the first shift register group 100 is connected to the first stage of second shift register of the group of second shift register groups 200, and the last stage of second shift register of the group of second shift register groups 200 is connected to the first stage of first shift register of the second shift register group 100.

a second frame start signal line STV2, the second frame start signal line STV2 providing a third frame start signal to the initial shift register S1;

the first shift register group 100 includes three cascaded first shift registers, where an initial shift register S1 is cascaded with a first-stage first shift register of the first shift register group 100; in a first shift register group 100, except for the 1 st first shift register, the inputs of the other two first shift registers are connected to the output terminal of the first shift register of the previous stage adjacent to the first shift register. The output end of the initial shift register S1 is connected to the input end of the first stage shift register (i.e., S2) in the first shift register group 100 adjacent to the initial shift register S1;

the second shift register group 200 includes two cascaded second shift registers; the input of the first-stage second shift register in the second shift register group 200 is connected to the output of the last and first shift register in the first shift register group 100 that is previous to the second shift register group, that is, the input of S5 is connected to the output of S4, and the input of each second shift register in the second shift register group 200 is the output of the previous-stage second shift register, that is, the input of S6 is connected to the output of S5.

Fig. 15 is a schematic flowchart of a driving method for driving the scan control circuit shown in fig. 3, and fig. 16 is a pulse diagram and a scan signal pulse diagram of each clock signal line of the scan signal control circuit driven by the driving method shown in fig. 15; as shown in fig. 15 and 16, the driving method includes:

step S300: inputting a second frame start signal STV2 output from the second frame start signal line STV2 into the initial shift register S1;

step S301: in a first time domain T1, inputting a first clock signal CK and a second clock signal XCK corresponding to a first clock signal line CK and a second clock signal line XCK into each first shift register in a first shift register group 100, where each first shift register outputs a display scan signal for performing display scan driving on a pixel unit corresponding to the first shift register; that is, in the first time domain T1, the three first shift registers S2-S4 in one first shift register group 100 respectively output the scan signals, and the scan signals output by S2-S4 are respectively transmitted to the pixel units in the 2 nd row to the 4 th row, so that the pixel units in the 2 nd row to the 4 th row emit light.

Step S302: in the time domain of the effective scanning signal output by S4, the effective scanning signal output by S4 is input to the input terminal of S5, meanwhile, the third effective clock signal output by the third clock signal line CKT is input to the first-stage second shift register S5, the fourth clock signal XCKT output by the fourth clock signal line XCKT is input to the first-stage second shift register S5, the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1 (i.e., the effective scanning signal output by S4), and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV1 (i.e., the effective scanning signal output by S4);

step S303: in the second time domain T2, touch detection is performed, i.e., a touch signal is transmitted to the touch electrodes in the 1 st row to the 4 th row to turn on the touch driver.

Step S304: inputting a fourth effective clock signal output from a fourth clock signal line XCKT to the first-stage second shift register S5 in the first and third sub-time domains T31; inputting a third clock signal CKT output from a third clock signal line CKT into the first-stage second shift register S5, wherein the polarity of the fourth active clock signal is the same as that of the first frame start signal STV1 (i.e., the active scan signal output from S4), the polarity of the third clock signal CKT is different from that of the first frame start signal STV1 (i.e., the active scan signal output from S4), and the start time point of the first third sub-time domain T31 is equal to the end time point of the second time domain T2; the first-stage second shift register S5 outputs a scan signal, and a row of pixel units corresponding to the second shift register emit light.

Step S305: in the second and third sub-time domains T32, the fourth clock signal XCKT output from the fourth clock signal line XCKT is input to the second stage of the second shift register S6; the third valid clock signal output from the third clock signal line CKT is input to the second stage second shift register S6, wherein the polarity of the fourth clock signal XCKT is opposite to that of the first frame start signal (i.e., the valid scan signal output from S4), the polarity of the third valid clock signal is the same as that of the first frame start signal (i.e., the valid scan signal output from S4), and the ending time point of the second third sub-time domain T32 is equal to that of the third time domain T3. The second-stage second shift register S6 outputs a scan signal, and a row of pixel units corresponding to the second-stage second shift register S6 emits light.

Fig. 15 and 16 show the driving method when the second shift register group of the scan control circuit includes two second shift registers, in a time domain where the last first shift register in the first shift register group outputs an effective scan signal, the third effective clock signal output by the third clock signal line CKT is input into the first second shift register, the fourth clock signal output by the fourth clock signal line XCKT is input into the first second shift register, the polarity of the third effective clock signal is the same as that of the frame start signal, the polarity of the fourth clock signal XCKT is different from that of the first frame start signal STV1 (i.e., the effective scan signal output by S4), so that the display scan and the touch scan are seamlessly connected.

It should be understood that the first frame start signal STV1 may be input to the first-stage second shift register of the second shift register group 200, the third valid clock signal output from the third clock signal line CKT may be input to the first-stage second shift register, the fourth clock signal XCKT output from the fourth clock signal line XCKT may be input to the first-stage second shift register, the polarity of the third valid clock signal may be the same as that of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT may be different from that of the first frame start signal STV1 in a time period between the second time domain T2 and the third time domain T3.

In the last time period of the second time domain T2, the first frame start signal STV1 may be input to the first-stage second shift register of the second shift register set 200, the third effective clock signal output by the third clock signal line CKT may be input to the first-stage second shift register, and the fourth clock signal XCKT output by the fourth clock signal line XCKT may be input to the first-stage second shift register, where the polarity of the third effective clock signal is the same as the polarity of the first frame start signal STV1, and the polarity of the fourth clock signal XCKT is different from the polarity of the first frame start signal STV1.

In another embodiment of the present invention, a time domain in which each of the first shift register and the second shift register respectively outputs the touch scan signal is a second time domain T2; the polarity of the first clock signal CK output from the second clock signal line CK in the same time domain as the second time domain T2 can be the following three conditions:

(1) As shown in fig. 17, the second clock signal line CK continuously outputs the first clock signal CK having the same polarity as that of the first active clock signal; for example, the low level is continuously output.

(2) As shown in fig. 18, the second clock signal line CK outputs a first clock signal having the same polarity as that of the first effective clock signal for a part of the time, and outputs a first clock signal having a different polarity from that of the first effective clock signal for a part of the time; for example, the time-low level and the time-high level may be periodically distributed, or may not be periodically distributed, as shown in fig. 18.

(3) As shown in fig. 19, the second clock signal line CK continuously outputs the first clock signal CK having a polarity different from that of the first active clock signal, for example, a high level.

Similarly, in the same time domain as the second sub-time domain, the polarity of the second clock signal XCK output by the second clock signal line XCK may be as follows:

(1) As shown in fig. 17, the second clock signal line XCK continuously outputs the second clock signal XCK having the same polarity as the second active clock signal; for example, the low level is continuously output.

(2) As shown in fig. 18, the second clock signal line XCK outputs the second clock signal XCK having the same polarity as the second valid clock signal for a partial time, and outputs the second clock signal XCK having a different polarity from the second valid clock signal for a partial time; for example, the time-low level and the time-high level may be periodically distributed, or may not be periodically distributed, as shown in fig. 18.

(3) As shown in fig. 19, the second clock signal line XCK continuously outputs the second clock signal XCK having a polarity different from that of the second active clock signal, for example, a high level.

As a third aspect of the present invention, an embodiment of the present invention provides a display device including the scan signal control circuit described above. The specific structure and driving method of the scan signal control circuit are the same as those of the above embodiments, and are not described herein again. The display device may be any electronic device with a display function, such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, an electronic paper book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A control method of a scan signal control circuit, the scan signal control circuit comprising: the shift register comprises an initial shift register, at least one first shift register group and at least one second shift register group, wherein the first shift register group comprises M cascaded first shift registers, the second shift register group comprises one cascaded second shift register, and the initial shift register and the first shift register of the first shift register group are cascaded or the initial shift register and the second shift register of the first shift register of the second shift register group are cascaded;

the control method is characterized by comprising the following steps:

in a third time domain, inputting a third clock signal and a fourth clock signal corresponding to the third clock signal line and the fourth clock signal line into each second shift register of the second shift register group cascaded in the first shift register, respectively, wherein the second shift register outputs a display scanning signal, the display scanning signal is used for performing display scanning driving on a pixel unit corresponding to the second shift register unit, and an effective touch detection signal is arranged between a third effective clock signal and a fourth effective clock signal corresponding to the second shift register group;

an interval period of the first time domain and the third time domain is a second time domain, and touch detection is executed in the second time domain;

the control method further comprises the following steps:

inputting a first frame start signal into a second shift register cascaded with a next stage of the first shift register in the same time domain as an effective scanning signal output by the first shift register cascaded with a previous stage of the second shift register;

the control method further comprises the following steps: inputting a third effective clock signal output by a third clock signal line into the second shift register and inputting a fourth clock signal output by a fourth clock signal line into the second shift register in the same time domain as an effective scanning signal output by the first shift register cascaded at the previous stage of the second shift register, wherein the polarity of the third effective clock signal is the same as that of the first frame start signal, and the polarity of the fourth clock signal is different from that of the first frame start signal;

wherein, in a third time domain, inputting a third clock signal and a fourth clock signal corresponding to the third clock signal line and the fourth clock signal line into each of the second shift registers of the second shift register group cascaded with the first shift register, respectively, includes:

inputting a fourth effective clock signal output by the fourth clock signal line into the second shift register in the third time domain; inputting a third clock signal output by the third clock signal line into the second shift register, wherein the polarity of the fourth effective clock signal is the same as that of the first frame start signal, and the polarity of the third clock signal is different from that of the first frame start signal;

the period of the waveform of the first clock signal output by the first clock signal line is T ₁ The second clock signal line outputs a second clock signal having a waveform with a period T ₂ Wherein T is ₁ Is equal to T ₂ And second isThe phase of the effective clock signal differs from the phase of the first effective clock signal by a phase difference T ₁ /2；

The period of the waveform of the third clock signal output by the third clock signal line is T ₃ The period of the waveform of the fourth clock signal outputted from the fourth clock signal line is T ₄ Wherein, T ₃ Is equal to T ₄ ；

A ratio of a period of a third clock signal waveform output from the third clock signal line to a period of a first clock signal waveform output from the first clock signal line is equal to (M + 1).

2. The control method according to claim 1, characterized by further comprising a fourth time domain during an interval between the second time domain and the third time domain, the control method further comprising:

in the fourth time domain, inputting a first frame start signal into a first-stage second shift register in the second shift register group;

in the fourth time domain, inputting a third effective clock signal output by the third clock signal line into the second shift register, and inputting a fourth clock signal output by the fourth clock signal line into the second shift register, wherein the polarity of the third effective clock signal is the same as that of the first frame start signal, and the polarity of the fourth clock signal is different from that of the first frame start signal;

wherein an end point of the second time domain is the same as a start point of the fourth time domain.

3. The control method according to claim 1, wherein the second time domain includes a second sub-time domain, and a termination point of the second sub-time domain is the same as a termination point of the second time domain, the control method further comprising:

in the second sub-time domain, inputting a first frame starting signal into a first-stage second shift register in the second shift register group;

and in the second sub-time domain, inputting a third effective clock signal output by the third clock signal line into the second shift register, and inputting a fourth clock signal output by the fourth clock signal line into the second shift register, wherein the polarity of the third effective clock signal is the same as that of the first frame start signal, and the polarity of the fourth clock signal is different from that of the first frame start signal.

4. The control method according to claim 1, wherein the first frame start signal outputs an active scanning signal for the first shift register cascaded with a stage above the second shift register.

5. The control method according to claim 1,

wherein the first effective clock signal output by the first clock signal line and the second effective clock signal output by the second clock signal line appear alternately.

6. The control method according to claim 1, wherein the second shift register group includes a first-stage second shift register and a second-stage shift register; the first shift register and the second shift register are cascaded, and the first shift register and the second shift register are cascaded in the first shift register group cascaded next to the second shift register group;

wherein the control method further comprises:

outputting effective scanning signals in the same time domain with the first shift register cascaded at the previous stage of the first stage of the second shift register; inputting a third effective clock signal output by the third clock signal line into the first-stage second shift register; inputting a fourth clock signal output by the fourth clock signal line into the first-stage second shift register, wherein the third effective clock signal has the same polarity as the first frame start signal, and the fourth clock signal has a different polarity from the first frame start signal;

wherein, in a third time domain, inputting a third clock signal and a fourth clock signal corresponding to the third clock signal line and the fourth clock signal line into each of the second shift registers of the second shift register group cascaded with the first shift register group, respectively, comprises: inputting a fourth effective clock signal output by the fourth clock signal line into the first-stage second shift register in a first third sub-time domain; inputting a third clock signal output by the third clock signal line into the first-stage second shift register, wherein the polarity of the fourth effective clock signal is the same as that of the first frame start signal, the polarity of the third clock signal is different from that of the first frame start signal, and the start time point of the first third sub-event domain is equal to the end time point of the second time domain;

inputting a fourth clock signal output from the fourth clock signal line into the second stage second shift register in a second one of the third sub-time domains; inputting a third effective clock signal output by the third clock signal line into the second-stage second shift register, wherein the polarity of the fourth clock signal is opposite to that of the first frame start signal, the polarity of the third effective clock signal is the same as that of the first frame start signal, the ending time point of the second third sub-time domain is equal to that of the third time domain, and the starting time point in the second third sub-time domain is equal to that of the first third sub-time domain.

7. The control method according to claim 1,

within the same time domain as the second time domain,

the first clock signal line continuously outputs a first clock signal having a polarity identical to a polarity of the first effective clock signal; or

The first clock signal line outputs a first clock signal with the same polarity as the first effective clock signal within a partial time, and outputs a first clock signal with the polarity different from that of the first effective clock signal within the partial time; or

The first clock signal line continuously outputs a first clock signal having a polarity different from a polarity of the first active clock signal.

8. The control method according to claim 1, characterized in that, in the same time domain as the second time domain,

the second clock signal line continuously outputs a second clock signal having the same polarity as the second active clock signal; or

The second clock signal line outputs a second clock signal with the same polarity as the second effective clock signal in a part of time, and outputs a second clock signal with the polarity different from that of the second effective clock signal in a part of time; or

The second clock signal line continuously outputs a second clock signal having a polarity different from a polarity of the second active clock signal.

9. A scan signal control circuit for performing the control method of any one of claims 1 to 8, comprising:

an initial shift register, at least one first shift register set and at least one second shift register set;

10. The scan signal control circuit according to claim 9, wherein an output terminal of a last stage first shift register in a first shift register cell group located at a stage higher than the second shift register group is connected to an input terminal of a first stage second shift register in the second shift register group.

11. The scan signal control circuit according to claim 9, further comprising:

at least one first frame start signal line, wherein each first frame start signal line is respectively connected with the input end of the first-stage second shift register in each second shift register group in a one-to-one correspondence manner;

the first frame start signal line provides a first frame start signal for the corresponding second shift register.

12. The scan signal control circuit according to claim 9, wherein, in one of the first shift register groups, except for the 1 st first shift register, inputs of the remaining M-1 first shift registers are connected to an output terminal of a first shift register of a previous stage adjacent to the first shift register.

13. A display device comprising the scan signal control circuit according to any one of claims 9 to 12.