CN112487744B - Connection avoidance method and device for logic element and storage medium - Google Patents
Connection avoidance method and device for logic element and storage medium Download PDFInfo
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Abstract
The invention relates to a connection avoidance method, a device and a storage medium of logic elements, wherein the method comprises the steps of determining all connection lines between at least two logic elements, wherein each connection line is used for connecting an output pin of one logic element with an input pin of the other logic element; determining the line type of the connecting line according to the relative positions of the input pin and the output pin; and carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided, avoidance of each connecting line in graphic programming is realized, layout of the connecting lines is optimized, graphic readability is enhanced, and the use efficiency of engineering personnel is improved.
Description
Technical Field
The present invention relates to the field of automation control technologies, and in particular, to a method and apparatus for avoiding connection between logic elements, and a storage medium.
Background
In general, in configuration software in the field of automation control, a graphic corresponding to a programmable logic controller may be connected, so as to implement configuration of the programmable logic controller.
In one implementation, the connection relationship of each pin in each programmable logic controller may be configured in configuration software. Further, when one pin has a connection relationship with another pin, a connection line may be used to connect the two pins.
Furthermore, the configuration software can use a connection algorithm to realize the function of automatic connection.
At present, the link algorithm mainly comprises Dijkstra algorithm, manhattan algorithm, sugiyama algorithm and the like. The Dijkstra algorithm and the Manhattan algorithm are suitable for path searching optimization, such as searching the shortest path, i.e. searching the shortest connecting line. The Sugiyama algorithm is complex and is commonly used for star network topologies.
However, these algorithms only solve the problem of the shortest path, and cannot realize mutual avoidance between the connecting lines, which is easy to cause the problem of complex wiring structure due to repeated overlapping of the connecting lines, and unfavorable for engineering personnel to view, so that the requirements of graphic configuration in the field of automatic control cannot be met.
Disclosure of Invention
The invention aims to provide a connection avoidance method, a device and a storage medium for logic elements, which realize avoidance of each connection line in graphic programming, optimize layout of the connection lines, enhance graphic readability and improve the use efficiency of engineering personnel.
In order to achieve the above object, a first aspect of the present application provides a connection avoidance method of a logic element, including:
determining all connecting lines between at least two logic elements, wherein each connecting line is used for connecting an output pin of one logic element with an input pin of the other logic element;
determining the line type of the connecting line according to the relative positions of the input pin and the output pin;
and carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided mutually.
Further, the line type includes: a first line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is at the lower right of the output pin, determining the connecting line to be a first line type;
two inflection points are arranged in the connecting line of the first line type, and the connecting line is a lower bending line which is sequentially connected with the output pin, the two inflection points and the input pin.
Further, the avoidance processing is performed on the same line type connection lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connection lines are avoided mutually, and the method includes:
When one logic element is provided with a plurality of first linear connecting lines for output, a first avoiding area is arranged at a position close to the logic element;
and setting an inflection point of each first linear connecting line in the first avoidance area so that each first linear connecting line is avoided in the first avoidance area.
Further, the line type includes: a second line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is at the upper right of the output pin, determining the connecting line to be a second line type;
two inflection points are arranged in the connecting line of the second line type, and the connecting line is an upper bending line which is sequentially connected with the output pin, the two inflection points and the input pin.
Further, the avoidance processing is performed on the same line type connection lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connection lines are avoided mutually, and the method includes:
when one logic element is provided with a plurality of connecting line inputs of a second line type, a second avoidance area is arranged at a position close to the logic element;
And setting an inflection point of each second linear connecting line in the second avoidance area so that each second linear connecting line is avoided in the second avoidance area.
Further, the line type includes: a third line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is arranged on the left side of the output pin and the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction is larger than zero, determining that the connecting line is of a third line type;
the connecting line of the third line type is provided with four inflection points, and the connecting line is an S-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin.
Further, the logic element includes a first logic element and a second logic element; the output pin of the first logic element and the input pin of the second logic element are connected with a plurality of connecting lines of a third line type;
the avoidance processing is performed on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided, and the method comprises the following steps:
A third avoidance area is arranged at a position close to the first logic element;
a fourth avoidance region is arranged in a gap between the first logic element and the second logic element in the vertical direction;
a fifth avoidance region is arranged at a position close to the second logic element;
the third avoidance area is provided with a first inflection point, the fourth avoidance area is provided with a second inflection point and a third inflection point, and the fifth avoidance area is provided with a fourth inflection point, so that each connecting line of the third line type is mutually avoided in the third avoidance area, the fourth avoidance area and the fifth avoidance area.
Further, the line type includes: a fourth line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is at the left side of the output pin and the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction is smaller than or equal to zero, determining that the connecting line is of a fourth line type;
the connecting line of the fourth line type is provided with four inflection points, and the connecting line is a U-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin.
Further, the logic elements include a third logic element and a fourth logic element; the output pin of the third logic element and the input pin of the fourth logic element are connected with a plurality of fourth linear connecting lines;
the avoidance processing is performed on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided, and the method comprises the following steps:
a sixth avoidance region is arranged at a position close to the third logic element;
a seventh avoiding area is arranged below the third logic element and the fourth logic element;
setting an eighth avoidance region at a position close to the fourth logic element;
the sixth avoidance region is provided with a first inflection point, the seventh avoidance region is provided with a second inflection point and a third inflection point, and the eighth avoidance region is provided with a fourth inflection point, so that each connecting line of the fourth line type is mutually avoided in the sixth avoidance region, the seventh avoidance region and the eighth avoidance region.
Further, the method further comprises the following steps:
when a plurality of connecting lines with different lines are staggered up and down on the same side of one logic element, the connecting lines staggered up and down are avoided, so that all the connecting lines are avoided.
Further, the avoidance processing is performed on the connection lines staggered up and down, so that all the connection lines avoid each other, including:
when the connecting lines staggered up and down are output from the logic element, the connecting lines bent up are avoided from connecting lines bent down;
when the connecting wires staggered up and down are input into the logic element, the connecting wires bent down avoid the connecting wires bent up.
In order to achieve the above object, a second aspect of the present application provides a connection avoidance device for a logic element, including:
the connecting wire determining module is used for determining all connecting wires between at least two logic elements, and each connecting wire is used for connecting an output pin of one logic element with an input pin of the other logic element;
the line type determining module is used for determining the line type of the connecting line according to the relative positions of the input pin and the output pin;
the avoidance module is used for carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided.
In order to achieve the above object, a third aspect of the present application provides a connection avoidance device for a logic element, including: a memory and one or more processors;
the memory is used for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the method for wire avoidance of a logic element as described in any one of the first aspects.
To achieve the above object, a fourth aspect of the present application provides a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a connection avoidance method of a logic element according to any one of the first aspects.
In view of the above, according to the technical solution provided in the present application, by determining all connection lines between at least two logic elements, each connection line is used to connect an output pin of one logic element with an input pin of another logic element; determining the line type of the connecting line according to the relative positions of the input pin and the output pin; the avoidance processing is carried out on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided mutually, the problems of complex layout and poor readability in graphic programming caused by mutual overlapping of the connecting lines between the logic elements are solved, avoidance of each connecting line in graphic programming is realized, the layout of the connecting lines is optimized, the graphic readability is enhanced, and the use efficiency of engineering staff is improved.
Drawings
Fig. 1 is a flowchart of a connection avoidance method of a logic element provided in embodiment 1 of the present invention;
FIG. 2 is a schematic diagram illustrating a logic device link avoidance according to embodiment 1 of the present invention;
fig. 3 is a schematic structural diagram of a connection avoidance device for a logic element according to embodiment 3 of the present invention;
fig. 4 is a schematic structural diagram of a connection avoidance device for a logic element according to embodiment 4 of the present invention.
Detailed Description
The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
Example 1
The method can be executed by a connection avoidance device of the logic element, and the connection avoidance device of the logic element can be realized in a software and/or hardware mode and is integrated in connection avoidance equipment capable of being used for the logic element. Optionally, the connection avoidance device of the logic element includes, but is not limited to, a terminal such as a computer, a server, and the like. In this embodiment, a computer is taken as an example to describe the connection avoidance device of the logic element in detail, and further, configuration software may be installed in the computer, which may be used to configure the logic element, and specifically, may be used to execute the connection avoidance method of the logic element provided in this embodiment.
Fig. 1 is a flowchart of a connection avoidance method of a logic element provided in embodiment 1 of the present invention, and fig. 2 is a schematic diagram of connection avoidance of a logic element provided in embodiment 1 of the present invention, and referring to fig. 1, the method may include the following steps:
s110, determining all connecting lines between at least two logic elements, wherein each connecting line is used for connecting an output pin of one logic element with an input pin of the other logic element.
In this embodiment, the logic element may be an electronic element in the field of automatic control, such as a programmable logic controller or other controller. In configuration software, graphics may be used to represent the logic element. The logic element is provided with input pins and output pins, and the pins can be similarly drawn out in the above-described figures. Illustratively, referring to FIG. 2, B1, B2, B3, and B4 are each a corresponding pattern of logic elements.
Further, in this embodiment, the input pins and the output pins may be respectively distributed on one side of the logic element, as referring to fig. 2, the input pins are located on the left side of the logic element, and the output pins are located on the right side of the logic element.
In one embodiment, the graphics corresponding to the logic elements may be dragged into the configuration interface of the configuration software during configuration. Furthermore, the connection relationship between pins (including input pins and output pins) in each logic element in the configuration interface can also be set in the configuration software. All the two pins with connection relation can be determined that a connecting wire exists to connect the two pins.
S120, determining the line type of the connecting line according to the relative positions of the input pin and the output pin.
In this embodiment, the line is in the shape of a connecting line. In general, inflection points are arranged in the connecting lines, and the shape of the connecting lines can be determined according to the number and the positions of the inflection points. Further, in the present embodiment, the line type may include a first line type, a second line type, a third line type, a fourth line type, and the like.
Wherein, two inflection points are arranged in the connecting line of the first line type, and the connecting line is a lower bending line sequentially connecting the output pin, the two inflection points and the input pin, such as connecting lines E1, E2, E3, E4 and E5 in FIG. 2.
Wherein, two inflection points are arranged in the connecting line of the second line type, and the connecting line is an upper bending line which is sequentially connected with the output pin, the two inflection points and the input pin, such as connecting lines E6, E7, E8, E9 and E14 in FIG. 2.
The third line type connecting line is provided with four inflection points, and the connecting line is an S-shaped bending line sequentially connecting the output pin, the four inflection points and the input pin, such as connecting lines E10, E11, E12 and E13 in fig. 2.
The fourth linear connecting line is provided with four inflection points, and the connecting line is a U-shaped bending line sequentially connecting the output pin, the four inflection points and the input pin, such as connecting line E16 in fig. 2.
In this embodiment, the relative positions of the input pins and the output pins indicate the positional relationship of the input pins on the left, right, upper left, upper right, lower left, and lower right of the output pins.
Further, in the present embodiment, the line type of the connection line may be set to one of the first line type, the second line type, the third line type, and the fourth line type according to the relative position between the input pin and the output pin.
S130, carrying out avoidance processing on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided.
In this embodiment, the preset avoidance mode may be set to at least include:
mode 1: corresponding to the first line type, the lower bending line is avoided at one side of the logic element where the output pin is located;
mode 2: corresponding to the second line type, the upper bending line is avoided at one side of the logic element where the input pin is located.
Mode 3: corresponding to the third line type, the S-shaped bending line is avoided at the middle position of the two logic elements;
mode 4: corresponding to the fourth line type, the 'U' -shaped bending line is avoided below the two logic elements.
Further, on the basis of the above 4 avoidance modes, the avoidance modes may further include:
mode 5: when a logic element has a plurality of connecting lines with different lines on the same side and is staggered up and down, the connecting lines staggered up and down are avoided, as in the case of the connecting line E13 on the same side of the logic element B3 in FIG. 2, the connecting line E15 is avoided; the connection line E14 on the same side in the logic element B4 bypasses the connection lines E10, E11 and E12.
Specifically, in this embodiment, the above 5 avoidance modes may be implemented for the connection line by setting the position of the inflection point on the connection line.
In the technical solution provided in this embodiment, by determining all connection lines between at least two logic elements, each connection line is used to connect an output pin of one logic element with an input pin of another logic element; determining the line type of the connecting line according to the relative positions of the input pin and the output pin; the avoidance processing is carried out on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided mutually, the problems of complex layout and poor readability in graphic programming caused by mutual overlapping of the connecting lines between the logic elements are solved, avoidance of each connecting line in graphic programming is realized, the layout of the connecting lines is optimized, the graphic readability is enhanced, and the use efficiency of engineering staff is improved.
Based on the above technical solution, in this embodiment, detailed description will be made on how to determine the position of the inflection point on the connection line to achieve mutual avoidance of the connection line.
In this embodiment, the inflection point sequence p= [ P ] on the connection may be set 0 ，…，p i ]＝[(x 0 ，y 0 )，…，(x i ，y i )]Wherein p is i For the ith inflection point on the connecting line, its coordinates can be expressed as (x i ，y i )。
In addition, the pins of the logic element may also be connected to include blocks V, such as "OUT_VAR1", "OUT_VAR2", "OUT_VAR3", "INT_VAR1", "INT_VAR2", and "INT_VAR4" in FIG. 2. Further, the width and height of each block V are h v And w v The plurality of blocks are included with a maximum width and height.
In this embodiment, each connection line is used to connect an output pin of a Source logic device (Source) with an input pin of another Target logic device (Target).
Wherein the position of the output pins can be expressed as (x) p1 ，y p1 ) The position of the output pins can be expressed as (x) p2 ，y p2 )。
In this embodiment, the position of the logic element may be represented using the coordinates of the upper left corner of the graph to which the logic element corresponds. The location of a Source logic element (Source) may be represented as (x) b1 ，y b1 ) The location of the Target logic element (Target) may be expressed as (x) b2 ，y b2 )。
Further, the width and height of the Source logic element (Source) may be expressed as (w b1 ，h b1 ) The width and height of the Target logic element (Target) can be expressed as (w) b2 ，h b2 )。
For clarity, in this embodiment, different avoidance modes corresponding to different line types will be described in a classification manner.
1. First line type
In this embodiment, when the input pin is at the lower right of the output pin, the connection line is determined to be the first line type.
In a specific embodiment, when x p2 >xp 1 And y is p2 >y p1 When the line type of the connection line may be determined as the first line type, such as the connection lines E3, E4, and E15 in fig. 2, etc.
Further, referring to fig. 2, when a logic element has a plurality of connection line outputs of a first line type, a first avoidance region 21 is provided at a position close to the logic element; the inflection point of each first line-type connecting line is provided in the first avoidance region 21 so that each first line-type connecting line is avoided from each other in the first avoidance region 21.
In a specific embodiment, when x p2 >xp1 and y p2 >y p1 In this case, the first relief region 21 may be disposed near the Source logic element (Source), and the inflection point P of each first linear connection line may be disposed in the first relief region 21 0 And P 1 。
Further, if the block V is not included below the first line type connecting lines, such as the connecting lines E3 and E4 in fig. 2, and all the connecting lines below the right side thereof are counted as n, the inflection point position can be calculated using the following formula:
p 0 ＝(x p1 +n*gap+gap，y p1 )
p 1 ＝(x p1 +n*gap+gap，y p2 )
In this embodiment, the configuration interface may be rasterized, and the side length of each small lattice is gap, and the sides of the small lattices may be used to draw the connection lines. In this embodiment, a gap equal to 5 is taken as an example.
Further, if the containing block V exists below the connection line of the first line type, such as connection lines E1 and E2 in fig. 2, all the connection lines below the right side are counted as n, and the width of the containing block V below the right side is W v The location of its inflection point can be calculated using the following formula:
p 0 ＝(x p1 +Max(n*gap，w v )+gap，y p1 )
p 1 ＝(x p1 +Max(n*gap，w v )+gap，y p2 )
in one embodiment, taking the connection line E2 as an example, the input pin (x p2 ，y p2 ) Is (185, 55), the output pin (x) p1 ，y p1 ) Is (50, 20), then x is satisfied p2 >xp1 and y p2 >y p1 I.e. the input pins (x p2 ，y p2 ) At the output pin (x) p1 ，y p1 ) The line type of the connection line E2 may be set to the first line type.
Furthermore, the output pin (x) in connection E2 in logic element B1 can be counted p1 ，y p1 ) All down link lines (including themselves) under count 3, including width w of block "OUT_VAR2 v =40, then x 0 =50+max (3*5, 40) =90. Further, the inflection point sequence of the connecting line E2 was determined to be [ (90, 20), (90, 55)]。
2. Second line type
In this embodiment, when the input pin is at the upper right of the output pin, the connection line is determined to be the second line type.
In a specific embodiment, when x p2 >x p1 And y is p1 >y p2 When the line type of the connection line may be determined as a second line type, such as the connection lines E6, E7, E8, E9, etc. in fig. 2.
Further, when a logic element has a plurality of connection line inputs of a second line type, a second avoidance region 22 is provided at a position close to the logic element; the inflection point of each of the second line-type connecting lines is provided at the second avoidance region 22 such that each of the second line-type connecting lines is avoided from each other in the second avoidance region 22.
In a specific embodiment, when x p2 >xp1 and y p1 >y p2 In this case, the second avoidance region 22 may be disposed at a position close to the Target logic element (Target), and the inflection point P of each of the second linear connection lines may be disposed in the second avoidance region 22 0 And P 1 。
Further, if the block V is not included below the second line type connecting lines, such as connecting lines E8 and E9 in fig. 2, and all the downward connecting lines below the left side thereof are counted as n, the position of the inflection point thereof can be calculated using the following formula:
p 0 ＝(x p2 –n*gap–gap，y p2 )
p 1 ＝(x p2 –n*gap–gap，y p1 )
further, if the containing block V exists below the second linear connecting line, such as connecting lines E6, E7 and E14 in fig. 2, all the downward connecting lines below the left side thereof are counted as n, and the width of the containing block V below the left side is W v The location of its inflection point can be calculated using the following formula:
p 0 ＝(x p2 –Max(n*gap，w v )–gap，y p2 )
p 1 ＝(x p2 –Max(n*gap，w v )–gap，y p1 )
3. third and fourth lines
In this embodiment, when the input pin is on the left side of the output pin, if the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction is greater than zero, the connection line is determined to be a third line type; if the gap between the logic element of the input pin and the logic element of the output pin in the vertical direction is smaller than or equal to zero, the connecting line is determined to be a fourth line type.
In this embodiment, the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction may be denoted by Δy, Δy=y b2 –y b1 +h b1 。
3.1 for the third type
When x is p1 >x p2 And Deltay>At 0, the line type of the connection line may be determined as a third line type.
For example, when x p1 >x p2 And y is p2 >y p1 And Deltay>At 0, the line type of the connection line may be determined as a third line type, such as connection lines E10, E11, and E12 in fig. 2, and the like.
As another example, when x p1 >x p2 And y is p1 >y p2 And Deltay>At 0, the line type of the connection line may be determined as a third line type, such as the connection line E13 in fig. 2.
Further, in the present embodiment, it is assumed that the logic element includes a first logic element and a second logic element, wherein a plurality of connection lines of a third line type are connected to an output pin of the first logic element and an input pin of the second logic element. I.e. the first logic element is the Source logic element (Source) and the second logic element is the Target logic element (Target).
Further, referring to fig. 2, a third avoidance region 23 may be provided at a position close to the first logic element; a fourth relief area 24 is provided in the gap between the first logic element and the second logic element in the vertical direction; a fifth avoidance area 25 is provided at a position close to the second logic element; a first inflection point P is arranged in the third avoidance region 23 0 The fourth avoidance region 24 is provided with a second inflection point P 1 And a third inflection point P 2 A fourth inflection point P is provided in the fifth avoidance region 25 3 So that each third line of connection lines is located in the third avoiding region 23 the fourth avoidance region 24 and the fifth avoidance region 25 avoid each other.
3.1.1 for x p1 >x p2 And y is p2 >y p1 Is the case of (2)
Like the connection lines E10, E11 and E12 in FIG. 2, the connection line count n of all the third lines between the first logic element (Source) and the second logic element (Target) can be determined 0 . An index i of the currently calculated connection line is determined, and if the currently calculated connection line is E12, the index i is 3. Further, count n for all down-connection lines to the right of the first logic element (Source) below the currently calculated connection line location 1 The method comprises the steps of carrying out a first treatment on the surface of the Counting n for all upward wires to the left of the second logic element (Target) below the currently calculated wire location 2 The method comprises the steps of carrying out a first treatment on the surface of the Taking the gap Δy=y in the vertical direction between the first logic element (Source) and the second logic element (Target) b2 –y b1 +h b1 。
If Δy >0, the location of the inflection point can be calculated using the following formula:
p 0 ＝(x p1 +Max(n 1 *gap+gap，w v1 )，y p1 )
p 1 ＝(x p1 +Max(n 1 *gap+gap，w v1 )，y b1 +(Δy+((n 0 /2)–i)*gap)/2)
p 2 ＝(x p2 –Max(n 2 *gap–gap，w v2 )，y b1 +(Δy+((n 0 /2)–i)*gap)/2)
p 3 ＝(x p2 –Max(n 2 *gap–gap，w v2 )，y p2 )
3.1.2 for x p1 >x p2 And y is p1 >y p2 Is the case of (2)
As with the connection line E13 in FIG. 2, the connection line count n of all the third lines between the first logic element (Source) and the second logic element (Target) can be determined 0 . Determining a current meterThe index i of the calculated connection line, e.g. the currently calculated connection line is E13, is 1. Further, count n for all up-link lines to the right of the first logic element (Source) above the currently calculated link line location 1 The method comprises the steps of carrying out a first treatment on the surface of the Counting n for all down-links to the left of the second logic element (Target) below the currently calculated location of the link 2 The method comprises the steps of carrying out a first treatment on the surface of the Taking the gap Δy=y in the vertical direction between the first logic element (Source) and the second logic element (Target) b2 –y b1 +h b1 。
If Δy >0, the location of the inflection point can be calculated using the following formula:
p 0 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，y p1 )
p 1 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，y b2 –(Δy+((n 0 /2)–i)*gap)/2)
p 2 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，y b2 –(Δy+((n 0 /2)–i)*gap)/2)
p 3 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，y p2 )
3.2 for the fourth wire type
When x is p1 >x p2 And Deltay<At 0, the line type of the connection line may be determined as a fourth line type.
For example, when x p1 >x p2 And y is p2 >y p1 And Deltay<At 0, the line type of the connection line may be determined as a fourth line type, such as the connection line E16 in fig. 2.
As another example, when x p1 >x p2 And y is p1 >y p2 And Deltay<At 0, the line type of the connection line may be determined as a fourth line type.
Further, in the present embodiment, it is assumed that the logic elements include a third logic element and a fourth logic element; the output pin of the third logic element and the input pin of the fourth logic element are connected with a plurality of fourth linear connecting lines. I.e. the third logic element is the Source logic element (Source) and the fourth logic element is the Target logic element (Target).
Further, referring to fig. 2, a sixth avoidance region 26 is provided at a position near the third logic element; a seventh avoidance region 27 is provided below the third logic element and the fourth logic element; an eighth avoidance region 28 is provided adjacent the fourth logic element; a first inflection point P is provided in the sixth avoidance region 26 0 The seventh avoidance region 27 is provided with a second inflection point P 1 And a third inflection point P 2 A fourth inflection point P is provided in the eighth avoidance region 28 3 So that each fourth line of connection line is located in the sixth relief area 26 the seventh avoidance region 27 and the eighth avoidance region 28 avoid each other.
3.2.1 for x p1 >x p2 And y is p2 >y p1 Is the case of (2)
The connection line count n of all third lines between the third logic element (Source) and the fourth logic element (Target) can be determined 0 . An index i of the currently calculated connection line is determined, and if the currently calculated connection line is E12, the index i is 3. Further, count n for all down-connection lines to the right of the third logic element (Source) below the currently calculated connection line location 1 The method comprises the steps of carrying out a first treatment on the surface of the Counting n for all upward wires to the left of the fourth logic element (Target) below the currently calculated wire location 2 The method comprises the steps of carrying out a first treatment on the surface of the Taking the gap Δy=y in the vertical direction between the third logic element (Source) and the fourth logic element (Target) b2 –y b1 +h b1 。
If Δy <0, such as the connecting line E16 in fig. 2, the location of the inflection point can be calculated using the following formula:
p 0 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，y p1 )
p 1 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，Max(y b1 +h b1 ，y b2 +h b2 )+i*gap)
p 2 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，Max(y b1 +h b1 ，y b2 +h b2 )+i*gap)
p 3 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，y p2 )
3.1.2 for x p1 >x p2 And y is p1 >y p2 Is the case of (2)
The connection line count n of all third lines between the third logic element (Source) and the fourth logic element (Target) can be determined 0 . An index i of the currently calculated connection line is determined, and if the currently calculated connection line is E13, the index i is 1. Further, count n for all up-link lines to the right of the third logic element (Source) above the currently calculated link line location 1 The method comprises the steps of carrying out a first treatment on the surface of the Counting n for all down-links to the left of the fourth logic element (Target) below the currently calculated location of the link 2 The method comprises the steps of carrying out a first treatment on the surface of the Taking the gap Δy=y in the vertical direction between the third logic element (Source) and the fourth logic element (Target) b2 –y b1 +h b1 。
If Δy <0, the location of the inflection point can be calculated using the following formula:
p 0 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，y p1 )
p 1 ＝(x p1 +Max(n 1 *gap，w v1 )+gap，Max(y b1 +h b1 ，y b2 +h b2 )+i*gap)
p 2 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，Max(y b1 +h b1 ，y b2 +h b2 )+i*gap)
p 3 ＝(x p2 –Max(n 2 *gap，w v2 )–gap，y p2 )
on the basis of the above embodiment, when a logic element has a plurality of connection lines of different lines on the same side and are staggered up and down, the connection lines staggered up and down are avoided, such as the connection line E13 on the same side of the logic element B3 in fig. 2 is avoided from the connection line E15; the connection line E14 on the same side in the logic element B4 bypasses the connection lines E10, E11 and E12.
Specifically, for the up-down staggering of the connection lines on the same side of the logic element, two cases can be divided into two cases, namely, adjacent inflection points p i Is corrected for the x-coordinate of (c). Wherein, the adjacent inflection point pi is calculated by the inflection point determining mode corresponding to each line type.
In the present embodiment, it is assumed that the maximum shift of all the connection lines of a logic element on one side in the x-axis direction is Δx=max (n i *gap+gap，w vi ) Where i represents the index of each connection line.
First case: when the connecting lines staggered up and down are output from the logic element, the connecting lines bent up are avoided from connecting lines bent down;
specifically, there are multiple connection lines of different line types on one side of the output pin in the logic element, and all the connection lines satisfy y p2 <y p1 As shown on the output pin side of the logic element B3, all the connection lines from below have inflection points p i The maximum offset of all connecting lines from above should be added in the x-axis direction, expressed as:
x＝p ix +Δx
for example, the connection line E13 from below in the logic element B3 should avoid the connection line E15 from above, and as can be seen from fig. 2, Δx=gap, the connection line E13 passes through the first inflection point p from the logic element B3 0 Should be avoided to the right by a gap distance.
Second case: when the connecting wires staggered up and down are input into the logic element, the connecting wires bent down avoid the connecting wires bent up.
Specifically, there are multiple connection lines of different line types on one side of the input pin in the logic element, and all the connection lines meet y p2 >y p1 As shown on one side of the input pin of logic element B4, all of the connection lines going from above have inflection points P i The maximum offset of all connecting lines coming from below should be subtracted in the x-axis direction:
x＝p ix -Δx
for example, the upper connection line E14 of the logic element B4 should avoid the lower connection lines E10, E11, and E12, and as can be seen from fig. 2, Δx is equal to the offset of the connection line E10, and the last inflection point before the connection line E14 is input to the logic element B4 should avoid the connection line E10 to the left by a gap distance.
Example 2
The utility model provides a device is dodged to connecting of logic element, this device is dodged to connecting of logic element can be realized through the mode of software and/or hardware to the integration can carry out in the device is dodged to connecting of logic element. Optionally, the connection avoidance device of the logic element includes, but is not limited to, a terminal such as a computer, a server, and the like. In this embodiment, a detailed description will be given by taking a connection avoidance device of the logic element as an example of a server.
Fig. 3 is a schematic structural diagram of a connection avoidance device for a logic element according to embodiment 2 of the present invention, and referring to fig. 3, the device may include the following structure: a link determination module 310, a line determination module 32, and a avoidance module 330.
The connection line determining module 310 is configured to determine all connection lines between at least two logic elements, where each connection line is configured to connect an output pin of one logic element with an input pin of another logic element.
The line type determining module 320 is configured to determine a line type of the connection line according to the relative positions of the input pin and the output pin.
The avoidance module 330 is configured to perform avoidance processing on the same line type connection lines located on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connection lines are avoided.
In the technical solution provided in this embodiment, by determining all connection lines between at least two logic elements, each connection line is used to connect an output pin of one logic element with an input pin of another logic element; determining the line type of the connecting line according to the relative positions of the input pin and the output pin; the avoidance processing is carried out on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided mutually, the problems of complex layout and poor readability in graphic programming caused by mutual overlapping of the connecting lines between the logic elements are solved, avoidance of each connecting line in graphic programming is realized, the layout of the connecting lines is optimized, the graphic readability is enhanced, and the use efficiency of engineering staff is improved.
On the basis of the technical scheme, the line type comprises: a first line type;
the line type determining module 320 includes:
a first line type determining unit configured to determine that the connection line is a first line type when the input pin is at the lower right of the output pin; two inflection points are arranged in the connecting line of the first line type, and the connecting line is a lower bending line which is sequentially connected with the output pin, the two inflection points and the input pin.
Based on the above technical solution, the avoidance module 330 is specifically configured to:
when one logic element is provided with a plurality of first linear connecting lines for output, a first avoiding area is arranged at a position close to the logic element;
and setting an inflection point of each first linear connecting line in the first avoidance area so that each first linear connecting line is avoided in the first avoidance area.
On the basis of the technical scheme, the line type comprises: a second line type;
the line type determining module 320 includes:
a second line type determining unit configured to determine the connection line as a second line type when the input pin is at the upper right of the output pin; two inflection points are arranged in the connecting line of the second line type, and the connecting line is an upper bending line which is sequentially connected with the output pin, the two inflection points and the input pin.
Based on the above technical solution, the avoidance module 330 is specifically configured to:
when one logic element is provided with a plurality of connecting line inputs of a second line type, a second avoidance area is arranged at a position close to the logic element;
and setting an inflection point of each second linear connecting line in the second avoidance area so that each second linear connecting line is avoided in the second avoidance area.
On the basis of the technical scheme, the line type comprises: a third line type;
the line type determining module 320 includes:
a third line type determining unit configured to determine that the connection line is a third line type when the input pin is on the left side of the output pin and a gap in a vertical direction between a logic element to which the input pin belongs and a logic element to which the output pin belongs is greater than zero; the connecting line of the third line type is provided with four inflection points, and the connecting line is an S-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin.
On the basis of the technical scheme, the logic element comprises a first logic element and a second logic element; the output pin of the first logic element and the input pin of the second logic element are connected with a plurality of connecting lines of a third line type;
the avoidance module 330 is specifically configured to:
a third avoidance area is arranged at a position close to the first logic element;
a fourth avoidance region is arranged in a gap between the first logic element and the second logic element in the vertical direction;
a fifth avoidance region is arranged at a position close to the second logic element;
The third avoidance area is provided with a first inflection point, the fourth avoidance area is provided with a second inflection point and a third inflection point, and the fifth avoidance area is provided with a fourth inflection point, so that each connecting line of the third line type is mutually avoided in the third avoidance area, the fourth avoidance area and the fifth avoidance area.
On the basis of the technical scheme, the line type comprises: a fourth line type;
the line type determining module 320 includes:
a fourth line type determining unit configured to determine that the connection line is a fourth line type when the input pin is on the left side of the output pin and a gap in a vertical direction between a logic element to which the input pin belongs and a logic element to which the output pin belongs is equal to or less than zero; the connecting line of the fourth line type is provided with four inflection points, and the connecting line is a U-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin.
On the basis of the technical scheme, the logic elements comprise a third logic element and a fourth logic element; the output pin of the third logic element and the input pin of the fourth logic element are connected with a plurality of fourth linear connecting lines;
The avoidance module 330 is specifically configured to:
a sixth avoidance region is arranged at a position close to the third logic element;
a seventh avoiding area is arranged below the third logic element and the fourth logic element;
setting an eighth avoidance region at a position close to the fourth logic element;
the sixth avoidance region is provided with a first inflection point, the seventh avoidance region is provided with a second inflection point and a third inflection point, and the eighth avoidance region is provided with a fourth inflection point, so that each connecting line of the fourth line type is mutually avoided in the sixth avoidance region, the seventh avoidance region and the eighth avoidance region.
On the basis of the technical scheme, the device further comprises:
and the up-down staggered avoidance module is used for carrying out avoidance processing on the up-down staggered connection lines when a plurality of connection lines with different line types exist on the same side of the logic element, so that all the connection lines are mutually avoided.
On the basis of the technical scheme, the up-down staggered avoiding module is specifically used for:
when the connecting lines staggered up and down are output from the logic element, the connecting lines bent up are avoided from connecting lines bent down;
When the connecting wires staggered up and down are input into the logic element, the connecting wires bent down avoid the connecting wires bent up.
Example 3
Fig. 4 is a schematic structural diagram of a connection avoidance device for a logic element according to embodiment 3 of the present invention. As shown in fig. 4, the connection avoidance device of the logic element includes: a processor 40, a memory 41, an input device 42 and an output device 43. The number of processors 40 in the link avoidance device of the logic element may be one or more, one processor 40 being illustrated in fig. 4. The number of memories 41 in the connection avoidance device of the logic element may be one or more, and one memory 41 is taken as an example in fig. 4. The processor 40, memory 41, input means 42 and output means 43 of the connection avoidance device of the logic elements may be connected by a bus or otherwise, in fig. 4 by way of example. The connection avoidance device of the logic element can be a computer, a server and the like. In this embodiment, the connection avoidance device of the logic element is used as a server for detailed description, and the server may be an independent server or a cluster server.
The memory 41 is used as a computer readable storage medium, and may be used to store a software program, a computer executable program, and a module, which are program instructions/modules corresponding to the connection avoidance method of a logic element according to any embodiment of the present invention (for example, the connection line determining module 310, the line type determining module 32, and the avoidance module 330 in the connection avoidance device of a logic element). The memory 41 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the device, etc. In addition, memory 41 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, memory 41 may further include memory located remotely from processor 40, which may be connected to the device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 42 may be used to receive input digital or character information and generate key signal inputs related to the setting and function control of the link avoidance device of the logic element, and may be a camera for capturing images and a pickup device for capturing audio data. The output means 43 may comprise an audio device such as a loudspeaker. The specific composition of the input device 42 and the output device 43 may be set according to the actual situation.
The processor 40 executes various functional applications of the device and data processing by running software programs, instructions and modules stored in the memory 41, i.e. implements the above-described connection avoidance method of logic elements.
Example 4
Embodiment 4 of the present invention further provides a storage medium containing computer-executable instructions for performing a link avoidance method of a logic element when executed by a computer processor, including:
determining all connecting lines between at least two logic elements, wherein each connecting line is used for connecting an output pin of one logic element with an input pin of the other logic element;
determining the line type of the connecting line according to the relative positions of the input pin and the output pin;
Carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines avoid each other
Of course, the storage medium containing the computer executable instructions provided by the embodiment of the invention is not limited to the operation of the connection avoidance method of the logic element, and the related operation in the connection avoidance method of the logic element provided by any embodiment of the invention can be executed, and the storage medium has corresponding functions and beneficial effects.
From the above description of embodiments, it will be clear to a person skilled in the art that the present invention may be implemented by means of software and necessary general purpose hardware, but of course also by means of hardware, although in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, where the instructions include a number of instructions for causing a computer device (which may be a robot, a personal computer, a server, or a network device, etc.) to execute the connection avoidance method of logic elements according to any embodiment of the present invention.
It should be noted that, in the connection avoidance device of the logic element, each unit and module included are only divided according to the functional logic, but not limited to the above division, so long as the corresponding function can be realized; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, reference to the term "in one embodiment," "in another embodiment," "exemplary," or "in a particular embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While the invention has been described in detail in the foregoing general description, embodiments and experiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (8)
1. A link avoidance method for a logic element, comprising:
determining all connecting lines between at least two logic elements, wherein each connecting line is used for connecting an output pin of one logic element with an input pin of the other logic element; wherein the input pins and the output pins are respectively distributed on one side of the logic element;
determining the line type of the connecting line according to the relative positions of the input pin and the output pin;
carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided;
the line type includes: a first line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
When the input pin is at the lower right of the output pin, determining the connecting line to be a first line type;
two inflection points are arranged in the first linear connecting line, and the connecting line is a lower bending line which is sequentially connected with the output pin, the two inflection points and the input pin;
the line type includes: a second line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is at the upper right of the output pin, determining the connecting line to be a second line type;
two inflection points are arranged in the second linear connecting line, and the connecting line is an upper bending line which is sequentially connected with the output pin, the two inflection points and the input pin;
the line type includes: a third line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is arranged on the left side of the output pin and the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction is larger than zero, determining that the connecting line is of a third line type;
The third linear connecting line is provided with four inflection points, and the connecting line is an S-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin;
the line type includes: a fourth line type;
the determining the line type of the connecting line according to the relative positions of the input pin and the output pin comprises the following steps:
when the input pin is at the left side of the output pin and the gap between the logic element to which the input pin belongs and the logic element to which the output pin belongs in the vertical direction is smaller than or equal to zero, determining that the connecting line is of a fourth line type;
the connecting line of the fourth line type is provided with four inflection points, and the connecting line is a U-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin;
when a plurality of connecting lines with different lines are staggered up and down on the same side of one logic element, the connecting lines staggered up and down are avoided, so that all the connecting lines are avoided.
2. The method according to claim 1, wherein the avoidance processing is performed on the same-line type connection lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connection lines are avoided mutually, and the method comprises:
When one logic element is provided with a plurality of first linear connecting lines for output, a first avoiding area is arranged at a position close to the logic element;
and setting an inflection point of each first linear connecting line in the first avoidance area so that each first linear connecting line is avoided in the first avoidance area.
3. The method according to claim 1, wherein the avoidance processing is performed on the same-line type connection lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connection lines are avoided mutually, and the method comprises:
when one logic element is provided with a plurality of connecting line inputs of a second line type, a second avoidance area is arranged at a position close to the logic element;
and setting an inflection point of each second linear connecting line in the second avoidance area so that each second linear connecting line is avoided in the second avoidance area.
4. The method of claim 1, wherein the logic element comprises a first logic element and a second logic element; the output pin of the first logic element and the input pin of the second logic element are connected with a plurality of connecting lines of a third line type;
The avoidance processing is performed on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided, and the method comprises the following steps:
a third avoidance area is arranged at a position close to the first logic element;
a fourth avoidance region is arranged in a gap between the first logic element and the second logic element in the vertical direction;
a fifth avoidance region is arranged at a position close to the second logic element;
the third avoidance area is provided with a first inflection point, the fourth avoidance area is provided with a second inflection point and a third inflection point, and the fifth avoidance area is provided with a fourth inflection point, so that each connecting line of the third line type is mutually avoided in the third avoidance area, the fourth avoidance area and the fifth avoidance area.
5. The method of claim 1, wherein the logic elements comprise a third logic element and a fourth logic element; the output pin of the third logic element and the input pin of the fourth logic element are connected with a plurality of fourth linear connecting lines;
the avoidance processing is performed on the same line type connecting lines on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are mutually avoided, and the method comprises the following steps:
A sixth avoidance region is arranged at a position close to the third logic element;
a seventh avoiding area is arranged below the third logic element and the fourth logic element;
setting an eighth avoidance region at a position close to the fourth logic element;
the sixth avoidance region is provided with a first inflection point, the seventh avoidance region is provided with a second inflection point and a third inflection point, and the eighth avoidance region is provided with a fourth inflection point, so that each connecting line of the fourth line type is mutually avoided in the sixth avoidance region, the seventh avoidance region and the eighth avoidance region.
6. The method according to claim 1, wherein the performing the avoidance process on the connection lines staggered up and down so that all the connection lines avoid each other includes:
when the connecting lines staggered up and down are output from the logic element, the connecting lines bent up are avoided from connecting lines bent down;
when the connecting wires staggered up and down are input into the logic element, the connecting wires bent down avoid the connecting wires bent up.
7. A link avoidance device for a logic element, comprising:
the connecting wire determining module is used for determining all connecting wires between at least two logic elements, and each connecting wire is used for connecting an output pin of one logic element with an input pin of the other logic element; wherein the input pins and the output pins are respectively distributed on one side of the logic element;
The line type determining module is used for determining the line type of the connecting line according to the relative positions of the input pin and the output pin;
the avoidance module is used for carrying out avoidance processing on the same line type connecting lines positioned on the same side of the logic element according to a preset avoidance mode associated with the line type, so that all the connecting lines are avoided;
the line type includes: a first line type;
the line type determining module includes:
a first line type determining unit configured to determine that the connection line is a first line type when the input pin is at the lower right of the output pin; two inflection points are arranged in the first linear connecting line, and the connecting line is a lower bending line which is sequentially connected with the output pin, the two inflection points and the input pin;
the line type includes: a second line type;
the line type determining module includes:
a second line type determining unit configured to determine the connection line as a second line type when the input pin is at the upper right of the output pin; two inflection points are arranged in the second linear connecting line, and the connecting line is an upper bending line which is sequentially connected with the output pin, the two inflection points and the input pin;
The line type includes: a third line type;
the line type determining module includes:
a third line type determining unit configured to determine that the connection line is a third line type when the input pin is on the left side of the output pin and a gap in a vertical direction between a logic element to which the input pin belongs and a logic element to which the output pin belongs is greater than zero; the third linear connecting line is provided with four inflection points, and the connecting line is an S-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin;
the line type includes: a fourth line type;
the line type determining module includes:
a fourth line type determining unit configured to determine that the connection line is a fourth line type when the input pin is on the left side of the output pin and a gap in a vertical direction between a logic element to which the input pin belongs and a logic element to which the output pin belongs is equal to or less than zero; the connecting line of the fourth line type is provided with four inflection points, and the connecting line is a U-shaped bending line which is sequentially connected with the output pin, the four inflection points and the input pin;
and the up-down staggered avoidance module is used for carrying out avoidance processing on the up-down staggered connection lines when a plurality of connection lines with different line types exist on the same side of the logic element, so that all the connection lines are mutually avoided.
8. A storage medium containing computer executable instructions which, when executed by a computer processor, are for performing a wire avoidance method of a logic element as claimed in any one of claims 1 to 6.
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Application publication date: 20210312 Assignee: Beijing Shuili Intelligent Building Technology Co.,Ltd. Assignor: KYLAND TECHNOLOGY Co.,Ltd. Contract record no.: X2022990000047 Denomination of invention: A connection avoidance method, device and storage medium of logic element License type: Common License Record date: 20220121 |
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