CN112486454B - Sequence multi-peak value searching and sorting device based on FPGA - Google Patents
Sequence multi-peak value searching and sorting device based on FPGA Download PDFInfo
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Abstract
The invention provides a sequence multi-peak value searching and sorting device based on an FPGA, which comprises a peak value register, an identification constant register, a comparison register and a processing unit. The processing unit performs a multimodal search ordering on the input sequence using a peak register, an identification constant register, and a comparison register. The invention effectively improves the sequence ordering speed, reduces the storage resources required to be occupied during ordering, and has stronger practicability and universality.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a sequence multi-peak searching and sorting device based on an FPGA.
Background
Sequence ordering is a classical algorithm problem, and there are a large number of ordering algorithms such as bubbling ordering, insertion ordering, quick ordering and the like. Sequencing the sequence is common processing in signal processing, and information of all sequences of the sequence is not required to be obtained, and only partial peak values and sequencing information thereof are required. For example, in applications such as object searching, there is a tendency to focus on the sorted head object information, or because part of the sequence information with lower energy is disturbed due to the influence of noise, only the sorted head information needs to be analyzed. If the existing full sequence ordering algorithm is directly applied, a large number of sequence values need to be stored, and a large amount of time and resources are wasted.
The FPGA has the capability of parallel signal processing, and the computing resources, the register resources and the like of the FPGA can be directly called through programming, so that the FPGA can be widely applied to the field of signal processing.
Disclosure of Invention
The invention aims to solve the technical problem of providing a sequential multi-peak searching and sorting device with less occupied storage space and short sorting time.
In order to solve the technical problems, the invention provides a sequence multi-peak value searching and sorting device based on an FPGA, which adopts the following technical scheme:
the device comprises a peak value register, an identification constant register, a comparison register and a processing unit;
the number of the peak value registers is N, the same as the number of the peak values to be searched and sequenced, the peak value registers store the first N peak values of the current sequenced sequence in real time, and the N peak value registers are arrayed according to the size sequence;
the identification constant register is used for storing N peak value register identification constants corresponding to N peak value registers, the bit width of the identification constant is N, and for the nth peak value register, the constant value of the identification constant is (2 (N-n+1)) -1;
the number of the comparison registers is 1; the bit width of the comparison register is N bits, the bit width is the same as the number of the peak value registers, and each 1bit corresponds to one peak value register; the highest bit of the comparison register corresponds to the peak register storing the maximum value in the N peak registers, the lowest bit of the comparison register corresponds to the peak register storing the minimum value in the N peak registers, and other sequences correspond to each other;
the processing unit performs a multimodal search ordering on the input sequence using a peak register, an identification constant register, and a comparison register. Sequence value input is carried out by sequential running water in sequence, and a sequence value i is input at the time t 1 Parallel comparison i 1 And updating the value of N bits in the comparison register to a corresponding value j at the time t+1 according to the ratio of the value in the N peak registers 1 The method comprises the steps of carrying out a first treatment on the surface of the Parallelizing the identification constant in the identification constant register with j 1 And comparing, namely finishing peak value screening and sorting updating of the N peak value registers at the time t+2 until the sequence searching is finished, wherein the values stored in the N peak value registers are N peak values.
Further, the value j of N bit in the comparison register 1 The acquisition method comprises the following steps:
for each peak register, if i 1 If the value is smaller than or equal to the value in a certain peak value register, the value of the bit corresponding to the peak value register in the comparison register is set to be 0, if i 1 And setting the value of the bit corresponding to the peak value register in the comparison register to be 1 when the value is larger than the value in the peak value register.
Further, the step of completing the peak value screening and the sorting updating of the N peak value registers at the time t+2 is specifically as follows:
the value of the comparison register at time t+1 is updated to j 1 Then, the identification constant of each corresponding peak value register in the identification constant registers is parallel to j 1 In comparison with the comparison result of the comparison,if the identification constant of the nth peak register is greater than j 1 The nth peak register at time t+2 holds the value at time t+1; if the identification constant of the nth peak register is equal to j 1 The value of the nth peak register at time t+2 is updated to i 1 The method comprises the steps of carrying out a first treatment on the surface of the If the identification constant of the nth peak register is less than j 1 The value of the nth peak register at time t+2 is updated to the value of the peak register n-1 at time t+1.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a sequence multi-peak searching and sorting device based on an FPGA, which fully exerts the advantages of parallelism and flexibility of the FPGA, can quickly, efficiently and stably search out the first N peaks of a sequence, and sorts the first N peaks according to the size. The time complexity of the method is O (n), and the method only needs to be traversed once by the search sequence, so that the sequence multi-peak sorting speed is effectively improved, and the target value is quickly searched. The space complexity of the invention is O (1), the storage space is irrelevant to the length of the sequence, only a small amount of register resources are needed, and additional on-chip RAM storage resources are not needed, thereby saving on-chip RAM storage resources and improving the sequencing efficiency. The data distribution of the common sequences to be sequenced in the traditional sequencing algorithm can cause different sequencing time, which is unfavorable for the estimation of calculation time. Compared with the traditional sorting algorithm, the method has the advantages of short sorting time, small occupied storage space and stable sorting time, and has strong practicability. The search ordered sequence can be a fixed-point value or a floating-point value, and has strong universality.
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FIG. 1 is a schematic diagram of a sequential multi-peak search sequencing apparatus of the present invention for running water treatment.
Detailed Description
The technical scheme of the invention is further described below with reference to the accompanying drawings.
A sequence multi-peak value searching and sorting device based on FPGA comprises a peak value register, an identification constant register, a comparison register and a processing unit.
The number of the peak value registers is N, which is the same as the number of peak values to be searched and ordered. The peak value register stores the top N peak values of the current ordered sequence in real time, and after the sequence search is finished, the values stored in the N peak value registers are the top N peak values. And N peak registers, wherein each peak register is ordered as N, n=1, 2,3 … N, the registers ordered as N are called N-th registers, the N peak registers are arranged according to the order of the sizes, the 1-th peak register stores the maximum value of data stored in the N peak registers, and the N-th peak register stores the minimum value of data stored in the N peak registers. N needs to be less than or equal to the length of the sequence that needs to be searched.
The bit width of the peak value register is M, and the value of M is determined according to the data bit width of the sequence to be ordered; confirming whether the sequence is a signed number or an unsigned number to determine the minimum value which can be represented by the M bit width; the value of the N peak registers is initialized to the minimum value that can be represented by the M-bit width.
The identification constant register is used for storing N peak value register identification constants corresponding to N peak value registers, the bit width of the identification constant is N, for the nth peak value register, the constant value of the identification constant is (2 (N-n+1)) -1, and the value in the identification constant register is a fixed value.
The number of the comparison registers is 1; the bit width of the comparison register is N bits, the bit width is the same as the number of the peak value registers, and each 1bit corresponds to one peak value register; the highest bit of the comparison register corresponds to the peak register storing the maximum value in the N peak registers, the lowest bit of the comparison register corresponds to the peak register storing the minimum value in the N peak registers, and other sequences correspond.
The value of the comparison register is initialized to the maximum value of the unsigned number, namely N bit wide data, and each bit data is 1.
The processing unit performs a multimodal search ordering on the input sequence using a peak register, an identification constant register, and a comparison register.
Inputting sequence values to be ordered, and setting the values as i in turn 1 ，1 2 ，i 3 …, the sequence values to be sorted are pipelined as shown in fig. 1.
Let t be input i 1 Parallel comparison i 1 After comparing with the values in the N peak registers, the value of N bit in the comparison register is updated at time t+1. the comparison register at time t+1 as a whole obtains a corresponding value j 1 。
Specifically, for each peak register, if i 1 If the value is smaller than or equal to the value in a certain peak value register, the value of the bit corresponding to the peak value register in the comparison register is set to be 0, if i 1 And setting the value of the bit corresponding to the peak value register in the comparison register to be 1 when the value is larger than the value in the peak value register.
Taking n=4 as an example, the value of the peak register at time t is set to 99, 88, 77, 66, i 1 79, the value of the comparison register at time t+1 is 0b0011, see Table 1 for details. As can be seen from Table 1, j at this time 1 The value of (1) is 0b0011.
Table 1 t+1 time comparison register calculation schematic table
Parallelizing the identification constant of each peak value register corresponding to the identification constant register with j 1 And comparing, and finishing the peak value screening and the sorting updating of the N peak value registers at the time t+2.
Specifically, the value of the comparison register at time t+1 is updated to j 1 Then, the identification constant of each corresponding peak value register in the identification constant registers is parallel to j 1 Comparing, if the identification constant of the nth peak register is greater than j 1 The nth peak register at time t+2 holds the value at time t+1; if the identification constant of the nth peak register is equal to j 1 The value of the nth peak register at time t+2 is updated to i 1 The method comprises the steps of carrying out a first treatment on the surface of the If the identification constant of the nth peak register is less than j 1 The value of the nth peak register at time t+2 is updated to the value of the peak register n-1 at time t+1.
As in the example above, the peak register values at time t+1 are 99, 88, 77, 66, i 1 For 79, compare register j 1 The value of (1) is 0b0011, the identification constants of the 1 st and 2 nd peak registers are larger than 0b0011, and the 1 st and 2 nd peak registers at the time t+2 keep the value at the time t+1; the identification constant of the 3 rd peak register is equal to 0b0011, and the value of the 3 rd peak register at the time t+2 is updated to 79; the identification constant of the 4 th peak register is less than 0b0011, and then the value of the 4 th peak register at time t+2 is updated to the value 77 of the 3 rd register at time t+1, as shown in table 2.
Table 2 t+2 time peak register change schematic table
The sequence is sequentially pipelined to input sequence values, and the sequence values are compared in parallel, and peak value screening and sorting processing is performed on the current input.
When the sequence search is completed, the values stored in the N peak registers are N peaks, and have been sorted from large to small in the order of n=1 to n=n.
The sequence multi-peak searching and sorting device can process fixed-point values and floating-point values. If the fixed point value is set, the time difference between the time t+1 and the time t is 1 signal processing clock period. If the time difference between the time t+1 and the time t is a floating point value, the time difference 1 is the number of processing clock cycles required by 1 floating point operation, and the specific number of clock cycles is determined according to the operation capability of the FPGA.
The above embodiments are only for explaining and describing the technical solution of the present invention, but should not be construed to limit the scope of protection of the claims. It should be clear to those skilled in the art that any simple modification or substitution of the technical solution of the present invention will result in a new technical solution that falls within the scope of the present invention.
Claims (3)
1. The sequence multimodal value searching and sorting device based on the FPGA is characterized by comprising a peak value register, an identification constant register, a comparison register and a processing unit;
the number of the peak value registers is N, the same as the number of the peak values to be searched and sequenced, the peak value registers store the first N peak values of the current sequenced sequence in real time, and the N peak value registers are arrayed according to the size sequence;
the identification constant register is used for storing N peak value register identification constants corresponding to N peak value registers, the bit width of the identification constant is N, and for the nth peak value register, the constant value of the identification constant is (2 (N-n+1)) -1;
the number of the comparison registers is 1; the bit width of the comparison register is Nbit, the bit width is the same as the number of the peak value registers, and each 1bit corresponds to one peak value register; the highest bit of the comparison register corresponds to the peak register storing the maximum value in the N peak registers, the lowest bit of the comparison register corresponds to the peak register storing the minimum value in the N peak registers, and other sequences correspond to each other;
the processing unit performs multimodal search sequencing on the input sequence by using a peak value register, an identification constant register and a comparison register;
sequence value input is carried out by sequential running water in sequence, and a sequence value i is input at the time t 1 Parallel comparison i 1 And the value of Nbit in the comparison register is updated to a corresponding value j at the time t+1 according to the ratio of the value in the N peak registers 1 The method comprises the steps of carrying out a first treatment on the surface of the Parallelizing the identification constant of each peak value register corresponding to the identification constant register with j 1 Comparing, completing the peak value screening and sorting updating of the N peak value registers at the time t+2 until the sequence searching is completed, wherein the values stored in the N peak value registers are N peak values;
the method completes the peak screening and the sorting updating of N peak registers at the time t+2, and is specifically as follows:
the value of the comparison register at time t+1 is updated to j 1 Then, the identification constant of each corresponding peak value register in the identification constant registers is parallel to j 1 Comparing, if the identification constant of the nth peak register is greater than j 1 The nth peak register at time t+2 holds the value at time t+1; if the identification constant of the nth peak register is equal toj 1 The value of the nth peak register at time t+2 is updated to i 1 The method comprises the steps of carrying out a first treatment on the surface of the If the identification constant of the nth peak register is less than j 1 The value of the nth peak register at time t+2 is updated to the value of the peak register n-1 at time t+1.
2. The FPGA-based sequential multimodal search sequencing apparatus of claim 1, wherein the value j of Nbit in said compare register 1 The acquisition method comprises the following steps:
for each peak register, if i 1 If the value is smaller than or equal to the value in a certain peak value register, the value of the bit corresponding to the peak value register in the comparison register is set to be 0, if i 1 And setting the value of the bit corresponding to the peak value register in the comparison register to be 1 when the value is larger than the value in the peak value register.
3. An FPGA-based sequential multimodal search sequencing apparatus according to claim 1 or claim 2, wherein the sequential values are fixed point values or floating point values.
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| US3810113A (en) * | 1971-08-27 | 1974-05-07 | Nat Res Dev | Digital data processing apparatus |
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