CN112486402A

CN112486402A - Storage node and system

Info

Publication number: CN112486402A
Application number: CN201910865315.5A
Authority: CN
Inventors: 钟刊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2021-03-12

Abstract

The utility model discloses a storage node and system, relates to the field of distributed systems, and solves the problem of how to reduce the time delay of the storage node for processing data intensive tasks. The storage node comprises a processor and a memory, wherein the memory comprises a processing unit and a memory. After receiving a data processing request sent by an application server, a processor reads data from a memory of a storage node to a memory of a memory according to the data processing request; the processor also sends at least one instruction to the processing unit of the memory to instruct the processing unit to process the data; after receiving the instruction, the processing unit reads data from a memory of the memory and processes the data; and finally, the processor sends the processed data to an application server. Therefore, the data is prevented from moving on the memory bus, the problem of a memory wall is solved, and the data processing delay of the storage node when processing a data intensive task is effectively reduced.

Description

Storage node and system

Technical Field

The present application relates to the field of distributed systems, and in particular, to a storage node and a system.

Background

In a distributed system, a computing node may split a Data-Intensive (Data-Intensive) task into a plurality of Data processing subtasks according to a storage location of Data, and send each Data processing subtask to a corresponding storage node. Therefore, the data is processed nearby by utilizing the computing power of the storage node, the data transmission on a network and an input/output (IO) bus is avoided, and the occupancy rate of the transmission data on the network resource and the IO bus resource and the time delay of data processing are effectively reduced. Data intensive tasks refer to data processing tasks that require a processor to frequently access memory.

However, since there are frequent and large numbers of memory access operations in the data processing subtasks pushed down to each storage node, the time delay for the processor in the storage node to process data is increased, and furthermore, the memory bus resources in the storage node compete, the time delay for other tasks to access the memory is increased, and a "memory wall" problem is generated. Therefore, how to reduce the latency of the storage node in processing the data-intensive task is a problem to be solved.

Disclosure of Invention

The application provides a storage node and a system, and solves the problem of how to reduce the time delay of processing a data-intensive task by the storage node.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present application provides a storage node, where the storage node includes a processor and a memory, and the memory includes a processing unit and a memory. After receiving a data processing request sent by an application server, a processor reads data from a memory of a storage node to a memory of a memory according to the data processing request; the processor also sends at least one instruction to the processing unit of the memory to instruct the processing unit to process the data; after receiving the instruction, the processing unit reads data from the memory of the memory, processes the data and feeds the processed data back to the processor of the storage node; and finally, the processor sends the processed data to an application server.

According to the storage node provided by the embodiment of the application, the processing unit is added in the memory, and the processor of the storage node indicates the processing unit in the memory to process the data-intensive task, so that the data is prevented from moving on a memory bus, the problem of a memory wall is solved, and the data processing delay of the storage node in the process of processing the data-intensive task is effectively reduced.

In one possible implementation, each instruction contains an address and an operation type for which data is located in memory.

In another possible implementation, the memory further includes a memory controller, which is different from the processing unit.

In another possible implementation manner, the memory further includes a cache for storing at least one instruction.

In another possible implementation manner, the storage node includes N memories, N is an integer, N is greater than or equal to 1, wherein the processor is further configured to determine at least one memory meeting the storage capacity requirement according to the remaining storage capacities of the N memories; the processor is further configured to determine a memory from the at least one memory that meets the computational requirements.

In another possible implementation manner, the memory includes M processing units, M is an integer, M is greater than or equal to 1, the memory further includes a status register, the status register is used for indicating a use status of the M processing units included in the memory, and the processor is used for determining the memory meeting the calculation requirement from at least one memory according to indication information of the status register of each memory.

Therefore, the processor of the storage node selects a proper memory allocation memory to unload the data intensive program segment according to the state of the processing unit indicated by the state register in each memory, so that memory congestion and waiting caused by incapability of sensing the memory state are avoided, and the unloading effectiveness of the data intensive program segment is ensured.

In a second aspect, the present application provides a distributed system, where the distributed system includes an application server and a storage node, the storage node includes a processor and a memory, and the memory includes a processing unit and a storage, where: the application server is used for sending a data processing request to the storage node; the processor is used for receiving a data processing request sent by the application server and reading data to the memory of the memory according to the data processing request; the processor is further used for sending at least one instruction to the processing unit, wherein the instruction is used for instructing the processing unit to process the data; the processor is also used for sending the processed data to the application server; the application server is used for receiving the processed data sent by the storage node.

The distributed system provided by the embodiment of the application transfers the data intensive subtasks from the computing nodes to the storage nodes, and directly completes the computation of data in the storage nodes by using the computing power of the storage nodes, so that the performance bottleneck caused by network transmission is avoided. In addition, by adding the processing unit in the memory, the processor of the storage node indicates the processing unit in the memory to process the data-intensive task, and the movement of data on a memory bus is avoided, so that the problem of a memory wall is solved, and the data processing delay of the storage node when processing the data-intensive task is effectively reduced.

In a third aspect, the present application provides a method for processing data, where the method is applied to a storage node, the storage node includes a processor and a memory, the memory includes a processing unit and a storage, and the method includes: the processor receives a data processing request sent by the application server, and reads data to a memory of the memory according to the data processing request; the processor sends at least one instruction to the processing unit, wherein the instruction is used for instructing the processing unit to process the data; and the processor sends the processed data to the application server.

The method for processing data is the same as that described in the first aspect, and is not described herein again.

In a fourth aspect, the present application further provides a computer-readable storage medium comprising: computer software instructions; the computer software instructions, when executed in the communication device, cause the communication device to perform the method of the first aspect as described above.

In a fifth aspect, the present application also provides a computer program product comprising instructions for causing a communication device to perform the method of the first aspect when the computer program product is run in the communication device.

In a sixth aspect, the present application provides a chip system, where the chip system includes a processor and may further include a memory, and is configured to implement the function of the memory in the foregoing method. The chip system may be formed by a chip, and may also include a chip and other discrete devices.

In addition, the technical effects brought by the design manners of any aspect can be referred to the technical effects brought by the different design manners in the first aspect, and are not described herein again.

In the present application, the names of the storage nodes do not limit the devices themselves, and in practical implementations, the devices may appear by other names. Provided that the function of each device is similar to that of the present application, and that the devices are within the scope of the claims of the present application and their equivalents.

Drawings

Fig. 1 is an exemplary diagram of a distributed system according to an embodiment of the present invention;

fig. 2 is a schematic view of a memory wall provided in the present application;

fig. 3 is a diagram illustrating an exemplary architecture of a distributed system according to an embodiment of the present application;

FIG. 4 is a diagram illustrating an exemplary structure of a DP-DIMM according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a near data processing provided by an embodiment of the present application;

fig. 6 is a flowchart of a method for processing data according to an embodiment of the present application.

Detailed Description

The terms "first," "second," and "third," etc. in the description and claims of this application and the above-described drawings are used for distinguishing between different objects and not for limiting a particular order.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. In the description of the text of the present application, the character "/" generally indicates that the former and latter associated objects are in an "or" relationship; in the formula of the present application, the character "/" indicates that the preceding and following related objects are in a relationship of "division".

For clarity and conciseness of the following descriptions of the various embodiments, a brief introduction to the related art is first given:

in general, a processor loads data from a memory to a memory through an IO bus or a network, and then reads the data from the memory for processing. However, in the big data era, the amount of data to be processed is explosively increasing, and the traditional data processing architecture needs to transmit a large amount of data. In a distributed system, for data-intensive applications such as a database, a large number of IO operations are first required for query processing, and data is loaded into a memory of a compute node, so that an IO bus or a network becomes a performance bottleneck of the system, which brings about a great performance problem: 1) a large amount of data movement increases the delay of data processing; 2) data transmission causes IO bus or network resource competition, affects data access of other applications in the system, and affects performance of other applications. Therefore, for data-intensive applications, data transmission should be avoided as much as possible, and the data moving overhead should be reduced.

Near Data Processing (NDP/NDC) is a method or concept of Processing Data, i.e., moving the Processing and computation of Data to a place close to the Data. Therefore, data movement is reduced or even avoided as much as possible, and the data processing efficiency is improved. The NDP can be divided into three types of In-Storage Processing (ISP), On-Disk Data Processing (ODDP), and In-Memory Processing (PIM) according to Processing modes.

The ISP generally refers to a system architecture in which computation and storage are separated, and transfers data-intensive tasks from a computing node to a storage node, and the computing power of the storage node is utilized to directly complete the computation of data in the storage node, thereby avoiding performance bottleneck caused by network transmission.

ODDP refers to the transfer of computing tasks from the host side to a specific storage device. For example, in Solid State Drives (SSD), data is processed in close proximity using the computing power of a controller or dedicated processing logic in the storage device.

PIM adds a calculation logic unit in the memory module to calculate in the memory module, thereby avoiding the movement of data on the memory bus.

Fig. 1 is an exemplary diagram of a distributed system according to the present embodiment. The distributed system adopts a shared disk (share disk) architecture with separated calculation and storage, and comprises a data processing layer, a network layer and a storage layer. The data processing layer includes at least one compute node 101. The computing node 101 is mainly responsible for performing computing processing on data. Such as calculations associated with a database. The storage tier includes at least one storage node 102. The storage nodes 102 are used to store data. The network layer may be an InfiniBand (IB) network 103. And the computing nodes and the storage nodes transmit data by using the IB network interconnection.

In some embodiments, one database server may be used to implement the functions of the computing node, and a plurality of database servers may also be used to implement the functions of the computing node, which is not limited in this application. The storage node may use one storage server (storage server) to implement the function of the storage node, or may use multiple storage servers to implement the function of the storage node, which is not limited in this application.

The distributed system can handle data intensive tasks using ISP-type near data processing techniques. Compute nodes 101 primarily process compute-intensive tasks while pushing down partially data-intensive tasks into storage nodes. For example, the storage node 102 may implement where predicate filtering, column filtering, Join connection filtering, etc. operations in a Structured Query Language (SQL) Query. The table data is specifically processed in the storage nodes, thereby reducing the amount of data transfer from the storage nodes to the compute nodes.

By computationally intensive tasks may be meant tasks that require a large number of operations on data.

A data intensive task may refer to a task that needs to read a large amount of data and perform operations on the data.

When a storage node processes data-intensive tasks, the processor needs to make frequent accesses to memory via the memory bus using load/store instructions.

As shown in fig. 2, in the past 20 years, the performance of processors has been rapidly increasing at a rate of about 60% per year, while the increase in memory performance has been only about 7%, resulting in the current memory speed falling significantly behind the processor speed. There is a severe performance gap between the memory and the processor, making it difficult to fully exploit the advantages of the processor, resulting in the memory system becoming a performance bottleneck for the computing system. Especially in the High Performance Computing (HPC) scenario with Memory Intensive (Memory Intensive), the Memory speed severely limits the system Performance. In addition, the internal bus between the memory and the processor also has the problems of low bandwidth, high delay and the like, and the data transmission is expensive, thereby seriously affecting the performance of the computing system. This Memory bottleneck that limits system performance is commonly referred to as a "Memory Wall".

Thus, memory bus bandwidth and processing data latency become performance bottlenecks for storage nodes to handle data-intensive tasks. In addition, a large amount of memory access causes memory bus resource competition of a memory system, memory access delay of other tasks is increased, and the performance of data processing in the storage node is restricted by the memory wall problem.

According to the storage node provided by the embodiment of the application, the processing unit is added in the memory, and the processor of the storage node indicates the processing unit in the memory to process the data-intensive task, so that the movement of data on a memory bus is avoided, the problem of a memory wall is solved, and the time delay of the storage node for processing the data-intensive task is effectively reduced.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 3 is a diagram illustrating an architecture of a distributed system according to an embodiment of the present application. The distributed system includes a compute node 301 and a storage node 302. The compute node 301 includes a processor 3011, a memory 3012, a data analysis module 3013, a subtask dispatcher module 3014, and the like. In some embodiments, the data analysis module 3013 and the subtask distribution module 3014 may be a logical unit. The functions of the data analysis module 3013 and the functions of the sub-task distribution module 3014 are performed by the processor 3011. The storage node 302 includes a processor 3021, a memory 3022, a memory controller 3023, a storage medium 3024 (e.g., a Hard Disk Drive (HDD) or SSD), and an IO controller 3025. Memory 3022 includes Dual-Inline-Memory-Modules (DIMMs) and data processing Dual-Inline-Memory-Modules (DP-DIMMs). DIMMs differ from DP-DIMMs in that DP-DIMMs contain processing units and DIMMs do not contain processing units.

The compute node 301 is mainly used to process compute-intensive tasks and run big data analysis programs (e.g., Online Analytical Processing (OLAP)). In some embodiments, the computing node 301 may be an application server (e.g., a database server, etc.). The distributed system may include a plurality of computing nodes 301 that collectively perform data processing and share a set of storage systems. The storage system is mainly responsible for storing data and responding to a data read-write request of an upper-layer computing node. The storage system may comprise a plurality of storage nodes 302.

The storage node 302 is used for running storage processing logic software and is responsible for persistent storage of data, so that reliability and availability of the data are guaranteed.

Fig. 3 is a schematic diagram, and other network devices (e.g., switches or routers) for transmitting data between the compute nodes and the storage nodes may be included in the distributed system, which are not shown in fig. 3. The embodiments of the present application do not limit the number of compute nodes and storage nodes included in the distributed system.

For big data analytics applications, the computing node 301 needs to read and process the massive data from the storage node 302, and therefore, the computing node 301 includes data intensive tasks when processing the big data analytics applications, such as a full-table scan operation in an OLAP application. In order to avoid the increase of the Data processing delay due to the transmission of mass Data in the network between the computing nodes and the storage nodes, the Data analysis module 3013 of the computing node 301 may analyze the large Data analysis type application, screen out a Data-Intensive task, and split the Data-Intensive task into a plurality of Data processing subtasks (or called Data-Intensive subtasks) according to the storage location of the Data by the Subtask distribution module 3014, and send each Data-Intensive Subtask to the corresponding storage node 302.

In some embodiments, the compute node 301 may send a data processing request to the storage node 302. The data processing request is used to instruct the storage node 302 to perform a data intensive subtask. Note that the data processing request is not an IO request. The data processing request is a message to push down data-intensive subtasks to the storage node. The data processing request may include a process type, data location information, data calculation information, and description information. The processing type may refer to data intensive. The data location information is used to indicate location information for storing data of the data-intensive subtasks. For example, if the data of the data-intensive subtask is stored in a file system, the data location information includes information such as a file name. If the data of the data-intensive subtask is stored in the K-V storage system, the data location information includes a K value (key). The data computation information includes computation instructions for the data-intensive subtasks. The description information includes format information for processing data of the data-intensive subtasks.

For example, assume that the data-intensive subtasks are data compression tasks. The data calculation information includes instructions related to data compression. The description information includes a compression format in which data is compressed. The compression format may be RAR.

After the processor 3021 of the storage node 302 receives the data processing request sent by the computing node 301, the processor 3021 sends a read request to the IO controller 3025 according to the data location information, and controls the IO controller 3025 to read data of the data-intensive subtask from a local storage medium 3024 (e.g., a disk) and store the data in the memory 3022. In some embodiments, if processor 3021 determines that data for a data intensive subtask needs to be processed by memory 3022, the data may be stored in a DP-DIMM. In other embodiments, if processor 3021 determines that the data of the data intensive subtask is processed by itself, the data may be stored to a DIMM or a DP-DIMM. The processor 3021 controls the memory controller 3023 to read data from the memory 3022 and transmit the read data to the processor 3021, and the processor 3021 performs corresponding calculation on the data according to the data calculation information and returns the final calculation result to the calculation node 301. Therefore, the data are processed nearby by utilizing the computing power of the storage nodes, the data are prevented from being transmitted on the network and the IO bus, and the occupancy rate of network resources and IO bus resources and the time delay of data processing in the data transmission process are effectively reduced.

The processor 3021 of the storage node 302 not only needs a large number of IO bus operations but also needs a large number of memory accesses when processing the data-intensive subtasks, and thus the "memory wall" problem becomes a performance bottleneck for the storage node to process the data-intensive subtasks.

In other embodiments, to avoid the "memory wall" problem when the processor 3021 of the storage node 302 processes the data-intensive subtasks, the processor 3021 may offload data-intensive segments of the data-intensive subtasks (or memory-intensive segments) to a DP-DIMM, which processes the data-intensive segments, thereby avoiding frequent accesses to the memory 3022 by the processor 3021 and reducing data transfers over the memory bus.

In the present embodiment, DP-DIMM refers to a memory with a processing unit integrated into the DIMM. The processing units in the DP-DIMM may perform specific computations on the data, substantially reducing the access of processor 3021 to memory 3022 in storage node 302. Multiple DP-DIMMs may be provided in each storage node 302. The DP-DIMM can be plugged into a memory slot and directly connected with a memory bus.

FIG. 4 is a diagram illustrating an exemplary structure of a DP-DIMM according to an embodiment of the present application. The DP-DIMM includes a processing unit 401 and a memory 402. In some embodiments, the Memory 402 may be a Memory unit having at least one Memory granule (e.g., Dynamic Random Access Memory (DRAM) or Synchronous Dynamic Random Access Memory (SDRAM)) integrated thereon. One or more processing units 401 may be integrated in the DP-DIMM, depending on the size of the memory capacity of the memory units in the DP-DIMM. Processing unit 401 may receive at least one instruction (e.g., a data-intensive program segment) from processor 3021 instructing processing unit 401 to process data from the data-intensive program segment. Each instruction contains an address where the data is located in memory and an operation type. Operation types include, but are not limited to, addition, subtraction, multiplication, and division. In other embodiments, the processing unit 401 receives the instruction, reads data from the memory 402, processes the data, and feeds the processed data back to the processor 3021, or stores the processed data in the memory 402, and the processor 3021 obtains the processed data from the memory 402. Processor 3021 may send the processed data to compute node 301.

In some embodiments, the storage node 302 further includes a network card, and the network card may read data from a Memory and send the processed data to the computing node 301 in a Remote Direct data Access (RDMA) manner.

Further, the DP-DIMM may also include a cache 403 and a memory controller 404. The cache is used to store at least one instruction sent by processor 3021. The memory controller 404 is configured to determine a physical address of the data in the memory 402 according to the at least one instruction, retrieve the data from the memory 402 according to the physical address, and transmit the data to the processing unit 401.

In some embodiments, memory controller 404 may be integrated into a DP-DIMM, but memory controller 404 and processing unit 401 are two distinct components.

In some embodiments, storage node 302 may include N DP-DIMMs, each DP-DIMM including M processing units, N and M being integers, N ≧ 1, M ≧ 1. Processor 3021, having received the data-intensive subtasks, determines the storage capacity requirements and the computation requirements needed to process the data-intensive subtasks, processor 3021 may determine at least one DP-DIMM that meets the storage capacity requirements based on the remaining storage capacity of the N DP-DIMMs, and then processor 3021 may determine the DP-DIMM that meets the computation requirements from the at least one DP-DIMM.

In still other embodiments, the DP-DIMM may further include a status register 405, the status register 405 to indicate a status of use of the M processing units included with the DP-DIMM. Processor 3021 may determine a DP-DIMM that meets the computational requirements from the at least one DP-DIMM based on the indication from the status register of each DP-DIMM.

In this embodiment, M processing units 401, a memory controller 404, a status register 405, and a cache 403 may be integrated together, which is referred to as an on-chip processor.

For example, for an on-chip processor having 4 processing units, "1111" indicates that each processing unit is occupied, and "1001" indicates that processing unit 1 and processing unit 4 are occupied, and that processing unit 2 and processing unit 3 are available.

It should be noted that one DP-DIMM may include a plurality of on-chip processors, and the number of the on-chip processors is not limited in the present application. Each on-chip processor may be coupled to a memory 402.

The pluggable DIMM-based DP-DIMM provided by the embodiments of the present application, i.e., a multi-core processor or a Single Instruction Multiple Data (SIMD) processor integrated in the DIMM, directly completes the calculation of the Data intensive program segment in the DIMM. If a SIMD processor is used, multiple processing units may be used simultaneously to achieve parallel computing. Compared with Oracle Exadata, the occupied condition of the processor of the storage node can be reduced by 20%, more processor resources are reserved for other storage services, and meanwhile, the execution time of the data intensive subtask is reduced by more than 50%.

In some embodiments, if processor 3021 does not determine a DP-DIMM to be available, in order to avoid processing data delays caused by waiting for a DP-DIMM, the data-intensive program segments will not be offloaded to a DP-DIMM, but rather will be processed using conventional processor-computational means.

Fig. 5 is a schematic diagram of near data processing according to an embodiment of the present disclosure. The application server pushes down the data-intensive subtasks to the storage nodes storing the corresponding data, and the storage nodes push down the data-intensive program segments to the DP-DIMM when processing the data-intensive subtasks, and the DP-DIMM processes the data-intensive program segments.

To facilitate the use of DP-DIMMs by processors of storage nodes, the present application provides a programming interface for DP-DIMMs. For example, the programming interface for a DP-DIMM may be CreateModContext (). When the processor of the storage node executes the statement createmiccoxt (), an appropriate DP-DIMM is selected to offload the data-intensive program segment, and the data of the data-intensive program segment is stored in the selected DP-DIMM. If there is no appropriate DP-DIMM, no offload will occur. Data intensive program segments that need to be offloaded to execution on a DP-DIMM may be defined using PIMKernelBegin () and PIMKernelEnd ().

By way of example, the following is an example of offloading convolution operations in a neural network algorithm to a DP-DIMM.

Fig. 6 is a flowchart of a method for processing data according to an embodiment of the present application. The description is made here taking, as an example, the computing node 301 and the storage node 302 shown in fig. 3. Computing node 301 may refer to an application server. Storage node 302 includes a processor 3021 and a memory 3022. Memory 3022 includes DIMMs and DP-DIMMs. Memory 3022 comprises a DP-DIMM including a processing unit and memory. Memory 3022 may include a DP-DIMM such as that shown in FIG. 4. The processing unit may be the processing unit 401 shown in fig. 4. The memory may be the memory 402 shown in fig. 4. As shown in fig. 6, the method includes the following steps.

S601, the application server sends a data processing request to the storage node.

S602, the processor of the storage node receives a data processing request.

S603, the processor reads data to a memory of the memory according to the data processing request.

In some embodiments, the processor reads data from a storage medium (e.g., a disk) of the storage node according to the data processing request, and stores the data in a memory of the memory. Memory is assumed to refer to DP-DIMMs described in the above embodiments.

S604, the processor sends at least one instruction to the processing unit.

The instructions are for instructing the processing unit to process the data.

S605, the processing unit reads data from the memory of the memory.

And S606, processing the data by the processing unit.

S607, the processing unit feeds back the processed data to the processor.

And S608, the processor receives the processed data fed back by the processing unit.

And S609, the processor sends the processed data to the application server.

For the specific implementation of processing data, reference may be made to the description of the foregoing embodiments, and details are not repeated.

Therefore, by adding the processing unit in the memory, the processor of the storage node instructs the processing unit in the memory to process the data-intensive tasks, so that the data is prevented from moving on a memory bus, the processing speed of the storage node for processing the data-intensive subtasks is effectively improved, and the time delay of data processing is reduced. The data transmission quantity between the storage nodes and the computing nodes is greatly reduced, and the application performance is improved. For data intensive tasks such as OLAP, the data transmission quantity between a computing node and a storage node can be reduced by more than 5 times, and the performance can be improved by 5-10 times.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A storage node, comprising a processor and a memory, the memory comprising a processing unit and a memory, wherein:

the processor is used for receiving a data processing request sent by the application server and reading data to the memory of the memory according to the data processing request;

the processor is further configured to send at least one instruction to the processing unit, where the instruction is configured to instruct the processing unit to process the data;

the processor is further configured to send the processed data to the application server.

2. The storage node of claim 1, wherein each of said instructions contains an address and an operation type for said data located in said memory.

3. The storage node of claim 1 or 2, wherein the memory further comprises a memory controller, the memory controller being distinct from the processing unit.

4. The storage node of any of claims 1-3, wherein the memory further comprises a cache, the cache to store the at least one instruction.

5. The storage node according to any of claims 1-4, wherein the storage node comprises N memories, N being an integer, N ≧ 1, wherein,

the processor is further configured to determine at least one memory meeting the storage capacity requirement according to the remaining storage capacity of the N memories;

the processor is further configured to determine a memory from the at least one memory that meets the computational requirements.

6. The storage node of claim 5, wherein the memory includes M processing units, M is an integer, M ≧ 1, the memory further including a status register for indicating a status of use of the M processing units included in the memory, wherein,

the processor is used for determining the memory meeting the calculation requirement from the at least one memory according to the indication information of the status register of each memory.

7. A distributed system, comprising an application server and a storage node, the storage node comprising a processor and a memory, the memory comprising a processing unit and a storage, wherein:

the application server is used for sending a data processing request to the storage node;

the processor is further used for sending the processed data to the application server;

and the application server is used for receiving the processed data sent by the storage node.

8. A method of processing data, the method being applied to a storage node, the storage node comprising a processor and a memory, the memory comprising a processing unit and a memory, the method comprising:

the processor receives a data processing request sent by an application server, and reads data to a memory of the memory according to the data processing request;

the processor sends at least one instruction to the processing unit, wherein the instruction is used for instructing the processing unit to process the data;

and the processor sends the processed data to the application server.

9. The distributed system of claim 7 or the method of claim 8, wherein each of the instructions contains an address and an operation type at which the data is located in the memory.

10. The distributed system of claim 7 or the method of claim 8, wherein the memory further comprises a memory controller, the memory controller being distinct from the processing unit.

11. The distributed system of claim 7 or the method of claim 8, wherein the memory further comprises a cache for storing the at least one instruction.

12. A computer-readable storage medium, comprising: computer software instructions;

the computer software instructions, when run in a computer device or a chip built into a computer device, cause the computer device to perform the method of any one of claims 8-11.