CN112484867A - Method for improving detection efficiency of single photon detection front-end circuit - Google Patents
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Abstract
The invention discloses a method for improving the detection efficiency of a single photon detection front-end circuit, which comprises the following steps: establishing an initial InP/InGaAs SPAD Verilog-A behavior model; converting the behavior model, loading the behavior model into Matlab for modeling, and setting parameter values to be fitted by the behavior model to obtain fitting curves for simulating the InP/InGaAs SPAD current-voltage characteristic, the dark counting characteristic and the post-pulse noise; adjusting the fitting parameters in Matlab until the fitting curve is matched with the actually measured data of InP/InGaAs SPAD; substituting the corresponding fitting parameter values in the matching state into the initial InP/InGaAs SPAD Verilog-A behavior model to obtain a final behavior model; and applying the final behavior model to the design of the single photon detection front-end circuit, adjusting various parameters and time sequence settings of the front-end circuit, and improving the detection efficiency of the front-end circuit.
Description
Technical Field
The invention relates to the field of single photon detectors, in particular to a method for improving the detection efficiency of a single photon detection front-end circuit.
Background
As an important weak signal detection technology, single photon detection is widely applied to the fields of high-resolution three-dimensional imaging, spectroscopy, quantum information processing and the like. Especially, with the rapid development of quantum secret communication technology, the remote quantum key distribution technology makes a major breakthrough, which makes the single photon detector working in the infrared band increasingly receive attention from people. Because the Single-Photon Avalanche Diode (SPAD) of InGaAs/InP has high detection efficiency in 1310nm and 1550nm communication bands and can work near room temperature, the Single-Photon Avalanche Diode becomes one of typical detectors in the field of Single Photon detection at present.
The InGaAs/InP SPAD operating in the geiger mode has a high electric field in the avalanche multiplication region, and after being triggered by carriers generated by photon absorption or other mechanisms and generating avalanche pulses, a front-end circuit (including a quenching/resetting circuit, a readout circuit, etc.) is required to control, quench the avalanche current, and then restore the SPAD to an over-bias state for the next single photon detection. Because the material system of the InGaAs/InP SPAD detector is incompatible with a silicon-based CMOS readout circuit, in order to accurately simulate the processes of avalanche, quenching, resetting and the like in the circuit design stage, an accurate InGaAs/InP SPAD simulation model is needed to describe the behavior of the InGaAs/InP SPAD detector. In addition to the basic characteristics of static dc and dynamic ac, SPAD is also severely affected by dark counts and post-pulse noise. Therefore, the statistics of dark counts and post-pulses should also be included in the SPAD model.
Early simple SPAD simulation models did not provide sufficient simulation accuracy, so Zappa et al[1]An accurate integrated circuit Simulation Program (SPICE) model is provided, which can simulate the rapid establishment of avalanche current, the self-sustained charge multiplication and the self-quenching process, and can provide more accurate avalanche current for a front-end circuit when being applied to a single-photon detection circuit. Subsequently, Mita R et al[2]The I-V characteristics of the Si-SPAD are described by applying a Verilog-A hardware language, so that the problem of convergence in the SPICE model is solved. However, these models cannot simulate statistical characteristics such as dark count and back pulse, and thus cannot solve the problem of setting dead time of the front-end circuit when applied to a single-photon detection circuit. To this end, Giustosisi et al[3]A Si-SPAD behavior model is proposed for predicting statistical events of dark counts and post-pulses. However, the simulation model only takes dark counts into accountDue to the thermal dependence, the influence of the electric field related tunneling effect is neglected, so that the influence of dark counting noise cannot be considered in the design of a front-end circuit when the single-photon detection circuit is applied. 2017, Yue Xu et al[4]A Si-based SPAD model for simulating a trap-assisted tunneling effect and an interband tunneling effect is provided. In addition, Zheng Lixia proposes an InGaAs/InP SPAD simulation model[5]The model embeds a function representing I-V characteristics in Verilog-A language into Dalla Mora[6]In the proposed enhanced equivalent circuit, functions such as photon absorption and self-quenching can be simulated, but the dark count and the back pulse effect are not considered in the model, so that when the model is applied to the design of a single photon detection front-end circuit, the front-end circuit cannot design proper dead time, the influence of dark count noise is not considered, and the single photon detection efficiency is reduced.
The statistical characteristics of InGaAs/InP SPAD cannot be simulated by the InGaAs/InP single photon detector model, the influence of dark count and back pulse of the InGaAs/InP SPAD on a single photon detection result cannot be well estimated, and therefore when the model is applied to design of a front-end circuit, the designed front-end circuit cannot be matched with the working state of an actual device.
Reference to the literature
[1]F.Zappa,A.Tosi,A.D.Mora,S.Tisa,SPICE modeling of single photon avalanche diodes,Sensors Actuator.Phys.153(2009)197e204.
[2]R.Mita,G.Palumbo,P.G.Fallica,Accurate model for single photon avalanche diodes,IET Circuits,Devices Syst.2(2008)207e212.
[3]G.Giustolisi,R.Mita,G.palumbo,Behavioral modeling of statistical phenomena of single-photon avalanche diodes,Int.J.Circ.Theor.Appl.40(2012)661e679.
[4]Xu Y,Zhao T,Li D.An accurate behavioral model for single-photon avalanche diode statistical performance simulation[J].Superlattices and Microstructures,2017:S0749603617326587.
[5]Zheng L,Tian J,Weng Z,et al.An Improved Convergent Model for Single-Photon Avalanche Diodes[J].IEEE Photonics Technology Letters,2017,29(10):798-801.
[6]Dalla Mora A,Tosi A,Tisa S,et al.Single-Photon Avalanche Diode Model for Circuit Simulations[J].IEEE Photonics Technology Letters,2007,19(23):1922-1924.
Disclosure of Invention
The invention provides a method for improving the detection efficiency of a single photon detection front-end circuit, which can establish the current-voltage characteristic of InGaAs/InP SPAD, the dark counting characteristic caused by various mechanisms of an absorption region and a multiplication region, and the rear pulse noise, and can be applied to design the single photon detection front-end circuit to replace an actual InP/InGaAs single photon detector, provide accurate avalanche current, dead time setting and the influence of the dark counting noise, and is described in detail as follows:
a method for improving detection efficiency of a single photon detection front-end circuit, the method comprising:
establishing an initial InP/InGaAs SPAD Verilog-A behavior model;
converting the behavior model, loading the behavior model into Matlab for modeling, and setting parameter values to be fitted by the behavior model to obtain fitting curves for simulating the InP/InGaAs SPAD current-voltage characteristic, the dark counting characteristic and the post-pulse noise;
adjusting the fitting parameters in Matlab until the fitting curve is matched with the actually measured data of InP/InGaAs SPAD;
substituting the corresponding fitting parameter values in the matching state into the initial InP/InGaAs SPAD Verilog-A behavior model to obtain a final InP/InGaAs SPAD Verilog-A behavior model;
the final InP/InGaAs SPAD Verilog-A behavior model is applied to the design of the single photon detection front-end circuit, various parameters and time sequence setting of the front-end circuit are adjusted, and the detection efficiency of the front-end circuit is improved.
The InP/InGaAs SPAD Verilog-A behavior model specifically comprises the following steps:
at the generation moment of hot carriers in an absorption region, if avalanche is judged not to occur and bias voltage is greater than avalanche breakdown voltage, a random number between 0 and 1 is generated and compared with avalanche trigger probability;
when the random number is greater than the triggering probability, judging avalanche triggering, and updating the time for the next occurrence of current carriers generated by thermal excitation and current carriers in the defects;
and if the bias voltage is smaller than the avalanche breakdown voltage or the random number is smaller than the trigger probability, avalanche does not occur, and the occurrence time of the current carriers generated by next thermal excitation is updated.
Wherein the method further comprises:
the detection unit judges whether the voltage applied by the detector is greater than or equal to the avalanche breakdown voltage, if the voltage is less than the avalanche breakdown voltage, corresponding current is output according to the applied voltage, and the temperature, the voltage and the photon detection unit are returned for re-judgment; if the avalanche breakdown voltage is larger than or equal to the avalanche breakdown voltage, the detector is in a Geiger mode, and the avalanche trigger probability and the electric field intensity of the multiplication region are calculated;
if photons arrive and the detector is in a Geiger mode, judging avalanche triggering and generating a photon counting signal, wherein the signal enters an output photon counting pulse unit to generate a pulse and update the generation time of a dark carrier and a rear pulse; if no photons arrive and are in geiger mode, the absorption zone dark count timer, the multiplication zone dark count timer, and the post pulse timer are triggered.
Further, the method further comprises:
if the detector does not receive a photon arrival signal at the occurrence moment of the dark carriers and is in a Geiger mode, generating a random number which is uniformly distributed by 1-0 and comparing the random number with the avalanche trigger probability;
if the random number is greater than the avalanche trigger probability, triggering the avalanche and generating a dark count signal, entering an output dark count pulse unit to generate a pulse, entering a dark carrier generation time unit and a defect carrier release time unit in the absorption region, and calculating and updating the time of the next occurrence of the dark carriers and the release of the defect carriers; if the random number is less than the avalanche trigger probability, then there is no avalanche trigger.
Wherein the method further comprises:
if the detector does not receive a photon arrival signal at the moment of the occurrence of the dark carriers and is in a Geiger mode, judging whether the number of carriers in the defect is greater than 1, and if the number of carriers in the defect is greater than 1, generating a uniformly distributed random number;
if the random number is greater than the generation probability of the rear pulse, carriers in the defects are interpreted and released, a second random number which is uniformly distributed is generated, and the second random number is compared with the avalanche trigger probability;
if the random number is greater than the avalanche trigger probability, triggering avalanche and generating a dark counting signal, entering a defect carrier release time unit, and calculating and updating the time for releasing the carriers in the next defect;
the generated dark counting signal enters an output dark counting pulse unit to generate a pulse, and then the pulse is judged again; if the number of carriers in the defect is 0, judging again; if the random number is smaller than the occurrence probability of the rear pulse, judging again;
and if the random number is less than the avalanche trigger probability, entering a defect carrier release time unit, calculating and updating the time of the next absorption region, multiplication region and the occurrence of carriers in the defect, and judging again.
The technical scheme provided by the invention has the beneficial effects that:
1. compared with an actual device, the I-V characteristic of the Verilog-A behavior model of the InP/InGaAs single-photon detector constructed by the method has smaller error, and the Verilog-A behavior model can be applied to the design of a single-photon detection front-end circuit, so that the single-photon detection front-end circuit can effectively extract avalanche current which is consistent with the actual device;
2. the method can accurately describe the dark counting characteristic of the InP/InGaAs single-photon detector, simulate the influence of dark counting noise on the front-end circuit, ensure that the working time sequence of the front-end circuit is reasonably designed, and effectively improve the single-photon detection efficiency when the front-end circuit is matched with an actual device;
3. the method can accurately describe the rear pulse noise of the InP/InGaAs single-photon detector, provides accurate dead time setting for the front-end circuit, and can effectively improve the single-photon detection efficiency when the front-end circuit is matched with an actual device;
4. the method adopts Verilog-A for writing, has good universality and compatibility, can be directly connected into a front-end circuit in a commercial simulator (such as Cadence spectrum) to simulate single photon detection, and has higher simulation precision and speed.
Drawings
FIG. 1 is a flow chart of a method of increasing the detection efficiency of a single photon detector;
FIG. 2 is a diagram of an actual InP/InGaAs single-photon detector simulated by a model constructed by the method;
FIG. 3 is a schematic structural diagram of an actual InP/InGaAs single photon detector modeled;
FIG. 4 is a diagram depicting part of the thermal excitation process in the initial InP/InGaAs SPAD Verilog-A behavioral model;
FIG. 5 is a state transition diagram of an initial InP/InGaAs SPAD Verilog-A behavioral model;
FIG. 6 is a schematic diagram of the I-V characteristic curve simulated in Matlab by the InP/InGaAs SPAD Verilog-A behavioral model;
FIG. 7 is a diagram showing a dark count characteristic curve simulated in Matlab by the InP/InGaAs SPAD Verilog-A behavioral model;
FIG. 8 is a schematic diagram of the application of the final InP/InGaAs SPAD Verilog-A behavioral model constructed by the present invention to the design of the front-end circuit in Cadence Spectre;
FIG. 9 is a diagram showing the simulation result of applying the final InP/InGaAs SPAD Verilog-A behavioral model constructed by the present invention to the front-end circuit design in Cadence Spectre.
FIG. 10 is a graph showing the total dark count rate of a single photon detector as a function of the period of the gate pulse at a temperature of 225K, a gate voltage pulse width of 20ns and a high level of 5V and 3V, respectively.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below.
Example 1
The invention provides a method for improving the detection efficiency of a single photon detection front-end circuit, which comprises the following steps:
step 1: establishing an initial InP/InGaAs SPAD Verilog-A behavior model;
step 2: converting the behavior model, loading the behavior model into Matlab for modeling, and setting parameter values to be fitted by the behavior model to obtain fitting curves for simulating the current-voltage characteristic, the dark counting characteristic and the post-pulse noise of the InP/InGaAs SPAD;
and step 3: directly adjusting the fitting parameters in Matlab until the fitting curve is matched with the actually measured data of InP/InGaAs SPAD;
and 4, step 4: substituting the corresponding fitting parameter values in the matching state into the initial InP/InGaAs SPAD Verilog-A behavior model to obtain a final InP/InGaAs SPAD Verilog-A behavior model;
and 5: the final InP/InGaAs SPAD Verilog-A behavior model is applied to the design of the single photon detection front-end circuit, various parameters and time sequence setting of the front-end circuit are adjusted, and the detection efficiency of the front-end circuit is improved.
Example 2
The scheme of example 1 is further described below in conjunction with fig. 1-10, and is described in detail below:
FIG. 1 is a flow chart of a method for constructing a Verilog-A behavior model of a single-photon detector, FIG. 2 shows an actual InP/InGaAs single-photon detector simulated by the constructed model, and FIG. 3 is a schematic structural diagram of the actual InP/InGaAs single-photon detector simulated by the model;
the electric field of the multiplication layer must be high enough to guarantee avalanche probability, and the electric field of the absorption layer must be low enough to avoid field induced leakage current. The highly doped charge layer is used to improve the electric field distribution of the absorption layer and the multiplication layer. The gradual change region is mainly used for buffering the sudden change of forbidden bands of InGaAs and InP and reducing the accumulative effect of photon-generated carriers at an interface. In the geiger mode, the SPAD operates above the avalanche breakdown bias. Incident photons are absorbed by the InGaAs layer with the narrow forbidden band to generate electron-hole pairs, the electron-hole pairs are separated under the action of reverse bias, holes enter the InP multiplication layer with the wide forbidden band, impact ionization is carried out under the action of a high electric field, self-sustaining avalanche is generated, and carrier generation and release of defect carriers in the absorption region and the multiplication region can trigger avalanche to cause dark counting. During single photon detection, the functions required to be executed by the InGaAs/InP SPAD are as follows: calculating avalanche voltage and avalanche trigger probability according to the temperature and the applied voltage and outputting correct current; photon counting can be generated when photons come under a Geiger mode; the absence of photons in geiger mode produces dark counts caused by thermally generated carriers in the absorption region; no photon arrives to generate dark counts caused by trap-assisted tunneling of the multiplication region in a Geiger mode; no photon arrives to generate a back pulse caused by releasing a defect carrier in a Geiger mode; quenching and resetting can be completed under the cooperation of the readout circuit.
In combination with the structure diagram and the working principle of the InGaAs/InP SPAD shown in fig. 3, it is necessary to construct single photon detection behaviors of analog detectors with different units. The temperature, voltage and photon detection unit is used for judging whether the Geiger mode is adopted or not and whether photons come or not and outputting corresponding current. The absorption region dark carrier generation time cell is used to simulate the dark counting process caused by heat generated carriers of the absorption region of the detector. The multiplication region dark carrier generation time cell is used to simulate the dark counting process caused by trap-assisted tunneling of the multiplication region of the detector. The defect carrier release time unit is used for simulating the process of a post pulse caused by the release of the defect carriers.
FIG. 4 is a section of the initial InP/InGaAs SPAD Verilog-A behavioral model describing the thermal excitation process, the code functions as follows: at the generation moment of hot carriers in the absorption region, if avalanche is judged not to occur and the bias voltage is larger than avalanche breakdown voltage, a random number between 0 and 1 is generated to be compared with avalanche trigger probability, and when the random number is larger than the trigger probability, avalanche trigger is judged, and the time for the next occurrence of carriers in the carriers generated by thermal trigger and defects is updated; and if the bias voltage is smaller than the avalanche breakdown voltage or the random number is smaller than the trigger probability, avalanche does not occur, and the occurrence time of the current carriers generated by next thermal excitation is updated.
In order to describe the initial InP/InGaAs SPAD Verilog-A behavior model conveniently, FIG. 5 shows the state transition diagram of the initial InP/InGaAs SPAD Verilog-A behavior model constructed by the present invention. Inputting the voltage and the temperature into a temperature, voltage and photon detection unit, calculating and judging whether the voltage applied by the detector is greater than or equal to the avalanche breakdown voltage by the unit, if the voltage is less than the avalanche breakdown voltage, outputting corresponding current according to the applied voltage, and returning to the temperature, voltage and photon detection unit for re-judgment; and if the avalanche breakdown voltage is larger than or equal to the avalanche breakdown voltage, the detector is in a Geiger mode, and the avalanche trigger probability and the electric field intensity of the multiplication region are calculated. Inputting photon signals into a temperature, voltage and photon detection unit, judging avalanche triggering and generating photon counting signals if photons come and a detector is in a Geiger mode, enabling the signals to enter an output photon counting pulse unit, generating pulses and updating dark carriers and the generation time of the rear pulses; if no photons arrive and are in geiger mode, the absorption zone dark count timer, the multiplication zone dark count timer, and the post pulse timer are triggered.
The time for generating the dark carriers in the absorption region of the InGaAs/InP single photon detector is scheduled by the dark carrier generation time unit in the absorption region. If the detector does not receive the incoming photon signal at the time of occurrence of the dark carriers and is in the geiger mode, a random number with 1-0 uniform distribution is generated and compared with the avalanche trigger probability. If the random number is greater than the avalanche trigger probability, avalanche is triggered and a dark count signal is generated. The generated dark counting signal enters an output dark counting pulse unit to generate a pulse, enters a dark carrier generation time unit and a defect carrier release time unit in an absorption region, calculates and updates the time for the next occurrence of dark carriers and the release of the defect carriers, and returns to a temperature, voltage and photon detection unit; if the random number is less than the avalanche trigger probability, no avalanche trigger exists, and the temperature, voltage and photon detection unit returns.
The time for generating the dark carriers in the multiplication region of the InGaAs/InP single photon detector is scheduled by a multiplication region dark carrier generation time unit. If the detector does not receive the incoming photon signal and is in the geiger mode at the time of occurrence of the dark carriers, a uniformly distributed random number is generated and compared with the avalanche trigger probability. If the random number is greater than the avalanche trigger probability, triggering the avalanche and generating a dark counting signal, enabling the generated dark counting signal to enter an output dark counting pulse unit to generate a pulse, then entering a multiplication region dark carrier generation time unit and a defect carrier release time unit, calculating and updating the time of next dark carrier occurrence and defect carrier release, and returning to a temperature, voltage and photon detection unit; if the random number is less than the avalanche trigger probability, returning to the temperature, voltage and photon detection unit.
The time of the defect carrier induced back pulse of the InGaAs/InP single photon detector is scheduled by a defect carrier release time unit. And if the detector does not receive the photon arrival signal at the time of the occurrence of the dark carriers and is in a Geiger mode, judging whether the number of carriers in the defect is greater than 1, and if the number of carriers in the defect is greater than 1, generating a uniformly distributed random number and comparing the random number with the generation probability of the post pulse. If the random number is greater than the generation probability of the back pulse, carriers in the defect are interpreted and released, a second random number which is uniformly distributed is generated, and the second random number is compared with the avalanche trigger probability. If the random number is larger than the avalanche trigger probability, triggering avalanche and generating a dark counting signal, entering a defect carrier release time unit, and calculating and updating the time for releasing the carriers in the next defect. The generated dark counting signal enters an output dark counting pulse unit to generate a pulse, and then enters a temperature, voltage and photon detection unit to judge again; if the number of the carriers in the defect is 0, returning to the temperature, voltage and photon detection unit for judging again; if the random number is smaller than the rear pulse occurrence probability, returning to the temperature, voltage and photon detection unit for judging again; and if the random number is less than the avalanche trigger probability, entering a defect carrier release time unit, calculating and updating the time of the next occurrence of carriers in the absorption region, the multiplication region and the defect, and returning to the temperature, voltage and photon detection unit for judging again.
FIG. 6 shows the I-V characteristic curve of the InP/InGaAs SPAD Verilog-A behavior model constructed by the invention in Matlab, the I-V characteristic curve is simulated under 225K, and the avalanche breakdown voltage of the InP/InGaAs SPAD is 45V.
FIG. 7 shows the simulated dark count characteristic curve of the InP/InGaAs SPAD Verilog-A behavior model in Matlab, which simulates the change of dark count rate of the model with temperature under the condition of a bias voltage of 47V. At low temperatures, the release of carriers from defects and the noise of the multiplication region are the main effects of dark counts, and as the temperature increases, the noise of the absorption region is the main cause of dark counts.
FIG. 8 shows a schematic diagram of the application of the final InP/InGaAs SPAD Verilog-A behavioral model constructed by the present invention to the design of the front-end circuit in Cadence Spectre. The circuit can complete single photon detection, reduce the influence of dark counting and rear pulse noise through time sequence adjustment, and improve the single photon detection efficiency. The InGaAs/InP single photon detector has three input and output ends, namely a photon incidence end, a cathode and an anode; the bias voltage was set to 44V; bias resistor RSA value of 1K Ω; induction resistance RLSet to 100K Ω; the capacitance C was 500 pf. The pulse width of the gate voltage is set to 20ns, and the period is adjustable.
The working principle of the circuit is as follows: for optimal gating period, the photon input terminal is grounded, which means that no photons are incident, so that the influence of the gating period on the dark count can be directly obtained. The bias voltage is loaded on the cathode of the single photon detector to provide a basic voltage which is less than the avalanche breakdown voltage. The gate control voltage is loaded on the cathode of the single photon detector to provide extra voltage, and the voltage at two ends of the single photon detector is larger than the avalanche breakdown voltage at high level. When the gate control pulse is at a low level, the voltage applied to two ends of the single-photon detector is smaller than the avalanche breakdown voltage, the single-photon detector cannot trigger avalanche generation, and no dark count is generated; when the gate control pulse is at high level, the cathode voltage of the single photon detector is controlled by a capacitor C and a bias resistor RSProvided that a voltage applied across the single-photon detector within the gate-controlled pulse width is larger than an avalanche breakdown voltage, and when an avalanche is triggered, an avalanche current flows through the sense resistor RLAnd generating an induced voltage, outputting the induced voltage through the cathode of the single photon detector, reducing the voltage of two ends of the single photon detector to a bias voltage along with the increase of the induced voltage, wherein the bias voltage is less than the avalanche breakdown voltage, completing the detection of the dark carrier pulse and waiting for the next detection. The influence of the rear pulse can be effectively reduced through the modulation of the gating period, and the detection efficiency of the front-end circuit is improved.
FIG. 9 shows a simulation result diagram of the application of the final InP/InGaAs SPAD Verilog-A behavioral model constructed by the invention in Cadence Spectre to the front-end circuit design. The gate pulse has a period of 1 μ s, a width of 20ns, and a high level of 3V. The abscissa is simulation time, and 2 ordinates gate the pulse voltage signal and the voltage signal of the anode node of the detector respectively from top to bottom. As shown in the figure, when the gate control pulse is at a high level, if a dark carrier is generated in the single photon detection and triggers avalanche, avalanche current flows through the induction resistor, voltage at two ends of the single photon detection is reduced due to the voltage division of the resistor, the current is reduced, and the single photon detector is quenched. The resistive voltage divider is also decreased again as the current is decreased until the reset is completed. When the gating pulse is low, it cannot be detected. Dark counts were detected at 15 μ s, 18 μ s, respectively.
FIG. 10 is a graph showing the total dark count rate of a single photon detector as a function of the period of the gate pulse at a temperature of 225K, a gate voltage pulse width of 20ns and a high level of 5V and 3V, respectively. It can be seen that at gate cycles less than 10 μ s, the total dark count rate decreases faster as the gate cycle increases; at gate periods greater than 10 μ s, the total dark count does not change significantly as the gate period increases. By integrating the above, when the gating period is set to 10 μ s, a small dark count can be obtained, and by integrating the small dark count and the large gate opening time of the front-end circuit, the detection efficiency can be effectively improved, and a better time sequence setting can be obtained.
In summary, the InP/InGaAs SPAD Verilog-a behavioral model constructed by the invention simulates the static dc characteristic and the dynamic ac characteristic of InGaAs/InP SPAD, and can describe the back pulse noise of the detector and the dark count characteristics of the absorption region and the multiplication region.
In the embodiment of the present invention, except for the specific description of the model of each device, the model of other devices is not limited, as long as the device can perform the above functions.
Those skilled in the art will appreciate that the drawings are only schematic illustrations of preferred embodiments, and the above-described embodiments of the present invention are merely provided for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
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