CN112470225A

CN112470225A - Programming and read biasing and access schemes to improve data throughput of 2-stack 3D PCM memories

Info

Publication number: CN112470225A
Application number: CN202080003147.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2021-03-09
Anticipated expiration: 2040-10-23
Also published as: WO2022082732A1; CN112470225B

Abstract

A method for accessing memory cells of a three-dimensional memory including a plurality of bottom cell blocks, a plurality of top cell blocks, a plurality of bottom cell bitlines coupled to the bottom cell blocks, a plurality of top cell bitlines coupled to the top cell blocks, and a plurality of wordlines coupled to each of the bottom cell blocks below the wordlines and the top cell blocks above the wordlines. The method includes accessing memory cells of a bottom cell block and memory cells of a top cell block at a time by biasing one word line, one of the bottom cell bit lines, and one of the top cell bit lines.

Description

Programming and read biasing and access schemes to improve data throughput of 2-stack 3D PCM memories

Technical Field

The present disclosure relates generally to three-dimensional electronic memories, and more particularly to improving the throughput of memory cell access schemes in three-dimensional cross-point memories.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of memory cells approaches the lower limit, planarization and fabrication techniques become more difficult and more costly. Thus, the storage density of the planar memory cell approaches the upper limit. A three-dimensional (3D) storage architecture can address density limitations in planar storage cells, and a biasing scheme for accessing storage cells of the three-dimensional (3D) storage architecture can address throughput limitations of the three-dimensional (3D) storage architecture.

Disclosure of Invention

The disclosed three-dimensional memory and biasing scheme solves the problems of the prior art and provides further benefits. According to one aspect, a distributed array and CMOS (complementary metal oxide semiconductor) architecture for 3D X-Point memory is disclosed and illustrated. The Word Line (WL) and Bit Line (BL) decoders of each memory slice (memory tile) are broken up into parts and arranged in a distributed pattern. The centers of the WL and BL decoder regions are connected to the centers of the word lines and bit lines. The TCBL (top cell bit line) blocks are offset by half blocks to interface with CMOS TCBL decoders between BCBL (bottom cell bit line) blocks. The BCBL blocks, TCBL blocks, and BCWL (bottom cell word line) blocks are offset to maximize area utilization. The selected WL and selected BL may be biased to read or program cells located at the intersection between the selected WL and BL, thereby accessing each of the BCBL block and TCBL block one cell at a time. Thus, array efficiency is greatly improved over prior art systems.

In another aspect, a method for accessing memory cells of a three-dimensional memory is provided. The method can comprise the following steps: accessing memory cells of a first bottom cell block of the bottom cell array and memory cells of a first top cell block of the top cell array above the bottom cell array by biasing one of the first portion of word lines, one of the first portion of bottom cell bit lines, and one of the first portion of top cell bit lines; and accessing memory cells of a second bottom cell block of the bottom cell array that is offset from the first bottom cell block and memory cells of a second top cell block of the top cell array that is offset from the first top cell block by biasing one of the second portion of word lines, one of the second portion of bottom cell bit lines, and one of the second portion of top cell bit lines.

In some examples, memory cells of a first bottom cell block and a first top cell block may be accessed simultaneously, and memory cells of a second bottom cell block and a second top cell block may be accessed simultaneously.

In some examples, accessing at least one cell of a block of cells may include increasing a voltage of a word line coupled to the at least one cell above a first threshold and decreasing a voltage of a bit line coupled to the at least one cell below a second threshold.

In some examples, the first threshold may be between about 5 and 20V, and the second threshold may be between about-20 and-5V.

In some examples, each unbiased word line may have a voltage of approximately 2V, and wherein each unbiased bit line may have a voltage of approximately 2V.

In some examples, accessing at least one cell of a memory block may include maintaining a voltage of each unbiased word line coupled to the memory block at a first unbiased voltage value and maintaining a voltage of each unbiased bit line coupled to the memory block at a second unbiased voltage value.

In some examples, the first unbiased voltage value may be about 2V, and wherein the second unbiased voltage value may be about 2V.

In some examples, each unbiased word line may have a voltage of approximately 0V, and wherein each unbiased bit line may have a voltage of approximately 0V.

In some examples, accessing the memory cell may include at least one of reading data from the memory cell or programming data to the memory cell.

In some examples, the three-dimensional memory may include a plurality of pages, each page may include a plurality of memory blocks, and accessing the memory cells of a given page of the three-dimensional memory may include accessing two memory cells of each memory block at a time.

In some examples, each page may include 128 memory blocks, and accessing memory cells of a given page may be performed at a rate of 256 memory cells at a time.

In yet another aspect, the method may include: performing one-cell-at-a-time access to memory cells of a bottom cell block of the bottom cell array by biasing one of the plurality of word lines and one of the plurality of bottom cell bit lines; and performing one-cell-at-a-time access to memory cells of a top cell block of the top cell array that is offset from the bottom cell block and is located above the bottom cell array in the depth direction, by biasing one of the plurality of word lines and one of the plurality of top cell bit lines. The first memory cell of the bottom cell block and the second memory cell of the top cell block above the first memory cell may be simultaneously accessed by biasing word lines of the plurality of word lines connected to both the first memory cell and the second memory cell.

In some examples, biasing one of the plurality of word lines may include increasing a voltage of the one word line above a first threshold.

In some examples, biasing one of the plurality of word lines may include maintaining voltages of a plurality of word lines other than the one word line at an unbiased word line voltage value.

In some examples, biasing the first bit line of the plurality of bottom cell bit lines and the second bit line of the plurality of top cell bit lines may include dropping voltages of the first bit line and the second bit line below a second threshold.

In some examples, biasing the first bit line of the plurality of bottom cell bit lines and the second bit line of the plurality of top cell bit lines includes maintaining voltages of the plurality of bottom cell bit lines and the plurality of top cell bit lines, other than the first bit line and the second bit line, at an unbiased bit line voltage value.

In some examples, the bottom cell block is located below the plurality of word lines in the depth direction, and the top cell block is located above the plurality of word lines in the depth direction.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure, specific terminology may be employed for the sake of clarity. However, there is no intention that aspects of the disclosure be limited to the specific terminology used.

Fig. 1 is an isometric view of a section of a three-dimensional cross-point memory.

Fig. 2 is a plan view of a sector of a conventional three-dimensional cross-point memory.

Fig. 3A and 3B are plan views of sections of a conventional three-dimensional cross-point memory.

Fig. 3C is a plan view of another section of a conventional three-dimensional cross-point memory.

Fig. 3D is a block diagram representation of a portion of a section of the prior art three-dimensional cross-point memory of fig. 3C.

Fig. 4 is a plan view of a section of a three-dimensional cross-point memory according to an embodiment.

Fig. 5A is another plan view of a section of a three-dimensional cross-point memory according to an embodiment.

FIG. 5B is a side view along the Y-Y axis of a section of a three-dimensional cross-point memory according to the embodiment of FIG. 5A.

FIG. 5C is a side view along the X-X axis of a section of a three-dimensional cross-point memory according to the embodiment of FIG. 5A.

Figure 6A is a plan view of a section of the three-dimensional cross-point memory of figure 5A illustrating a biasing scheme, according to an embodiment.

FIG. 6B is a side view along the Y-Y axis of a section of a three-dimensional cross-point memory according to the embodiment of FIG. 6A.

FIG. 6C is a side view along the X-X axis of a section of a three-dimensional cross-point memory according to the embodiment of FIG. 6A.

Detailed Description

The technology is applied to the field of three-dimensional memories. Fig. 1 shows a generalized example of a three-dimensional (3D) memory. Specifically, fig. 1 is an isometric view of a section of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first level memory cells 5 and the second level memory cells are a number of word lines 15 extending in the horizontal or X direction. Above the first level memory cells 5 are a number of first bit lines 20 extending in the vertical or Y direction, and below the second level memory cells are a number of second bit lines 25 extending in the Y direction.

Further, as shown in fig. 1, the sequential structure of bit lines, memory cells, word lines, memory cells may be repeated in the Z-direction to create a stacked configuration. In the example of fig. 1, a first layer of the stack may include first layer memory cells 5, bit lines 20, and word lines 15, and a second layer of the stack may include second layer memory cells 10, bit lines 25, and word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their corresponding set of

bit lines

20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 shows a 4-layer stack configuration, in other examples, the stack configuration may include any number of memory cell layers and other elements. In any case, individual memory cells in the structure can be accessed by selectively activating the word lines and bit lines corresponding to the cells.

To selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown). The word line decoder is coupled to the word lines through word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode the bit line address so that a particular bit line is activated when addressed. Thus, the stack configuration of the memory may further include bit line contacts and decoders and word line contacts and decoders to selectively activate bit lines and word lines within the stack. For example, the stack may be configured as an array of elements in each stacked layer, wherein each array includes a group of memory cells and corresponding groups of bit lines, word lines, bit line contacts and word line contacts, and bit line decoders and word line decoders.

Fig. 2 is a plan view of a section of a three-dimensional cross-point memory having a prior configuration. The figure depicts the segments as seen in the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes a plurality of memory cell arrays, including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in fig. 2, fig. 1 illustrates this, for example, in a top array, the memory cells may be arranged as the first tier memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as the second tier memory cells 10 shown in fig. 1.

The segment includes word and bit lines, word and bit line contacts, and word and bit line decoders corresponding to the top and bottom cells. As shown, several word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to both the top and bottom cells. The segment further includes a number of top cell bit lines (e.g., bit line 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a number of bottom cell bit lines (e.g., bit line 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed in a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are horizontally aligned for a given cell array. For example, as shown, the word lines for the

cell arrays

60, 61, 65, and 66 are all horizontally aligned with one another and are not offset from one another in the X direction. Each of these word lines is shown as extending across the entire width of the respective cell array. The top cell bit lines for a given top cell array or the bottom cell bit lines for a given bottom cell array are vertically aligned with each other and are not offset from each other in the vertical or Y-direction. For example, the top cell bit line 35 is vertically aligned along the Y-direction, and the bottom cell bit line 40 is vertically aligned along the Y-direction. The top cell bit line of the top cell array and the bottom cell bit line of the overlapping bottom cell array (such as top cell bit line 35 and bottom cell bit line 40) are also vertically aligned with each other and are not offset from each other in the vertical or Y-direction, although they are shown slightly offset in fig. 2 in order to clearly illustrate these two layers. Each of these bit lines is shown extending across the entire length of the respective cell array.

The memory segment of fig. 2 also includes a word line contact region 45, a top cell bit line contact region 50, and a bottom cell bit line contact region 55. The word line contact region 45 is elongated in the vertical direction, while the top cell bit line contact region 50 and the bottom cell contact region 55 are elongated in the horizontal direction. The word line contact region 45 includes a plurality of word line contacts (e.g., contacts 45a), which are shown as dots that are enclosed by the word line contact region 45. The top cell bit line contact region 50 includes a plurality of top cell bit line contacts (e.g., contacts 50a), which are shown as points that are encased by the top cell bit line contact region 50. The bottom cell bit line contact region 55 includes a plurality of bottom cell bit line contacts (e.g., contacts 55a), which are shown as dots that are encased by the bottom cell bit line contact region 55.

The word line contact and the bit line contact are connected to the middle of the corresponding word line and the corresponding bit line. Thus, as shown, word line contact region 45 is located in the horizontal center of word line 40, bottom cell bit line contact region 55 is located in the vertical center of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical center of top cell bit line 35. Since the word lines of a given cell array extend horizontally lengthwise in the X-direction and are aligned with each other such that no word line is offset from other word lines, the word line contacts may form substantially straight lines in the vertical or Y-direction such that they are aligned with each other and not horizontally offset from each other. Similarly, since the bit lines of a given cell array extend vertically in the Y-direction and are substantially aligned with each other such that substantially no bit line is offset relative to other bit lines, the bit line contacts form substantially straight lines in the horizontal or X-direction such that they are aligned with each other and vertically not offset from each other.

The word line contact region 45 also includes a plurality of word line decoders (not shown). The word line decoder is generally coincident with the word line contact area and extends generally in a vertical direction. A word line decoder is coupled to the word line at a word line contact. The top cell bit line contact region 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally coincides with the top cell bit line contact region 50 and generally extends in a horizontal direction. A top cell bit line decoder is coupled to the top cell bit line at a top cell bit line contact. The bottom cell bit line contact region 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally coincides with the bottom cell bit line contact area 55 and generally extends in a horizontal direction. A bottom cell bit line decoder is coupled to the bottom cell bit line at a bottom cell bit line contact.

The configuration illustrated in fig. 2 is inefficient in its use of storage area (or "storage footprint"). This defect is mainly due to the arrangement of the word line decoder. As can be seen from fig. 2, the word line contact regions 45 and accordingly the word line contacts and word line decoders are arranged to the horizontal center of the memory structure. For example, as shown, the word line contacts 45 and word line decoders are arranged along the horizontal centers of the top memory cell array 60 and the bottom memory cell array 65 (but at different depths in the Z-direction). This is also true for other arrays within the memory, such as the top cell array 61 and the bottom cell array 66, where the word line contact area also occupies the center of these arrays. The decoder is so arranged because the word lines are horizontally aligned and the bit lines are vertically aligned as described above.

Fig. 3A is a plan view of a sector of a conventional three-dimensional cross-point memory. The figure depicts the segments as seen in the depth or Z direction. This example is a 2-layer stack configuration. The figure shows a plurality of bottom cell arrays, including a bottom cell array 60 extending from a first or top edge 75 to a second or bottom edge 80; and a plurality of top cell arrays including a top cell array 65 extending from a first or top edge 76 to a second or bottom edge 81. Fig. 3B is the same plan view as fig. 3A except that the marks representing the bottom cell array 60 and the top cell array 65 have been removed. For clarity of presentation, fig. 3A and 3B will be discussed in relation to only those portions belonging to the bottom cell array 60 and the top cell array 65, at which point it will be understood that such discussion can readily be applied to other portions of the figure. Further, it should be noted that the figures only show the word line decoder, the top cell bit line decoder, and the bottom cell bit line decoder, while other portions of the memory are not shown.

Referring to fig. 3A and 3B, it can be seen that the memory segment includes a set of word line decoders 70 arranged in a continuous vertical stripe from a top edge 75 of the bottom cell array 60 to a bottom edge 80 of the bottom cell array 60. The word line decoder 70 extends generally in the vertical or Y direction, coinciding with the word line contact regions 45 shown in fig. 2. The memory section also includes a set of top cell bit line decoders 85 of the top cell array 65, which are divided into two vertically aligned

sections

85a and 85b along the horizontal or X direction; and a set of bottom cell bit line decoders 90 of the bottom cell array 60 that are divided into two vertically aligned

sections

90a and 90b along the horizontal or X direction. Top cell bit line decoder 85 and bottom cell bit line decoder 90 extend generally in the horizontal or X direction, coinciding with top cell bit line contact region 50 and bottom cell bit line contact region 55, respectively, as shown in fig. 2.

As shown in fig. 3A and 3B, the bit line decoder and the word line decoder are symmetrically arranged in the memory structure. This is because, as described in connection with fig. 2, the word lines are horizontally aligned and the bit lines are vertically aligned. Thus, this prior configuration shown in fig. 3A and 3B dedicates vertical stripes of storage areas to word line contacts and word line decoders that do not include any bit lines or memory cells for data storage, thereby limiting the efficiency of the memory.

Fig. 3C is a plan view of another section of a conventional three-dimensional cross-point memory. The figure depicts the segments as seen in the depth or Z direction. The figure shows a plurality of pages of memory. In particular, the plan view in FIG. 3C shows sixteen pages of memory, including a first page 310 at a first end of the illustrated portion of memory and a sixteenth page 320 at an opposite second end of the illustrated portion of memory. The pages are arranged in strips extending parallel to each other.

FIG. 3D illustrates a block diagram of components included in the first page 310 of the memory of FIG. 3C. Included in page 310 are control circuitry 312 for reading and programming the memory cells of page 310, and a plurality of memory blocks 314. The representation in FIG. 3D also shows bits 316 read from memory block 314 or programmed into memory block 314. In the example of FIG. 3D, page 310 is shown to include enough control circuitry 312 to access 128 blocks simultaneously. At each block 314, only a single memory location can be accessed at a time. This limits the access size of a single page to 128 bits (or 16 bytes), thereby enabling 128 bits to be read from or programmed to the page at a time.

Although 128-bit access sizes are suitable for many applications, the demand for higher access sizes is increasing. For example, an access size of 256 bits (or 32 bytes) is generally preferred in server applications. Therefore, it would be advantageous if more data could be read from or programmed to the memory at one time.

Fig. 4 is a plan view of an exemplary section of a three-dimensional crosspoint memory according to an embodiment. The figure depicts the segments as seen in the depth or Z direction. The section in fig. 4 shows a plurality of columns of unit blocks. In the example of fig. 4, a portion of the first column of cell blocks 410 is shown to include a pair of bottom cell blocks 412, 414 and a pair of

top cell blocks

416, 418. The bottom cell block is offset in the vertical or Y direction relative to the top cell block such that the first bottom cell block 412 is partially underneath the first top cell block 416 and such that the second bottom cell block 414 is partially underneath each of the first top cell block 416 and the second top cell block 418. The overlap between the top and bottom cell blocks may be repeated in the vertical or Y direction such that additional cell blocks are included in the column of cell blocks. Further, the pattern of columns of unit blocks may be repeated in one or more other columns at positions adjacent to the first column of unit blocks. In the example of fig. 4, a portion of the second column of cell blocks 420 is shown to include a pair of bottom cell blocks 422, 424 and a pair of

top cell blocks

426, 428. Like the first column cell block 410, the top and bottom cell blocks of the second column 420 are offset from each other.

Additionally, the word line decoder and bit line decoder for each bottom cell block and top cell block of the exemplary configuration are broken down into separate and offset portions as shown. Taking the top cell block 416 of the first column 410 of fig. 4 as an example, the top cell block 416 includes a word line decoder having a first portion 432 and a second portion 434, and the top cell block 426 includes a word line decoder having a third portion 436 and a fourth portion 438. The first and second portions 432, 434 may be horizontally aligned with each other, and the third and fourth portions 436, 438 may be horizontally aligned with each other, but horizontally offset from the first and second portions 432, 434 in the X-direction.

Offsetting the portions of the word line decoder may allow each portion to be connected to the center of a corresponding plurality of word lines. In the example of fig. 4, the first portion 432 of the word line decoder is placed at a midpoint of the first plurality of word lines 442, the second portion 434 of the word line decoder is placed at a midpoint of the second plurality of word lines 444, the third portion 436 of the word line decoder is placed at a midpoint of the third plurality of word lines 446, and the fourth portion 438 of the word line decoder is placed at a midpoint of the fourth plurality of word lines 448. The word lines may extend parallel to each other in the horizontal or X direction, and each plurality of word lines may be offset from its immediately adjacent plurality of word lines such that the midpoints of each plurality of word lines are aligned with the midpoints of their corresponding word line decoders (similarly spaced in the horizontal or X direction as explained above).

In the example of fig. 4, the cell blocks may be combined to form a cell array. For example, the

bottom cell blocks

412 and 422 may be considered as the bottom cell array 452, such that the individual blocks of the bottom cell array 452 are offset from each other in the vertical or Y direction. Similarly,

top cell blocks

418 and 428 may be considered top cell array 458, whereby the individual blocks of top cell array 458 are offset from each other in the vertical or Y-direction.

Fig. 5A is a plan view of a section of a three-dimensional cross-point memory according to an embodiment. The figure depicts the segments as seen in the depth or Z direction. The embodiment of fig. 5A includes features comparable to those described in connection with the embodiment of fig. 4. For example, the memory cells, word lines, bit lines, word line contacts and bit line contacts, and word line decoders and bit line decoders in each array in FIG. 5A may be arranged in a similar manner as described in connection with FIG. 4. FIG. 5A is provided to illustrate word line contacts and bit line contacts to the word line and bit line. Thus, there is highlighted a bottom cell array 500, which may be configured similarly to the arrays of fig. 4 (e.g., bottom cell array 452 and top cell array 456 discussed in detail in connection with fig. 4). As shown, the bottom cell array 500 is divided into two

subsections

500a and 500 b. A first portion of bottom cell bit lines 510a extends along the length of sub-segment 500a and a second portion of bottom cell bit lines 510b extends along the length of sub-segment 500 b. A first set of bottom cell bit line contacts 520a is provided in the vertical center of the first portion of bottom cell bit lines 510a and a second set of bottom cell bit line contacts 520b is provided in the vertical center of the second portion of bottom cell bit lines 510 b.

The two

subsections

500a and 500b are offset from each other, for example, by a predetermined length in the vertical or Y direction as shown. Similarly, the first portion of bottom cell bit lines 510a and the second portion of bottom cell bit lines 510b also have a vertical offset with respect to each other. Since the bit line contacts are located at the center of the bit lines, the first set of bottom cell bit line contacts 520a and the second set of bottom cell bit line contacts 520b also have an offset from each other in the vertical or Y-direction.

Above the first set of bottom cell bitline contacts 520a, a first portion of wordlines 530a extend from a first horizontally adjacent cell through sub-segment 500a into a second sub-segment 500 b. A first set of word line contacts 540a is provided along the center of the first portion of word lines 530a to couple the first portion of word lines 530a to a first set of word line decoders (not shown). Below the first set of bottom cell bit line contacts 530a, a second portion of word lines 540b also extend from the first horizontally adjacent cell through sub-segment 510a into the second sub-segment 510 b. A second set of word line contacts 540b is provided along the center of the second portion of word lines 530b to couple the second portion of word lines 530b to a second set of word line decoders (not shown).

Above the bottom cell bit line contact 520b, a third portion of word lines 530c extends from the sub-segment 500a through the second sub-segment 500b into the area of a second horizontally adjacent cell. A third set of word line contacts 540c is provided along the center of the third portion of word lines 530c to couple the third portion of word lines 530c to a third set of word line decoders (not shown). Below the second set of bottom cell bit line contacts 520b, a fourth portion of word lines 530d extend from the sub-segment 500a through the second sub-segment 500b into the area of a second horizontally adjacent cell. A fourth set of word line contacts 530d is provided along the center of the fourth portion of word lines 530d to couple the fourth portion of word lines 530d to a fourth set of word line decoders (not shown). The word line decoder (although not shown) may be located substantially in the same region as the word line contacts. Similarly, the bit line decoder (although not shown) may be located substantially within the same area as the word line contacts.

By introducing an offset between a word line and a bit line, an offset is also introduced to the corresponding word line contact, bit line contact, word line decoder, and bit line decoder. Due to the distributed positioning of these elements, the bit lines can occupy an area that overlaps with the word line contacts. Although fig. 5A seems to show that the bit lines do not overlap with the regions for word line contacts, this is because the illustration is convenient to show a large space.

FIG. 5B is a cross-sectional view of a section of the three-dimensional cross-point memory of FIG. 5A along the vertical or Y direction at the Y-Y axis shown in FIG. 5A. The bottom cell array 500 includes a first level of memory cells 560. Bit lines and bit line contacts are provided below the first level memory cells 560. For example, two portions of bottom cell bitlines (visible only from 510a in this cross-sectional view) may be provided, and two sets of bottom cell bitline contacts (visible only from 520a in this cross-sectional view) may be provided. Word lines and word line contacts are provided above the first level of memory cells 560. For example, four portions of word lines may be provided, with only two

portions

530a and 530b being visible from the illustration, and four sets of word line contacts may be provided, with only two

sets

540a and 540b being visible from the illustration. Thus, the bottom cell bit line and the bottom cell memory cell are provided in a region overlapping with a region in contact with the word line.

Fig. 5B further illustrates a top array of cells 550 partially overlapping the bottom array of cells 510. The top cell array 550 includes a second layer of memory cells 570. Above the second tier of memory cells 570, two portions of top cell bit lines (only 560a visible) may be provided, and two sets of top cell bit line contacts (only 570a visible) may be provided. Below the second level memory cells 570, word lines and word line contacts are provided, some of which may be shared with the bottom cell array 500. For example, the top cell array 550 may include four portions of word lines (of which only two

portions

580a and 530a are visible from this illustration) and four sets of word line contacts (of which only 540a is visible from this illustration). Thus, the top cell bit line and the top cell memory cell are provided in a region overlapping with a region in contact with the word line. Although not shown, the word line decoder and the bit line decoder are located approximately in the same regions as the corresponding word line contact and bit line contact, respectively.

FIG. 5C is a cross-sectional view of a section of the three-dimensional cross-point memory of FIG. 5A along the horizontal or X direction at the X-X axis shown in FIG. 5A. In this illustration, the bottom cell array 510, the top cell array 550, and many of the same elements as shown in FIG. 5B are shown and labeled as such. From this illustration, two portions of bottom

cell bit lines

510a and 510b can be seen, and two portions of top

cell bit lines

560a and 560b can be seen. In addition, two sets of bottom

cell bitline contacts

520a and 520b can be seen, while each set of top cell bitline contacts can be hidden behind the bottom

cell bitline contacts

510a and 520 b. Two portions of wordlines 530a and 530c and

corresponding wordline contacts

540a and 540c are visible from this illustration. Thus, as shown, both the bottom cell bit line and the top cell bit line and the memory cell are provided in a region overlapping a region contacted by the word line.

Fig. 6A-6D illustrate an exemplary biasing scheme for operating the exemplary three-dimensional cross-point memory shown in fig. 5A. In an example biasing scheme, the memory cells of the top cell array and the bottom cell array may receive a program signal or a read signal in a combination of a word line decoder and a bit line decoder. Each decoder receiving the signal determines the line to be activated based on the signal. As shown in the previous figures, the word lines and bit lines are arranged in a grid, whereby memory cells are located and thus data is stored at the intersections between the word lines and bit lines. Activation of the word line and one or more of the intersecting bit lines causes data to be programmed to or read from the memory cells at the intersection.

The example of FIG. 6A shows two cells A and B being programmed or read from based on activation of word lines and bit lines that intersect at the respective cells. In the example of cell a, word line 600 intersects bit line 604. Thus, a signal to a word line decoder of a word line 600 may indicate that the word line 600 is activated and that other word lines of the same word line decoder are kept inactive. Similarly, a signal to a bit line decoder of a bit line 604 may indicate that the bit line 604 is activated and that other bit lines of the same bit line decoder are to remain inactive. In the example of cell B, word line 600 intersects bit line 614. Thus, a signal to a word line decoder of a word line 600 may indicate that the word line 600 is activated and that other word lines of the same word line decoder are kept inactive. Similarly, a signal to the bit line decoder of a bit line 614 may indicate that the bit line 614 is activated and that other bit lines of the same bit line decoder are to remain inactive.

In the example of fig. 6A, the bit line 604 is a Bottom Cell Bit Line (BCBL) connected to a bottom cell bit line decoder through a bottom cell bit line contact (BCBL contact). Cell a is located between word line 600 and BCBL 604, making cell a the bottom array of memory cells. In contrast, bit line 614 is a Top Cell Bit Line (TCBL) connected to a top cell bit line decoder through a top cell bit line contact (TCBL contact). Cell B is located between word line 600 and TCBL 614, making cell B a top array of memory cells. Thus, fig. 6A shows how word lines, BCBL and TCBL can be arranged in order to activate memory cells of both the bottom cell array and the top cell array of the memory.

Activation of a word line or bit line may involve raising the voltage of the line above a threshold high voltage value (+ Vhh) or lowering the voltage of the line below a threshold low voltage value (-Vll). More generally, activation of a line may involve raising the absolute value of the voltage of the line above a threshold marker. In some examples, the threshold high voltage value may be between 5V and 20V, and preferably between 10V and 15V. In some examples, the threshold low voltage value may be between-20V and-5V, and preferably between-15V and-10V. The threshold high and low voltage values are different from the typical voltages of the word lines and bit lines when inactive. The inactive or unbiased voltage value is referred to herein as Vuw for the word line and Vub for the bit line. The absolute value of Vuw is less than the thresholds + Vhh and-Vll, and may preferably be not more than 2V, and more preferably 0V. Similarly, the absolute value of Vub is less than the thresholds + Vhh and-Vll, and may preferably be not greater than 2V, and more preferably 0V.

In the example of FIG. 6A, the biasing scheme for activating cell A includes raising the voltage of the word line 600 to or above a threshold high voltage value (+ Vhh), and lowering the voltage of the bit line 604 to or below a threshold low voltage value (-Vll). Similarly, the biasing scheme for activating cell B includes raising the voltage of the word line 600 to or above the threshold high voltage value (+ Vhh), and lowering the voltage of the bit line 614 to or below the threshold low voltage value (-Vll). As noted above, activation of a given cell may allow data to be programmed into the cell, or read from the cell. In some examples, activation of a cell may involve both reading data from the cell and further programming the cell with the read data.

In the example of FIG. 6A, while the wordline decoder activates wordline 600, the remaining unselected wordlines connected to the wordline decoder may remain inactive. The inactive word line may have a voltage Vuw, which may be about 0V in some examples. Similarly, while the bit line decoder activates the bit line 604 or the bit line 614, the remaining unselected TCBL and BCBL bit lines may remain inactive. The inactive bit lines may have a voltage Vub, which may be about 0V in some examples.

Table 1 summarizes the example biasing scheme of fig. 6A with respect to each of cells a and B:

TABLE 1

	Unit A	Unit B
			Selected WL	+Vhh	+Vhh
Selecting BL	-Vll	-Vll
			(one or more) unselected WLs	Vuw	Vuw
(one or more) unselected BL	Vub	Vub

Table 2 summarizes the example biasing scheme of fig. 6A for each of cells a and B, but for which the unbiased word line voltage Vuw and the unbiased bit line voltage Vub are equal to 0V.

TABLE 2

	Unit A	Unit B
			Selected WL	+Vhh	+Vhh
Selecting BL	-Vll	-Vll
			(one or more) unselected WLs	0	0
(one or more) unselected BL	0	0

The biasing scheme of fig. 6A is shown in more detail in each of fig. 6B, 6C, and 6D. FIG. 6B is a cross-sectional view of a section of the three-dimensional cross-point memory of FIG. 6A along the vertical or Y direction at the Y-Y axis shown in FIG. 6A. FIG. 6C is a cross-sectional view of a section of the three-dimensional cross-point memory of FIG. 6A along the horizontal or X direction at the X-X axis shown in FIG. 6A.

Each of fig. 6B and 6C shows cell a included in the first cell stack (cell stack 1) of the bottom cell array located between a word line (BCWL) including word line 600 and a BCBL including bit line 604; and cell B, which is included in the second cell stack (cell stack 2) of the top cell array located between the word line (BCWL) including the word line 600 and the TCBL including the bit line 614. As can be seen from these figures, the cell stack occupies almost all of the space between the top and bottom bit lines, only a small space is required for the word lines and the top cell bit lines to be connected to their respective decoders. This results in an increased storage density in the memory device and thus an increased storage efficiency.

When one of a high voltage or a low voltage is used to activate the word line of a given cell, the other of the high voltage or the low voltage is used to activate the bit line of the same given cell. For example, in the particular example of FIG. 6A, all word lines are activated by raising their voltage and all bit lines are activated by lowering their voltage. However, in other examples, all word lines may be activated by lowering their voltage and bit lines may be activated by raising their voltage.

In the above examples, it will be appreciated that any cell of the memory may be accessed (e.g., read, programmed) using the example biasing schemes discussed above. Further, it will also be appreciated that any two cells vertically aligned with each other may be accessed (e.g., read, programmed) simultaneously. This is possible because two vertically aligned cells share a word line and are connected to separate bit line blocks. For example, in FIGS. 6A, 6B, and 6C, each of the above cases may be achieved by applying a bias voltage + Vhh to the word line 600 and a bias voltage-Vll to each of the

bit lines

604 and 614.

This embodiment makes it possible to access two memory cells from a single block of memory without increasing the number of word line drivers or bit line drivers of the memory. As for the word line driver, as can be seen from fig. 6A, 6B, and 6C, only a single word line driver is required to access both cell a and cell B. With respect to the bit line drivers, the adjacent memory blocks are arranged so that they share the bit line drivers, so that it is not necessary to increase the total number of bit line drivers of the memory. Thus, two cells per memory block can be accessed simultaneously, doubling throughput without having to provide additional word line or bit line drivers.

In the above example, for a page of memory that includes 128 blocks, the access size of the page may be increased from 128 bits (16 bytes) to 256 bits (32 bytes). Similar improvements can be made to memories having pages of different sizes, whereby the access size of the page will be doubled, since two cells of each block can be accessed simultaneously. This makes the memory more suitable for applications requiring large access sizes, e.g. server applications preferably having an access size of 256 bits.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for accessing memory cells of a three-dimensional memory, comprising:

accessing memory cells of a first bottom cell block of a bottom cell array and memory cells of a first top cell block of a top cell array above the bottom cell array by biasing one of a first portion of word lines, one of a first portion of bottom cell bit lines, and one of a first portion of top cell bit lines; and

memory cells of a second bottom cell block of the bottom cell array that is offset from the first bottom cell block and memory cells of a second top cell block of the top cell array that is offset from the first top cell block are accessed by biasing one of a second portion of word lines, one of a second portion of bottom cell bit lines, and one of a second portion of top cell bit lines.

2. The method of claim 1, wherein the memory cells of the first bottom cell block and the first top cell block may be accessed simultaneously, and wherein the memory cells of the second bottom cell block and the second top cell block may be accessed simultaneously.

3. The method of claim 1, wherein accessing at least one cell of a block of cells comprises increasing a voltage of a word line coupled to the at least one cell above a first threshold and decreasing a voltage of a bit line coupled to the at least one cell below a second threshold.

4. The method of claim 3, wherein the first threshold is between about 5 and 20V, and wherein the second threshold is between about-20 and-5V.

5. The method of claim 3, wherein each unbiased word line has a voltage of approximately 2V, and wherein each unbiased bit line has a voltage of approximately 2V.

6. The method of claim 3, wherein:

accessing at least one cell of a memory block includes maintaining a voltage of each unbiased word line coupled to the memory block at a first unbiased voltage value and maintaining a voltage of each unbiased bit line coupled to the memory block at a second unbiased voltage value.

7. The method of claim 6, wherein the first unbiased voltage value is approximately 2V, and wherein the second unbiased voltage value is approximately 2V.

8. The method of claim 6, wherein each unbiased word line has a voltage of approximately 0V, and wherein each unbiased bit line has a voltage of approximately 0V.

9. The method of claim 1, wherein accessing a memory cell comprises at least one of reading data from the memory cell or programming data to the memory cell.

10. The method of claim 1, wherein the three-dimensional memory comprises a plurality of pages, wherein each page comprises a plurality of memory blocks, and wherein accessing memory cells of a given page of the three-dimensional memory comprises accessing two memory cells of each memory block at a time.

11. The method of claim 10, wherein each page comprises 128 memory blocks, and wherein accessing memory cells of a given page is performed at a rate of 256 memory cells at a time.

12. A method of accessing memory cells of a three-dimensional memory, comprising:

performing one-cell-at-a-time access to memory cells of a bottom cell block of the bottom cell array by biasing one of the plurality of word lines and one of the plurality of bottom cell bit lines; and

performing one-cell-at-a-time access to memory cells of a top cell block of a top cell array that is offset from the bottom cell block and is located above the bottom cell array in a depth direction by biasing one of the plurality of word lines and one of a plurality of top cell bit lines,

wherein the first memory cell and the second memory cell are simultaneously accessed by biasing word lines of both a first memory cell connected to the bottom cell block and a second memory cell located above the first memory cell of the top cell block among the plurality of word lines.

13. The method of claim 12, wherein biasing one of the plurality of word lines comprises increasing a voltage of the one word line above a first threshold.

14. The method of claim 13, wherein biasing one of the plurality of word lines comprises maintaining voltages of the plurality of word lines other than the one word line at an unbiased word line voltage value.

15. The method of claim 13, wherein biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines comprises dropping a voltage of the first bit line and the second bit line below a second threshold.

16. The method of claim 15, wherein biasing a first bit line of the plurality of bottom cell bit lines and a second bit line of the plurality of top cell bit lines comprises maintaining voltages of the plurality of bottom cell bit lines and the plurality of top cell bit lines other than the first bit line and the second bit line at unbiased bit line voltage values.

17. The method of claim 12, wherein accessing the memory cell comprises at least one of reading data from or programming data to the memory cell.

18. The method of claim 12, wherein the three-dimensional memory comprises a plurality of pages, wherein each page comprises a plurality of memory blocks, and wherein accessing memory cells of a given page of the three-dimensional memory comprises accessing two memory cells of each memory block at a time.

19. The method of claim 18, wherein each page comprises 128 memory blocks, and wherein accesses to memory cells of a given page are performed at a rate of 256 memory cells at a time.

20. The method of claim 12, wherein the bottom cell block is located below the plurality of word lines in the depth direction, and the top cell block is located above the plurality of word lines in the depth direction.