CN112466817B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN112466817B CN112466817B CN202011332020.0A CN202011332020A CN112466817B CN 112466817 B CN112466817 B CN 112466817B CN 202011332020 A CN202011332020 A CN 202011332020A CN 112466817 B CN112466817 B CN 112466817B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1022—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including bipolar transistors
Abstract
The preparation method comprises the step of carrying out patterning treatment on a sacrificial layer, and simultaneously forming two first boundary pattern units arranged at intervals along a first direction and a plurality of separation pattern units arranged at intervals between the first boundary pattern units and along a second direction. The method and the device realize the simultaneous formation of the boundary patterns in the process of forming the internal fine patterns, increase the available area of the preparation process of the boundary between the internal fine pattern area and the peripheral circuit area, reduce the difficulty of the preparation process, simplify the process flow and reduce the cost.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a preparation method of a semiconductor device and the semiconductor device.
Background
Today, semiconductor devices are typically highly integrated and highly dense. Accordingly, design rules of semiconductor devices have been continuously reduced, and methods of forming fine patterns in semiconductor devices have been used. Sometimes because they are too small, it is necessary to form fine patterns using techniques that exceed the resolution limits of the lithographic apparatus. However, in the peripheral circuit region or the core region, the boundary between the internal fine pattern region and the peripheral circuit region is usually formed by etching after the internal fine pattern and the peripheral circuit are formed, but at this time, since the fine pattern and the peripheral circuit are already formed, a process available region left for the boundary is small, and the difficulty of a preparation process is large.
Disclosure of Invention
In view of the above problems, the present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device, which solves the technical problem in the prior art that the difficulty of the manufacturing process of the boundary between the internal fine pattern region and the peripheral circuit region is high.
In a first aspect, the present disclosure provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate;
forming a dielectric layer over the substrate;
forming a sacrificial layer over the dielectric layer;
patterning the sacrificial layer to form a sacrificial layer pattern over the dielectric layer; the sacrificial layer pattern comprises two first boundary pattern units arranged at intervals along a first direction and a plurality of separation pattern units arranged between the first boundary pattern units and arranged at intervals along a second direction; wherein the first direction intersects the second direction;
forming a spacer on a sidewall of each pattern unit of the sacrificial layer pattern;
filling the space between the spacers to form a first filling layer coating the sacrificial layer pattern, and removing the spacers in the first filling layer to form a filling layer pattern above the dielectric layer; wherein the filling layer pattern comprises a plurality of filling pattern units which are spaced from and alternate with the separation pattern units;
forming a mask layer above the sacrificial layer pattern and the filling layer pattern, and performing patterning treatment on the mask layer to form a mask pattern above the sacrificial layer pattern and the filling layer pattern; the mask pattern comprises a plurality of first line mask pattern units arranged at intervals along a third direction, and second line mask pattern units covering the first boundary pattern units, wherein the third direction is intersected with the second direction;
and patterning the separation pattern unit and the filling pattern unit by using the mask pattern so as to form a plurality of sacrificial columns and a plurality of filling columns which are arranged in an array manner above the dielectric layer.
According to an embodiment of the present disclosure, preferably, the partition pattern unit is in contact with the first boundary pattern unit.
According to an embodiment of the present disclosure, preferably, the partition pattern unit intersects the first boundary pattern unit, and the partition pattern unit extends to the outside of the first boundary pattern unit.
According to an embodiment of the present disclosure, preferably, the third direction is the same as the first direction.
According to the embodiment of the present disclosure, preferably, the method further includes:
filling the space among the first boundary pattern unit, the sacrificial columns and the filling columns to form a second filling layer;
removing the first boundary pattern unit, the sacrificial columns and the filling columns in the second filling layer to form boundary trenches and a plurality of openings arranged in an array on the second filling layer; wherein, a plurality of the openings form an opening array;
etching the dielectric layer below the boundary trench and the opening by taking the boundary trench and the opening as etching windows so as to form etching trenches and a plurality of etching holes arranged in an array on the dielectric layer;
and forming a storage unit in the etching hole, and forming a region boundary of the storage unit in the etching groove.
According to an embodiment of the present disclosure, preferably, the sacrificial layer pattern further includes two second boundary pattern units disposed at intervals along a fourth direction, wherein the fourth direction is perpendicular to the first direction, and the first boundary pattern unit and the second boundary pattern unit constitute a closed boundary pattern.
According to the embodiment of the present disclosure, preferably, in the opening array, a shape of the opening located at the fourth directional edge position does not coincide with a shape of the opening located inside;
the distance between the openings located at the fourth direction edge position in the first direction of the opening array is not uniform with the distance between the openings located at the inside.
According to an embodiment of the present disclosure, preferably, the patterning process of the sacrificial layer to form a sacrificial layer pattern over the dielectric layer includes:
forming a first photoresist layer over the sacrificial layer;
patterning the first photoresist layer through a first mask to form a photoresist pattern;
etching the sacrificial layer through the photoresist pattern to form a sacrificial layer pattern over the dielectric layer;
and removing the photoresist pattern.
According to an embodiment of the present disclosure, preferably, forming a spacer on a sidewall of each pattern unit of the sacrificial layer pattern includes:
forming an oxide layer over each pattern unit of the sacrificial layer pattern and on sidewalls thereof by an atomic layer deposition method;
performing an etch-back process on the oxide layer to form a spacer on a sidewall of each pattern unit of the sacrificial layer pattern.
According to the embodiment of the present disclosure, preferably, the material of the mask layer is a photoresist; forming a mask layer above the sacrificial layer pattern and the filling layer pattern, and performing patterning processing on the mask layer to form a mask pattern above the sacrificial layer pattern and the filling layer pattern, wherein the method comprises the following steps:
forming a second photoresist layer over the sacrificial layer pattern and the filling layer pattern;
and patterning the second photoresist layer through a second mask to form a mask pattern over the sacrificial layer pattern and the filling layer pattern.
According to an embodiment of the present disclosure, preferably, the patterning of the separation pattern unit and the filling pattern unit by using the mask pattern to form a plurality of sacrificial columns and a plurality of filling columns arranged in an array above the dielectric layer includes:
etching the separation pattern unit and the filling pattern unit by taking the mask pattern as an etching mask to form a plurality of sacrificial columns and a plurality of filling columns;
and removing the mask pattern.
In a second aspect, the present disclosure provides a semiconductor device fabricated using the method of any one of the first aspects.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the preparation method comprises the step of carrying out patterning treatment on a sacrificial layer, and simultaneously forming two first boundary pattern units arranged at intervals along a first direction and a plurality of separation pattern units arranged at intervals between the first boundary pattern units and along a second direction. The method and the device realize the simultaneous formation of the boundary patterns in the process of forming the internal fine patterns, increase the available area of the preparation process of the boundary between the internal fine pattern area and the peripheral circuit area, reduce the difficulty of the preparation process, simplify the process flow and reduce the cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic flow chart illustrating a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure;
fig. 2-18 are schematic front side plan views and schematic cross-sectional structures formed at steps associated with a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure;
in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;
101-a substrate; 102-a dielectric layer; 103-sacrificial layer pattern; 1031-first boundary pattern unit; 1032-separation pattern unit; 1033-a second boundary pattern unit; 104-a spacer; 105-a first fill layer; 1051-fill pattern units; 106-mask pattern; 1061-first line mask pattern unit; 1062-second line mask pattern unit; 107-sacrificial post; 108-a packed column; 109-a second fill layer; 110-a boundary trench; 111-opening; 112-etching the hole.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
The embodiment provides a method for manufacturing a semiconductor device. Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 2-18 are schematic diagrams of a top view and a cross-sectional structure of a front surface and formed by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the disclosure. Next, detailed steps of an exemplary method of a method of manufacturing a semiconductor device proposed by an embodiment of the present disclosure are described with reference to fig. 1 and fig. 2 to 18.
As shown in fig. 1, the method for manufacturing a semiconductor device of the present embodiment includes the following steps:
step S101: a semiconductor substrate 101 is provided.
The semiconductor substrate 101 may include, for example, at least one of a single crystal silicon substrate and a silicon epitaxial layer.
Step S102: a dielectric layer 102 is formed over a substrate 101.
The material of the dielectric layer 102 includes silicon oxide.
Step S103: a sacrificial layer is formed over the dielectric layer 102.
The sacrificial layer is used as an auxiliary film layer in the subsequent process and is used for forming fine patterns and region boundaries, and the sacrificial layer is removed after the patterns are formed. The material of the sacrificial layer includes at least one of silicon oxide, silicon oxynitride, polysilicon, and amorphous carbon.
Step S104: as shown in fig. 2 and 3, a sacrificial layer (not labeled) is patterned to form a sacrificial layer pattern 103 over the dielectric layer 102; wherein the sacrificial layer pattern 103 includes two first boundary pattern units 1031 arranged at intervals in a first direction, and a plurality of partition pattern units 1032 positioned between the first boundary pattern units 1031 and arranged at intervals in a second direction; wherein the first direction intersects the second direction.
Therefore, the preparation process of the area boundary is simultaneously carried out in the process of forming the internal fine pattern, so that the available area of the preparation process of the area boundary is increased, the difficulty of the preparation process is reduced, the process flow is simplified, and the cost is reduced.
Specifically, step S104 includes the following steps:
s104 a: forming a first photoresist layer (not shown) over the sacrificial layer (not shown);
s104 b: patterning the first photoresist layer (not shown) through a first mask (not shown) to form a photoresist pattern (not shown);
s104 c: etching a sacrificial layer (not shown) through a photoresist pattern (not shown) to form a sacrificial layer pattern 103 over the dielectric layer 102;
s104 d: the photoresist pattern is removed.
The first boundary pattern unit 1031 in the first direction is a longitudinal first boundary pattern unit 1031 as shown in fig. 2, and it should be noted that the sacrificial layer pattern 103 may further include two boundary pattern units arranged at intervals in another direction (fourth direction) perpendicular to the first direction, and a transverse second boundary pattern boundary 1033 as shown in fig. 2. The first and second boundary pattern units 1031 and 1033 constitute a closed boundary pattern, such as a square boundary pattern shown in fig. 2.
The partition pattern unit 1032 is in contact with the first boundary pattern unit 1031, as shown in fig. 2. Or the partition pattern units 1032 intersect the first boundary pattern units 1031 and the partition pattern units 1032 extend beyond the first boundary pattern units 1031 (and the second boundary pattern boundaries 1033), as shown in fig. 4, such a structure can compensate for the stress that is not uniform between the partition pattern units 1032 at the ends and also can prevent the cells from being damaged.
Step S105: as shown in fig. 5 and 6, spacers 104 are formed on sidewalls of each pattern unit of the sacrificial layer pattern 103.
Specifically, step S105 includes the following steps:
s105 a: forming an oxide layer (not labeled) over and on sidewalls of each pattern unit of the sacrificial layer pattern 103 by an atomic layer deposition method;
s105 b: an etch-back process is performed on the oxide layer (not shown) to form spacers 104 on sidewalls of each pattern unit of the sacrificial layer pattern 103.
The oxide layer prepared by the atomic layer deposition method has good step coverage, and can completely cover each pattern unit of the sacrificial layer pattern 103.
The oxide layer may have an etch selectivity with respect to the sacrificial layer and thus may have a faster etch rate than the sacrificial layer pattern 103. After the etch-back process, only the portion of the oxide layer located on the sidewalls of each pattern unit of the sacrificial layer pattern 103, i.e., the spacer 104, remains. The etch-back process may include: a dry etch back process, a Chemical Mechanical Polishing (CMP) process, or a wet strip process. In the etch back process, the oxide layer above each pattern unit of the sacrificial layer pattern 103 is removed to expose the upper surface of each pattern unit.
The oxide layer material may be formed of silicon oxide, silicon oxynitride, or silicon nitride.
Step S106: filling the space between the spacers 104 to form a first filling layer 105 covering the sacrificial layer pattern 103, as shown in fig. 7 and 8, and removing the spacers 104 in the first filling layer 105 to form a filling layer pattern over the dielectric layer 102, as shown in fig. 9 and 10; wherein the filling layer pattern includes a plurality of filling pattern units 1051 spaced and alternating with the separation pattern units 1032.
Wherein the thickness of the first filling-up layer 105 is less than or equal to the thickness of the sacrificial layer pattern 103 and the spacer 104. The first filling layer 105 fills the gap between the spacers 104 and exposes the sacrificial layer pattern 103 and the tops of the spacers 104. Then, the spacers 104 are removed, and a plurality of filling pattern units 1051 spaced and alternating with the separation pattern units 1032 may be formed.
The material of the first filling-up layer 105 may be identical to that of the sacrificial layer. The line width of the separation pattern unit 1032 is the same as the line width of the filling pattern unit 1051 to form a fine pattern having a uniform line width. And a high-density fine pattern is formed by the spacing action of the spacers 104.
Step S107: as shown in fig. 11 and 12, a mask layer (not shown) is formed over the sacrificial layer pattern 103 and the filling layer pattern, and is subjected to a patterning process to form a mask pattern 106 over the sacrificial layer pattern 103 and the filling layer pattern; the mask pattern 106 includes a plurality of first line mask pattern units 1061 arranged at intervals along a third direction, and second line mask pattern units 1062 covering the first boundary pattern units 1031, wherein the third direction intersects the second direction.
The second line mask pattern units 1062 are overlaid on the first boundary pattern units 1031, and the direction of the second line mask pattern units 1062 coincides with the direction of the first boundary pattern units 1031, i.e., the first direction.
For example, the third direction may be a vertical direction as shown in fig. 11, that is, the directions of the first and second line mask pattern units 1061 and 1062 are identical, and the third direction may be the same as the first direction. The first line mask pattern unit 1061 and the second line mask pattern unit 1062 extend to the outside of the closed boundary pattern, so that the mask pattern 106 can fully cover the portion of the boundary pattern that does not need to be etched, and the portion of the boundary pattern that does not need to be etched due to errors in the exposure and etching processes is prevented from being etched.
The material of the mask layer may be photoresist, and step S107 includes the following steps:
s107 a: forming a second photoresist layer (not shown) over the sacrificial layer pattern 103 and the filling layer pattern;
s107 b: the second photoresist layer (not shown) is patterned through a second mask (not shown) to form a mask pattern 106 over the sacrificial layer pattern 103 and the filling layer pattern.
In addition, the material of the mask layer may be a hard mask material such as silicon oxide or silicon nitride, and in this case, the mask pattern 106 may be formed in a specific manner, similar to the preparation method of the separation pattern unit 1032 and the filling pattern unit 1051, and the high-density mask pattern 106 may be formed by the spacing effect of the spacers.
Step S108: as shown in fig. 13 and 14, the partition pattern unit 1032 and the filling pattern unit 1051 are patterned by using the mask pattern 106 to form a plurality of sacrificial columns 107 and a plurality of filling columns 108 arranged in an array over the dielectric layer 102.
Specifically, step S108 includes the following steps:
s108 a: etching the partition pattern unit 1032 and the filling pattern unit 1051 with the mask pattern 106 as an etching mask to form a plurality of sacrificial columns 107 and a plurality of filling columns 108;
s108 b: the mask pattern 106 is removed.
Since the first line mask pattern unit 1061 of the third direction in the mask pattern 106 intersects the separation pattern unit 1032 and the filling pattern unit 1051 of the second direction, the portion (columnar portion) covered by the first line mask pattern unit 1061 remains during the etching process, i.e., the sacrificial post 107 and the filling post 108. And the first boundary pattern unit 1031 is covered by the second line mask pattern unit 1062 and also remains. It is further realized that the process of preparing the region boundary is simultaneously performed in the process of forming the inner fine pattern.
Step S109: as shown in fig. 15, the first boundary pattern unit 1031, the sacrificial post 107 and the filling post 108 are filled therebetween to form a second filling layer 109.
Wherein the thickness of the second filling-up layer 109 is less than or equal to the thickness of the sacrificial post 107 and the filling-up post 108. The second filling layer 109 fills the gap between the sacrificial post 107 and the filling post 108 and exposes the top of the sacrificial post 107 and the filling post 108.
Step S110: as shown in fig. 16 and 17, the first boundary pattern unit 1031, the sacrificial columns 107 and the filling columns 108 in the second filling layer 109 are removed to form a boundary trench 110 and a plurality of openings 111 arranged in an array on the second filling layer 109; wherein, the plurality of openings 111 form an opening array (not labeled in the figure).
Since the thickness of the second filling-up layer 109 is less than or equal to the thickness of the sacrificial post 107 and the filling post 108, after removing the first boundary pattern unit 1031, the sacrificial post 107 and the filling post 108, a corresponding boundary trench 110 is formed on the second filling-up layer 109 at the position of the first boundary pattern unit 1031, and an opening 111 is formed on the second filling-up layer 109 at the corresponding position of the sacrificial post 107 and the filling post 108.
Note that, due to the presence of the second boundary pattern unit 1033, as shown in fig. 16, in the opening array, the shape of the opening 111 located at the fourth directional edge (lateral edge) does not coincide with the shape of the opening 111 located inside. In the opening array in the first direction (longitudinal direction), the distance (longitudinal distance) between the openings 111 located at the fourth direction edge (lateral edge) is not uniform with the distance (longitudinal distance) between the openings 111 located at the inner portion.
Step S111: as shown in fig. 18, the dielectric layer 102 under the boundary trench 110 and the opening 111 is etched by using the boundary trench 110 and the opening 111 as an etching window, so as to form an etching trench and a plurality of etching holes 112 arranged in an array on the dielectric layer 102.
If the etching window is formed by adopting a mask photoetching mode, the process difficulty is higher, and the boundary groove 110 and the opening 111 are used as the etching window, so that the process difficulty is reduced.
Therefore, the area boundary is formed simultaneously in the process of forming the internal fine pattern, so that the available area of the preparation process of the area boundary is increased, the difficulty of the preparation process is reduced, the process flow is simplified, and the cost is reduced.
Step S112: memory cells are formed in the etch holes 112 and the region boundaries of the memory cells are formed in the etched trenches.
In summary, the present disclosure provides a method for manufacturing a semiconductor device, which simultaneously forms two spaced first boundary pattern units 1031 in a first direction and a plurality of spaced separation pattern units 1032 between the first boundary pattern units 1031 in a second direction when patterning a sacrificial layer, and a semiconductor device. The method and the device realize the simultaneous formation of the boundary patterns in the process of forming the internal fine patterns, increase the available area of the preparation process of the boundary between the internal fine pattern area and the peripheral circuit area, reduce the difficulty of the preparation process, simplify the process flow and reduce the cost.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (12)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a dielectric layer over the substrate;
forming a sacrificial layer over the dielectric layer;
patterning the sacrificial layer to form a sacrificial layer pattern over the dielectric layer; the sacrificial layer pattern comprises two first boundary pattern units arranged at intervals along a first direction and a plurality of separation pattern units arranged between the first boundary pattern units and arranged at intervals along a second direction; wherein the first direction intersects the second direction;
forming a spacer on a sidewall of each pattern unit of the sacrificial layer pattern;
filling the space between the spacers to form a first filling layer coating the sacrificial layer pattern, and removing the spacers in the first filling layer to form a filling layer pattern above the dielectric layer; wherein the filling layer pattern comprises a plurality of filling pattern units which are spaced from and alternate with the separation pattern units;
forming a mask layer above the sacrificial layer pattern and the filling layer pattern, and performing patterning treatment on the mask layer to form a mask pattern above the sacrificial layer pattern and the filling layer pattern; the mask pattern comprises a plurality of first line mask pattern units arranged at intervals along a third direction, and second line mask pattern units covering the first boundary pattern units, wherein the third direction is intersected with the second direction;
and patterning the separation pattern unit and the filling pattern unit by using the mask pattern so as to form a plurality of sacrificial columns and a plurality of filling columns which are arranged in an array manner above the dielectric layer.
2. The method of claim 1, wherein the separation pattern unit is in contact with the first boundary pattern unit.
3. The method of claim 1, wherein the separation pattern unit intersects the first boundary pattern unit and the separation pattern unit extends beyond the first boundary pattern unit.
4. The method of claim 1, wherein the third direction is the same as the first direction.
5. The method of claim 1, further comprising:
filling the space among the first boundary pattern unit, the sacrificial columns and the filling columns to form a second filling layer;
removing the first boundary pattern unit, the sacrificial columns and the filling columns in the second filling layer to form boundary trenches and a plurality of openings arranged in an array on the second filling layer; wherein, a plurality of the openings form an opening array;
etching the dielectric layer below the boundary trench and the opening by taking the boundary trench and the opening as etching windows so as to form etching trenches and a plurality of etching holes arranged in an array on the dielectric layer;
and forming a storage unit in the etching hole, and forming a region boundary of the storage unit in the etching groove.
6. The method of claim 5, wherein the sacrificial layer pattern further comprises two second boundary pattern units spaced apart along a fourth direction, wherein the fourth direction is perpendicular to the first direction, and the first boundary pattern unit and the second boundary pattern unit form a closed boundary pattern.
7. The method according to claim 6, wherein in the array of openings, the shape of the opening at the fourth directional edge position does not coincide with the shape of the opening at the interior;
the distance between the openings located at the fourth direction edge position in the first direction of the opening array is not uniform with the distance between the openings located at the inside.
8. The method of claim 1, wherein patterning the sacrificial layer to form a sacrificial layer pattern over the dielectric layer comprises:
forming a first photoresist layer over the sacrificial layer;
patterning the first photoresist layer through a first mask to form a photoresist pattern;
etching the sacrificial layer through the photoresist pattern to form a sacrificial layer pattern over the dielectric layer;
and removing the photoresist pattern.
9. The method of claim 1, wherein forming spacers on sidewalls of each pattern unit of the sacrificial layer pattern comprises:
forming an oxide layer over each pattern unit of the sacrificial layer pattern and on sidewalls thereof by an atomic layer deposition method;
performing an etch-back process on the oxide layer to form a spacer on a sidewall of each pattern unit of the sacrificial layer pattern.
10. The method of claim 1, wherein the material of the mask layer is a photoresist; forming a mask layer above the sacrificial layer pattern and the filling layer pattern, and performing patterning processing on the mask layer to form a mask pattern above the sacrificial layer pattern and the filling layer pattern, wherein the method comprises the following steps:
forming a second photoresist layer over the sacrificial layer pattern and the filling layer pattern;
and patterning the second photoresist layer through a second mask to form a mask pattern over the sacrificial layer pattern and the filling layer pattern.
11. The method according to claim 1, wherein the patterning the separation pattern unit and the filling pattern unit using the mask pattern to form a plurality of sacrificial columns and a plurality of filling columns arranged in an array over the dielectric layer comprises:
etching the separation pattern unit and the filling pattern unit by taking the mask pattern as an etching mask to form a plurality of sacrificial columns and a plurality of filling columns;
and removing the mask pattern.
12. A semiconductor device prepared by the method of any one of claims 1 to 11.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011332020.0A CN112466817B (en) | 2020-11-24 | 2020-11-24 | Method for manufacturing semiconductor device and semiconductor device |
Applications Claiming Priority (1)
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