CN112466748A - Method for manufacturing gate dielectric layer of MOS device - Google Patents
Method for manufacturing gate dielectric layer of MOS device Download PDFInfo
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- CN112466748A CN112466748A CN202011361953.2A CN202011361953A CN112466748A CN 112466748 A CN112466748 A CN 112466748A CN 202011361953 A CN202011361953 A CN 202011361953A CN 112466748 A CN112466748 A CN 112466748A
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- oxide film
- silicon substrate
- dielectric layer
- gate dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a gate dielectric layer of an MOS device. The manufacturing method of the MOS device gate dielectric layer comprises the following steps: providing a silicon substrate; growing and forming a first oxide film on the silicon substrate, so that the first oxide film and the silicon substrate are in interfacial contact with a first interfacial contact surface; performing nitriding treatment on the first oxide film by adopting a decoupling plasma nitriding process so as to enable nitrogen ions to permeate into the first oxide film; and oxidizing the silicon substrate at the first interface contact surface through oxidation annealing treatment to form a second oxide film, so that the second oxide film and the silicon substrate are in interface contact with a second interface contact surface. The problem that the concentration of nitrogen ions at the interface between the gate dielectric layer and the silicon substrate is high after the nitrogen doping treatment in the related technology can be solved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a gate dielectric layer of an MOS device.
Background
With the continuous reduction of the critical dimension of Metal Oxide Semiconductor (MOS) devices, the conventional thickness of silicon dioxide gate dielectric layer has not been able to meet the requirements of the devices. Therefore, in order to increase the response speed of the device and increase the driving current and the capacity of the storage capacitor, the thickness of the silicon dioxide gate dielectric layer in the device is continuously reduced. However, as the thickness of the silicon dioxide gate dielectric layer is reduced, some effects may occur that degrade device performance. For example, in the presence of a thin dielectric layer, gate leakage current often also increases due to tunneling; boron in the boron-doped gate electrode can permeate into the silicon substrate below through the thin silicon dioxide gate dielectric layer, so that not only is the threshold voltage drift caused, but also the silicon dioxide gate dielectric layer is damaged and the reliability of the silicon dioxide gate dielectric layer is reduced; thin silicon dioxide gate dielectric layers are susceptible to hot carrier damage, and high energy carriers moving through the dielectric layers can damage or destroy the gate; in addition, thin silicon dioxide gate dielectric layers are also susceptible to negative bias temperature instability, wherein the threshold voltage or drive current drifts with the operation of the gate. Therefore, the conventional gate structure needs to be changed, and the dielectric constant of the gate dielectric layer needs to be improved.
Currently, the related art usually employs nitrogen doping into the gate dielectric layer to meet the process requirement, and the conventional nitrogen doping process employs nitrogen oxide or nitrogen dioxide to perform annealing for a certain time to achieve nitrogen doping. However, after the nitrogen doping treatment is completed, the concentration of nitrogen ions at the interface between the gate dielectric layer and the silicon substrate is high, so that on one hand, the device generates a coulomb scattering effect to slow down the reaction speed of the device, and on the other hand, the high concentration of nitrogen ions at the interface can make the formed nitrogen-silicon chemical bond unstable, and the silicon dangling bond can be formed under stress to influence the performance of the device.
Although the peak of the nitrogen ions can be pushed away from the interface by some technical means, the higher nitrogen ion concentration is still kept at the interface between the gate dielectric layer and the silicon substrate, which is about in the order of E21 at/cc. Thereby adversely affecting the performance of the device.
Disclosure of Invention
The application provides a manufacturing method of an MOS gate dielectric layer, which can solve the problem that the concentration of nitrogen ions at the interface between the gate dielectric layer and a silicon substrate is high after nitrogen doping treatment in the related technology.
The application provides a manufacturing method of a gate dielectric layer of an MOS device, which comprises the following steps:
providing a silicon substrate;
growing and forming a first oxide film on the silicon substrate, so that the first oxide film and the silicon substrate are in interfacial contact with a first interfacial contact surface;
performing nitriding treatment on the first oxide film by adopting a decoupling plasma nitriding process so as to enable nitrogen ions to permeate into the first oxide film;
and oxidizing the silicon substrate at the first interface contact surface through oxidation annealing treatment to form a second oxide film, so that the second oxide film and the silicon substrate are in interface contact with a second interface contact surface.
Optionally, the step of growing and forming a first oxide film on the silicon substrate includes:
and growing and forming a first oxide film on the silicon substrate by an ISSG (silicon-on-glass) process.
Optionally, in the ISSG process, the ambient temperature for forming the first oxide film is: the ISSG process is carried out at 850-950 ℃ for 15-20 s.
Optionally, the step of performing nitridation treatment on the first oxide film by using a decoupled plasma nitridation process to make the first oxide film permeate nitrogen ions includes:
and performing nitriding treatment on the first oxide film by adopting a decoupling plasma nitriding process within the power range of 1800W to 2500W for 60s to 120s so that nitrogen ions permeate into the first oxide film.
Optionally, the step of forming a second oxide film by oxidizing the silicon substrate located at the first interface contact surface through an oxidation annealing process includes:
and annealing and oxidizing for 10s to 20s in an environment with the temperature of 1100 ℃ to 1200 ℃, so that the silicon substrate positioned at the first interface contact surface is oxidized to form a second oxide film.
Optionally, nitrogen and oxygen are introduced during the oxidation annealing treatment.
Optionally, the gas flow ratio of the nitrogen gas to the oxygen gas is as follows: 20: 6 to 20: 9.
the technical scheme at least comprises the following advantages: and after nitriding treatment is carried out on the first oxide film, carrying out oxidation process again, so that the surface of the silicon substrate at the interface contact surface of the first oxide film and the silicon substrate is oxidized to form a second oxide film. The second oxide film is not subjected to nitridation treatment, and the content of nitrogen ions in the second oxide film is small, so that the nitrogen content between the interface contact area of the second oxide film and the silicon substrate can be reduced, and the problem that the nitrogen-silicon bond in the interface contact area is unstable to form a silicon dangling bond to influence the performance of a device is further avoided.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a process flow of a MOS device gate dielectric layer fabrication process according to an embodiment of the present application;
fig. 2 shows a schematic cross-sectional structure of a provided silicon substrate 110;
fig. 3 shows a schematic cross-sectional structure of the device after step S2 is completed;
fig. 4 shows a schematic diagram of step S3 of performing a plasma nitridation process on the first oxide film;
fig. 5 shows a schematic cross-sectional structure after step S4 is completed;
fig. 6 is a graph showing the nitrogen content of the gate dielectric layer manufactured by the related art and the gate dielectric layer manufactured by the present embodiment as a function of depth.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 shows a flowchart of a method for manufacturing a gate dielectric layer of an MOS device according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a gate dielectric layer of an MOS device includes the following steps:
step S1: a silicon substrate is provided. The silicon substrate includes opposing upper and lower surfaces.
Fig. 2 shows a schematic cross-sectional structure of a provided silicon substrate 110, the silicon substrate 110 comprising an upper surface 111 and a lower surface 112 opposite to each other.
Step S2: and growing and forming a first oxide film on the silicon substrate, wherein the first oxide film is in interface contact with the silicon substrate.
Fig. 3 shows a schematic cross-sectional structure of the device after step S2 is completed, and as shown in fig. 3, a first oxide film 120 is grown on the silicon substrate 110, and the first oxide film 120 and the silicon substrate 110 are in interfacial contact with a first interfacial contact area 121.
In this embodiment, the upper surface layer of the silicon substrate 110 is oxidized to form a dense first oxide film 120 by processing for 15s to 20s In a low pressure environment containing oxygen and hydrogen at a temperature of 850 ℃ to 950 ℃ through an ISSG (In-Situ Steam oxidation) process, and the lower surface 121 of the formed first oxide film 120 is In interfacial contact with the silicon substrate 110; it should be noted that the surface of the oxide film in interface contact with the silicon substrate 110 is an interface contact surface, and therefore the lower surface 121 of the first oxide film 120 is the interface contact surface 121 of the oxide film.
Step S3: and nitriding the first oxide film by adopting a decoupling plasma nitriding process so as to enable the first oxide film to be permeated with nitrogen ions.
Fig. 4 shows a schematic diagram of step S3 of performing a plasma nitridation process on the first oxide film. After the nitriding process is performed on the first oxide film 120, nitrogen ions permeate into the first oxide film 120 and react with silicon dioxide to form nitrogen-silicon bonds. The first oxide film 120 having nitrogen-silicon bonds has an improved dielectric constant, and the thickness of the first oxide film 120 can be reduced without increasing the damage to the gate dielectric layer. However, nitrogen ions are easily accumulated on the interface between the first oxide film 120 and the silicon substrate 110, so that the nitrogen-silicon bond around the interface is unstable, and the nitrogen-silicon bond is broken to form a silicon dangling bond, thereby affecting the performance of the device.
In this embodiment, a decoupled plasma nitridation process is adopted, the power range of the nitridation process performed on the first oxide film 120 is 1800W to 2500W, and the processing time is 60s to 120s, so that nitrogen ions permeate into the first oxide film.
Step S4: and oxidizing the silicon substrate positioned at the first interface contact surface through oxidation annealing treatment to form a second oxide film, wherein the second oxide film and the silicon substrate are in interface contact with a second interface contact surface.
Fig. 5 shows a schematic cross-sectional structure after step S4 is completed, and referring to fig. 3 and 5, the silicon substrate 110 at the first interface contact surface 121 shown in fig. 3 is oxidized to form the second oxide film 130 shown in fig. 5, and the second oxide film 130 and the silicon substrate 10 interface-contact the second interface contact surface 131.
After the nitridation treatment is performed on the first oxide film 120, the oxidation process is performed again, so that the surface of the silicon substrate 110 at the interface contact surface 121 of the first oxide film 120 and the silicon substrate 110 is oxidized to form a second oxide film 130. The second oxide film 130 is grown on the lower surface of the first oxide film 120 on the basis of the first oxide film 120, and the first oxide film 120 and the second oxide film 130 together constitute an oxide film which can be used as a gate dielectric layer. The second oxide film 130 is in interfacial contact with the silicon substrate 110, and the second oxide film 130 is in interfacial contact with the silicon substrate 110 at a second interfacial contact surface 131.
The second oxide film 13 is not subjected to nitridation treatment, so that the content of nitrogen ions in the second oxide film is small, the nitrogen content between the interface contact area of the second oxide film 13 and the silicon substrate 110 can be reduced, and the problem that nitrogen ions are accumulated in the interface contact area of the oxide film and the silicon substrate 110, so that nitrogen-silicon bonds in the interface contact area are unstable to form silicon dangling bonds, and the performance of a device is affected is solved.
In the embodiment, the device is subjected to oxidation annealing treatment in a gas environment comprising nitrogen and oxygen, wherein the annealing temperature is 1100 ℃ and the annealing time is 10-20 s. Wherein the gas flow ratio range of N2 and O2 is 20: 6 to 20: 9. the second oxide film 130 is formed by oxidizing the silicon substrate 110 at the oxide film contact surface by subjecting the device after the nitridation treatment to an oxidation annealing treatment here.
Fig. 6 is a graph showing the nitrogen content of the gate dielectric layer manufactured by the related art and the gate dielectric layer manufactured by the present embodiment as a function of depth.
In the graph shown in FIG. 6, the horizontal axis represents the depth from the surface of the gate dielectric layer in angstroms (A), and the vertical axis represents the nitrogen content in units of the number of nitrogen atoms per unit volume, i.e., at/cc. Curve a in fig. 6 represents a curve of nitrogen content with depth for a gate dielectric layer fabricated by the related art; curve B shows the curve of the nitrogen content with depth for the gate dielectric layer fabricated by this example. In addition, the thickness of the gate dielectric layer manufactured by the related technology is 26A; the thickness of the gate dielectric layer manufactured by the embodiment is 30A, the annealing temperature used in the oxidation annealing process in the embodiment is 1100 ℃, the time is 20s, and the gas flow ratio range of N2 to O2 is 20: 6.
fig. 6 shows that Y1 is the position of the interface between the gate dielectric layer and the silicon substrate in the related art, Y2 is the position of the interface between the gate dielectric layer and the silicon substrate in this embodiment, point (i) is the nitrogen content at the position of the interface between the gate dielectric layer and the silicon substrate in the related art, and point (ii) is the nitrogen content at the position of the interface between the gate dielectric layer and the silicon substrate in this embodiment, and it can be seen from fig. 6 that the nitrogen content at the position of the interface between the gate dielectric layer and the silicon substrate in this embodiment is lower than the nitrogen content at the position of the interface between the gate dielectric layer and the silicon substrate in the related art.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A manufacturing method of a gate dielectric layer of an MOS device is characterized by comprising the following steps:
providing a silicon substrate;
growing and forming a first oxide film on the silicon substrate, so that the first oxide film and the silicon substrate are in interfacial contact with a first interfacial contact surface;
performing nitriding treatment on the first oxide film by adopting a decoupling plasma nitriding process so as to enable nitrogen ions to permeate into the first oxide film;
and oxidizing the silicon substrate at the first interface contact surface through oxidation annealing treatment to form a second oxide film, so that the second oxide film and the silicon substrate are in interface contact with a second interface contact surface.
2. The method for manufacturing a gate dielectric layer of a MOS device of claim 1, wherein the step of growing and forming a first oxide film on the silicon substrate comprises:
and growing and forming a first oxide film on the silicon substrate by an ISSG (silicon-on-glass) process.
3. The method for manufacturing a gate dielectric layer of a MOS device according to claim 2, wherein in the ISSG process, an ambient temperature for forming the first oxide film is: the ISSG process is carried out at 850-950 ℃ for 15-20 s.
4. The method for manufacturing a gate dielectric layer of a MOS device according to claim 1, wherein the step of performing nitridation processing on the first oxide film by using a decoupled plasma nitridation process to make the first oxide film permeate nitrogen ions comprises:
and performing nitriding treatment on the first oxide film by adopting a decoupling plasma nitriding process within the power range of 1800W to 2500W for 60s to 120s so that nitrogen ions permeate into the first oxide film.
5. The method for manufacturing a gate dielectric layer of a MOS device according to claim 1, wherein the step of oxidizing the silicon substrate located at the first interface contact surface by the oxidizing annealing treatment to form the second oxide film comprises:
and annealing and oxidizing for 10s to 20s in an environment with the temperature of 1100 ℃ to 1200 ℃, so that the silicon substrate positioned at the first interface contact surface is oxidized to form a second oxide film.
6. The method for manufacturing the gate dielectric layer of the MOS device as claimed in claim 1 or 5, wherein nitrogen and oxygen are introduced during the oxidation annealing treatment.
7. The method for manufacturing the gate dielectric layer of the MOS device according to claim 6, wherein the gas flow ratio of the nitrogen to the oxygen is as follows: 20: 6 to 20: 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011361953.2A CN112466748A (en) | 2020-11-27 | 2020-11-27 | Method for manufacturing gate dielectric layer of MOS device |
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| CN202011361953.2A CN112466748A (en) | 2020-11-27 | 2020-11-27 | Method for manufacturing gate dielectric layer of MOS device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000655A1 (en) * | 2021-07-21 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101124665A (en) * | 2005-02-25 | 2008-02-13 | 飞思卡尔半导体公司 | Method of making a nitrided gate dielectric |
| CN102456732A (en) * | 2010-10-19 | 2012-05-16 | 格科微电子（上海）有限公司 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof as well as CMOS (Complementary Metal Oxide Semiconductor) image sensor |
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2020
- 2020-11-27 CN CN202011361953.2A patent/CN112466748A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101124665A (en) * | 2005-02-25 | 2008-02-13 | 飞思卡尔半导体公司 | Method of making a nitrided gate dielectric |
| CN102456732A (en) * | 2010-10-19 | 2012-05-16 | 格科微电子（上海）有限公司 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof as well as CMOS (Complementary Metal Oxide Semiconductor) image sensor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000655A1 (en) * | 2021-07-21 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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Application publication date: 20210309 |