CN112463478A - Interface test method and device of circuit board and test equipment - Google Patents
Interface test method and device of circuit board and test equipment Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G06F11/00—Error detection; Error correction; Monitoring
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Abstract
The application provides a method and a device for testing an interface of a circuit board and a test device, which are used for more accurately detecting whether the interface of the circuit board has a fault condition to a certain extent. The application provides a method for testing an interface of a circuit board, which comprises the following steps: when a test task of an interface of a target circuit board is triggered, the test equipment receives simulation data issued by a server, wherein the simulation data is used for simulating input data acquired by the interface when the target equipment configuring the target circuit board provides equipment service; the test equipment inputs the analog data into the interface according to the communication connection configured between the test equipment and the interface; the test equipment acquires the response result of the target circuit board to the simulation data; and the test equipment determines whether the interface has an interface fault condition according to the response result of the simulation data.
Description
Technical Field
The present application relates to the field of testing, and in particular, to a method and an apparatus for testing an interface of a circuit board, and a testing device.
Background
After a Printed Circuit Boards (PCBs) are produced in a production shop, a testing process is generally performed to test the performance of the PCBs, to quantify the performance of the PCBs, and to check whether the PCBs have faults.
Taking an interface on a circuit board as an example, the interface can be subjected to circuit testing, and whether an internal circuit of the circuit board can be normally powered on or can be normally subjected to data transmission can be tested.
In the research process of the prior related art, the inventor finds that the interface fault still occurs after the circuit board interface which partially passes through the circuit test is actually applied or sold, and obviously, the test result measured by the prior circuit test mechanism has errors.
Disclosure of Invention
The application provides a method and a device for testing an interface of a circuit board and a test device, which are used for more accurately detecting whether the interface of the circuit board has a fault condition to a certain extent.
In a first aspect, the present application provides a method for testing an interface of a circuit board, the method including:
when a test task of an interface of a target circuit board is triggered, the test equipment receives simulation data issued by a server, wherein the simulation data is used for simulating input data acquired by the interface when the target equipment configuring the target circuit board provides equipment service;
the test equipment inputs the analog data into the interface according to the communication connection configured between the test equipment and the interface;
the test equipment acquires the response result of the target circuit board to the simulation data;
and the test equipment determines whether the interface has an interface fault condition according to the response result of the simulation data.
With reference to the first aspect of the present application, in a first possible implementation manner of the first aspect of the present application, the method further includes:
the test equipment carries out circuit test on the interface;
the test equipment acquires the response result of the target circuit board to the circuit test;
and the test equipment determines whether the interface has an interface fault condition according to the response result of the circuit test.
With reference to the first possible implementation manner of the first aspect of the present application, in a second possible implementation manner of the first aspect of the present application, when the test device determines that an interface fault does not exist in the interface according to a response result of the circuit test, the method further includes:
the test equipment sends a test request to the server to trigger the server to issue the simulation data.
With reference to the first aspect of the present application, in a third possible implementation manner of the first aspect of the present application, determining, by the test device, whether an interface fault condition exists in the interface according to a response result of the analog data includes:
the test equipment checks whether the data length of the data passed by the interface is consistent with the data length of the simulation data;
if not, the test equipment determines that the interface has an interface fault condition.
With reference to the first aspect of the present application, in a fourth possible implementation manner of the first aspect of the present application, the method further includes:
the test equipment tracks the test process;
and the test equipment outputs the tracking result obtained in the tracking process in the user interface.
With reference to the fourth possible implementation manner of the first aspect of the present application, in a fifth possible implementation manner of the first aspect of the present application, the method further includes:
and the test equipment sends the tracking result to the server so that the server performs test analysis according to the tracking result.
With reference to the first aspect of the present application, in a sixth possible implementation manner of the first aspect of the present application, the target device is a road test instrument device, the interface is an interface used for being connected with an automobile diagnostic system (On Board Diagnostics, OBD), a camera, a signal receiver, or a sensor, and the analog data is used for simulating data acquired by the OBD, the camera, the signal receiver, or the sensor.
In a second aspect, the present application provides an interface testing apparatus for a circuit board, the apparatus comprising:
the device comprises a receiving unit, a processing unit and a processing unit, wherein the receiving unit is used for receiving simulation data issued by a server when a test task of an interface of a target circuit board is triggered, and the simulation data is used for simulating input data acquired by a target device configured with the target circuit board through the interface when the device service is provided;
the input unit is used for inputting the analog data into the interface according to the communication connection configured between the input unit and the interface;
the acquisition unit is used for acquiring the response result of the target circuit board to the analog data;
and the determining unit is used for determining whether the interface has the interface fault condition according to the response result of the analog data.
With reference to the second aspect of the present application, in a first possible implementation manner of the second aspect of the present application, the apparatus further includes a circuit testing unit, configured to:
carrying out circuit test on the interface;
an acquisition unit, further configured to:
collecting a response result of the target circuit board to the circuit test;
a determination unit further configured to:
and determining whether the interface has an interface fault condition according to the response result of the circuit test.
With reference to the first possible implementation manner of the second aspect of the present application, in a second possible implementation manner of the second aspect of the present application, the apparatus further includes a sending unit, when the test device determines that the interface has no interface fault condition according to a response result of the circuit test, the sending unit is configured to:
and sending a test request to the server to trigger the server to issue the simulation data.
With reference to the second aspect of the present application, in a third possible implementation manner of the second aspect of the present application, the determining unit is specifically configured to:
checking whether the data length of the data passed by the interface is consistent with the data length of the simulation data;
if not, determining that the interface has an interface fault condition.
With reference to the second aspect of the present application, in a fourth possible implementation manner of the second aspect of the present application, the apparatus further includes a tracking unit, configured to:
tracking the test process;
an output unit for:
and outputting a tracking result obtained in the tracking process in the user interface.
With reference to the fourth possible implementation manner of the second aspect of the present application, in a fifth possible implementation manner of the second aspect of the present application, the apparatus further includes a sending unit, configured to:
and sending the tracking result to a server so that the server performs test analysis according to the tracking result.
With reference to the second aspect of the present application, in a sixth possible implementation manner of the second aspect of the present application, the target device is a road test instrument device, the interface is an interface used for being connected with an OBD, a camera, a signal receiver, or a sensor, and the analog data is used for simulating data acquired by the OBD, the camera, the signal receiver, or the sensor.
In a third aspect, the present application provides a testing device, including a processor and a memory, where the memory stores a computer program, and the processor executes the method provided in the first aspect of the present application or any one of the possible implementation manners of the first aspect of the present application when calling the computer program in the memory.
In a fourth aspect, the present application provides a computer-readable storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the method provided in the first aspect of the present application or any one of the possible implementations of the first aspect of the present application.
From the above, the present application has the following advantageous effects:
aiming at the interface test of the circuit board, a cloud test scene is established, the test equipment receives the simulation data sent by the server, the simulation data is used for simulating input data acquired by a target device for configuring a target circuit board through an interface of the circuit board when the device service is provided, the test device inputs the simulation data into the interface according to communication connection configured between the test device and the interface, and collecting the response result of the target circuit board to the simulation data, thereby determining whether the interface has interface fault condition according to the response result, under the test scene, the server flexibly configures the simulation data according to the requirement, detects whether the interface fault condition exists in the target circuit board from the software perspective, particularly, whether the interface fault condition which cannot be detected by the circuit test exists in the target circuit board can be detected, and the detection precision is better to a certain extent.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of a method for testing an interface of a circuit board according to the present application;
FIG. 2 is a schematic flow chart illustrating a method for testing an interface of a circuit board according to the present application;
FIG. 3 is a schematic structural diagram of an interface testing apparatus of a circuit board according to the present application;
fig. 4 is a schematic structural diagram of the testing apparatus of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Moreover, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus. The naming or numbering of the steps appearing in the present application does not mean that the steps in the method flow have to be executed in the chronological/logical order indicated by the naming or numbering, and the named or numbered process steps may be executed in a modified order depending on the technical purpose to be achieved, as long as the same or similar technical effects are achieved.
The division of the modules presented in this application is a logical division, and in practical applications, there may be another division, for example, multiple modules may be combined or integrated into another system, or some features may be omitted, or not executed, and in addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, and the indirect coupling or communication connection between the modules may be in an electrical or other similar form, which is not limited in this application. The modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in a plurality of circuit modules, and some or all of the modules may be selected according to actual needs to achieve the purpose of the present disclosure.
First, before the present application is introduced, the relevant contents of the present application with respect to the application background will be described.
The interface testing method and device of the circuit board and the computer readable storage medium can be applied to testing equipment and used for detecting whether the interface of the circuit board has a fault condition to a certain extent more accurately.
The execution main body of the interface test method of the circuit board can be an interface test device of the circuit board or a test device integrated with the interface test device of the circuit board. The interface testing device of the circuit board can be realized in a hardware or software mode.
Next, the interface test method of the circuit board provided by the present application is described.
First, referring to fig. 1, fig. 1 shows a schematic flow chart of a method for testing an interface of a circuit board according to the present application, where the method for testing an interface of a circuit board according to the present application may specifically include the following steps:
step S101, when a test task of an interface of a target circuit board is triggered, a test device receives simulation data issued by a server, wherein the simulation data is used for simulating input data acquired by the interface when the target device configured with the target circuit board provides device services;
step S102, the test equipment inputs the simulation data into the interface according to the communication connection configured between the test equipment and the interface;
step S103, the test equipment collects the response result of the target circuit board to the simulation data;
and step S104, the test equipment determines whether the interface has an interface fault condition according to the response result of the simulation data.
As can be seen from the embodiment shown in fig. 1, for the interface test of the circuit board, the present application establishes a cloud test scenario, the test device receives the simulation data sent by the server, the simulation data is used to simulate the input data obtained by the target device configured with the target circuit board through the interface of the circuit board when providing the device service, the test device inputs the simulation data into the interface according to the communication connection configured between itself and the interface, and collects the response result of the target circuit board to the simulation data, thereby determining whether the interface has an interface fault condition according to the response result, in the test scenario, the server flexibly configures the simulation data according to the needs, and from the software perspective, detects whether the target circuit board has an interface fault condition, and particularly detects whether the target circuit board has an interface fault condition that cannot be detected by the circuit test, and the detection precision is better to a certain extent.
It can be understood that the circuit boards are generally produced in batches, once problems are found and rework is needed, the circuit boards are called back in a large amount, huge loss is caused to a production company of the circuit boards, and consumption of a large amount of manpower and material resources exists.
The steps of the embodiment shown in fig. 1 and the possible implementation manner thereof in practical applications are described in detail below.
In the present application, the test task for the interface of the target circuit board may be specifically triggered by the test device, or may also be triggered by the server.
For example, when a worker initiates a test at a test device, the communication connection between the test device and an interface of a target circuit board may be configured locally at the test device, and the test device triggers a test task for the interface of the target circuit board through user operation, and then initiates a test request to a server, triggering the server to issue simulation data.
Or after the working personnel configures the communication connection between the testing equipment and the interface of the target circuit board locally in the testing equipment, the server is triggered to send the simulation data through the cloud platform, and at the moment, after the testing equipment receives the simulation data sent by the server, the testing task of the interface of the target circuit board can be triggered.
Of course, the specific triggering mode of the test task may be adjusted according to actual needs, and is not limited herein.
Wherein, it should be understood that the interface of the target circuit board exists in the form of hardware entity, and the specific structural form of the interface can be adjusted according to the actual need; and the communication connection between the test equipment and the interface of the target circuit board is also a communication connection configured in a wired connection mode.
The analog data is corresponding to the target circuit board. In the present application, the target circuit board, when configured on the target device, may implement a specific service function thereof to provide a device service, and the simulation data is data configured for performing service simulation and service simulation for data that may be transmitted at an interface of the target circuit board in actual application of the service function or the device service, so that when the simulation data is input to the interface of the target circuit board, a real application scene of the target circuit board or the target device may be restored.
After the analog data are input into the interface of the target circuit board, the response of the target circuit board to the analog data on the software level can be collected, whether the response result is matched with the preset and normal response result or not is determined, and if the response result is matched with the preset and normal response result, the interface fault condition does not exist; if not, the interface fault condition of the interface can be judged.
For example, whether an interface failure condition exists may be determined based on the data length. It can be understood that if there is a fault condition in the interface, the data passing through the interface may cause conditions such as code confusion and packet loss, and the data itself is changed, which may affect the data length of the data.
Therefore, the test equipment can check whether the data length of the data passed by the interface is consistent with the data length of the simulation data;
if not, the test equipment determines that the interface has an interface fault condition.
The test equipment can be in communication connection with both ends of the interface of the target circuit board, so that data of analog data passing through the interface can be directly read.
Or, if the target circuit board is provided with the processor, the data transmitted to the processor after the analog data passes through the interface of the target circuit board can be read from the processor.
After determining whether the interface of the target circuit board has the interface fault condition, the test equipment may generate a test result, where the test result may indicate whether the interface of the target circuit board has the interface fault condition, and further may indicate the content, such as the interface fault reason, obtained according to the analysis of the response result.
In order to provide more powerful data support and obtain richer test results, the test equipment can also track the test process of a local test task, for example, the whole test process is restored from the initiation of the test task and the passing of simulation data from the server to an interface of a target circuit board through the test equipment.
The obtained tracking data is tracked, and the testing equipment can also output the tracking data in the user interface of the testing equipment, so that a worker in front of the user interface can visually check the testing process and the testing result of the testing task, and the control processing such as manual intervention is facilitated.
It is easy to understand that the test device itself may have a display screen to output the user interface, or the test device may also have an external display or a device with a display screen to output the user interface.
Further, it has been mentioned above that, the test mechanism of the present application is implemented on the basis of the cloud test scenario set up in the present application, and the cloud test scenario can also specifically implement full link tracking of each test task, so that the test device can also report to the server after obtaining the tracking data, and the server stores the tracking data. And on the server side, the test analysis can be carried out based on the tracking data of the test task, even based on the tracking data of a plurality of test tasks, the effect of test quality analysis is achieved, a feedback mechanism is formed, the test mechanism can be adjusted or optimized according to the test analysis result, and data support and data guarantee are provided for the interface test of the circuit board.
For the purpose of understanding the present application, reference is made to the following description by way of an example of an application.
Illustratively, the target circuit board is configured to be configured on a road test instrument device, where the target device is a road test instrument device, and the interface of the target circuit board is an interface for connecting the road test instrument device with an OBD, a camera, a signal receiver, or a sensor.
The road test instrument equipment relates to a driving test scene, and the vehicle state of an examiner when driving a vehicle is acquired so as to automatically or under the cooperation of workers to determine whether the examiner normally drives the vehicle or not and whether the vehicle can be driven for test or not.
The OBD is an automobile vehicle-mounted diagnosis system which can acquire the working states of automobile components such as automobile speed, tire rotating speed, automobile horn, automobile left turn lamp, automobile fog lamp and the like;
the camera, the signal receiver or the sensor is a component configured for collecting the driving state information of the vehicle from the examiner in the driving examination scene, and the camera can be arranged in the vehicle or at any position on the surface of the vehicle and is used for collecting videos; the signal receiver can be matched with a specific signal transmitter of a driving test site to determine whether the vehicle is normally stored in a garage or not and determine the vehicle driving state specified by the driving test; the sensors are similar to the signal receivers and are used for collecting the driving state of the vehicle involved in driving test in the driving test scene.
Correspondingly, the analog data sent by the server is data collected by an analog OBD, a camera, a signal receiver or a sensor.
Furthermore, the test device can test the interface of the target circuit board in a software layer, and can also test the interface of the target circuit board in a hardware layer, that is, a circuit test is performed to monitor whether the interface of the target circuit board has an interface fault condition in the hardware layer.
The circuit test is performed from a hardware level, for example, whether the pins of the interface can conduct electricity normally, whether the pins are intact, whether the resistance of the pins is within a normal range, whether the working voltage of the pins is normal, whether the interface appearance is normal, whether the circuit connection relationship is normal, and the like can be detected.
The test content related to the circuit test can be not only the test content of the circuit test in the existing test mechanism, but also other test content, and can be specifically adjusted according to actual needs, and the test can be triggered from a hardware level.
Correspondingly, the interface testing method for the circuit board provided by the present application, as shown in fig. 2, another flow diagram of the interface testing method for the circuit board of the present application, may further include the following steps:
step S201, the test equipment carries out circuit test on the interface;
step S202, the test equipment collects the response result of the target circuit board to the circuit test;
step S203, the test equipment determines whether the interface has an interface fault condition according to the response result of the circuit test.
In addition, for circuit testing, it may also perform tracking of the testing process as in software level testing, and form tracking data, and for processing of the tracking data, for example, output in the user interface or report to the server, refer to the foregoing contents, and details are not described herein.
In yet another implementation, the interface test implemented in the software layer as described in the above application may also be triggered by a circuit test in the hardware layer in practical applications.
It can be understood that if an interface of the target circuit board has an interface fault condition on a hardware level, the interface fault condition is often generated on a software level along with the interface of the target circuit board; if the interface of the target circuit board has an interface fault condition in the software layer, the interface of the target circuit board does not necessarily have an interface fault condition in the software layer.
Therefore, the interface test of the software layer, or the far-end test mechanism, provided by the application can be triggered to test when the interface of the target circuit board passes through the circuit test of the hardware layer, so that certain communication cost is saved, and meanwhile, the test of the software layer also has higher pertinence, and is more convenient for relevant test analysis especially for the interface fault condition which cannot be tested by the circuit test of the hardware layer.
Correspondingly, when the test equipment determines that the interface does not have the interface fault condition according to the response result of the circuit test, the test equipment can send a test request to the server to trigger the server to issue the simulation data.
The above is the introduction of the interface test method of the circuit board provided by the present application, and in order to better implement the interface test method of the circuit board provided by the present application, the present application also provides an interface test device of the circuit board.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an interface testing apparatus of a circuit board according to the present application, in which the interface testing apparatus 300 of the circuit board may specifically include the following structure:
a receiving unit 301, configured to receive, by a test device, analog data issued by a server when a test task for an interface of a target circuit board is triggered, where the analog data is used to simulate input data acquired through the interface when a target device configured with the target circuit board provides a device service;
an input unit 302 for inputting analog data into the interface according to a communication connection configured between itself and the interface;
the acquisition unit 303 is used for acquiring a response result of the target circuit board to the analog data;
and the determining unit 304 is configured to determine whether an interface failure condition exists in the interface according to a response result of the analog data.
In an exemplary implementation, the apparatus further comprises a circuit test unit 305 for:
carrying out circuit test on the interface;
an acquisition unit 303, further configured to:
collecting a response result of the target circuit board to the circuit test;
the determining unit 304 is further configured to:
and determining whether the interface has an interface fault condition according to the response result of the circuit test.
In yet another exemplary implementation manner, the apparatus further includes a sending unit 306, when it is determined that the interface has no interface fault condition according to the response result of the circuit test, configured to:
and sending a test request to the server to trigger the server to issue the simulation data.
In another exemplary implementation manner, the determining unit 304 is specifically configured to:
checking whether the data length of the data passed by the interface is consistent with the data length of the simulation data;
if not, determining that the interface has an interface fault condition.
In yet another exemplary implementation, the apparatus further comprises a tracking unit 307 configured to:
tracking the test process;
an output unit 308 for:
and outputting a tracking result obtained in the tracking process in the user interface.
In yet another exemplary implementation, the apparatus further includes a sending unit 306, configured to:
and sending the tracking result to a server so that the server performs test analysis according to the tracking result.
In yet another exemplary implementation manner, the target device is a road test instrument device, the interface is an interface for connecting with an OBD, a camera, a signal receiver, or a sensor, and the analog data is used for simulating data collected by the OBD, the camera, the signal receiver, or the sensor.
The present application further provides a testing device, referring to fig. 4, fig. 4 shows a schematic structural diagram of the testing device of the present application, specifically, the testing device of the present application may include a processor 401, a memory 402, and an input/output device 403, where when the processor 401 is used to execute a computer program stored in the memory 402, each step of the interface testing method of the circuit board in any embodiment corresponding to fig. 1 and fig. 2 is implemented; alternatively, the processor 401 is configured to implement the functions of the units in the embodiment corresponding to fig. 3 when executing the computer program stored in the memory 402, and the memory 402 is configured to store the computer program required by the processor 401 to execute the interface testing method for the circuit board in any embodiment corresponding to fig. 1 and fig. 2.
Illustratively, a computer program may be partitioned into one or more modules/units, which are stored in memory 402 and executed by processor 401 to accomplish the present application. One or more modules/units may be a series of computer program instruction segments capable of performing certain functions, the instruction segments being used to describe the execution of a computer program in a computer device.
The test equipment may include, but is not limited to, a processor 401, a memory 402, and input-output devices 403. It will be appreciated by those skilled in the art that the illustration is merely an example of a test device and does not constitute a limitation of a test device and may include more or less components than those illustrated, or some components may be combined, or different components, for example, the test device may also include a network access device, bus, etc. through which the processor 401, memory 402, input output device 403, and network access device, etc. are connected.
The Processor 401 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center for the test equipment and connecting the various parts of the overall equipment using various interfaces and lines.
The memory 402 may be used to store computer programs and/or modules, and the processor 401 may implement various functions of the computer device by running or executing the computer programs and/or modules stored in the memory 402 and invoking data stored in the memory 402. The memory 402 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to use of the test equipment, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
The processor 401, when executing the computer program stored in the memory 402, may specifically implement the following functions:
when a test task of an interface of a target circuit board is triggered, receiving simulation data issued by a server, wherein the simulation data is used for simulating input data acquired by a target device configured with the target circuit board through the interface when the device service is provided;
inputting analog data into the interface according to communication connection configured between the interface and the self;
collecting a response result of the target circuit board to the simulation data;
and determining whether the interface has an interface fault condition according to the response result of the simulation data.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the interface testing apparatus and the testing device of the circuit board and the corresponding units thereof described above may refer to the description of the interface testing method of the circuit board in any embodiment corresponding to fig. 1 and fig. 2, and are not described herein again in detail.
It will be understood by those skilled in the art that all or part of the steps of the methods of the above embodiments may be performed by instructions or by associated hardware controlled by the instructions, which may be stored in a computer readable storage medium and loaded and executed by a processor.
Therefore, the present application provides a computer-readable storage medium, in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute steps in the interface testing method of the circuit board in any embodiment corresponding to fig. 1 and fig. 2 in the present application, and specific operations may refer to descriptions of the interface testing method of the circuit board in any embodiment corresponding to fig. 1 and fig. 2, which are not described herein again.
Wherein the computer-readable storage medium may include: read Only Memory (ROM), Random Access Memory (RAM), magnetic or optical disks, and the like.
Since the instructions stored in the computer-readable storage medium can execute the steps in the method for testing the interface of the circuit board in any embodiment of the present application, such as that shown in fig. 1 and fig. 2, the beneficial effects that can be achieved by the method for testing the interface of the circuit board in any embodiment of the present application, such as that shown in fig. 1 and fig. 2, can be achieved, for details, see the foregoing description, and are not repeated herein.
The method, the device, the testing equipment and the computer-readable storage medium for testing the interface of the circuit board provided by the present application are introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A method for testing an interface of a circuit board, the method comprising:
when a test task of an interface of a target circuit board is triggered, a test device receives simulation data issued by a server, wherein the simulation data is used for simulating input data acquired through the interface when the target device configuring the target circuit board provides device services;
the test equipment inputs the simulation data into the interface according to communication connection configured between the test equipment and the interface;
the test equipment acquires a response result of the target circuit board to the simulation data;
and the test equipment determines whether the interface has an interface fault condition according to the response result of the simulation data.
2. The method of claim 1, further comprising:
the test equipment performs circuit test on the interface;
the test equipment acquires a response result of the target circuit board to the circuit test;
and the test equipment determines whether the interface has an interface fault condition according to the response result of the circuit test.
3. The method of claim 2, wherein when the test equipment determines from the response results of the circuit test that an interface fault condition does not exist for the interface, the method further comprises:
and the test equipment sends a test request to the server to trigger the server to issue the simulation data.
4. The method of claim 1, wherein determining, by the test device, whether an interface fault condition exists at the interface based on the response result of the simulation data comprises:
the test equipment checks whether the data length of the data passed by the interface is consistent with the data length of the simulation data;
if not, the test equipment determines that the interface has an interface fault condition.
5. The method of claim 1, further comprising:
the test equipment tracks a test process;
and the test equipment outputs a tracking result obtained in the tracking process in a user interface.
6. The method of claim 5, further comprising:
and the test equipment sends the tracking result to the server so that the server performs test analysis according to the tracking result.
7. The method of claim 1, wherein the target device is a road test equipment device, the interface is an interface for connecting with an automotive diagnostic system (OBD), a camera, a signal receiver, or a sensor, and the simulation data is used for simulating data collected by the OBD, the camera, the signal receiver, or the sensor.
8. An interface testing apparatus for a circuit board, the apparatus comprising:
the device comprises a receiving unit, a processing unit and a processing unit, wherein the receiving unit is used for receiving simulation data issued by a server when a test task of an interface of a target circuit board is triggered, and the simulation data is used for simulating input data acquired by a target device configured with the target circuit board through the interface when the device service is provided;
the input unit is used for inputting the analog data into the interface according to communication connection configured between the input unit and the interface;
the acquisition unit is used for acquiring a response result of the target circuit board to the simulation data;
and the determining unit is used for determining whether the interface has an interface fault condition according to the response result of the analog data.
9. A test device comprising a processor and a memory, the memory having stored therein a computer program, the processor when calling the computer program in the memory performing the method of any of claims 1 to 7.
10. A computer-readable storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the method of any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011290125.4A CN112463478A (en) | 2020-11-17 | 2020-11-17 | Interface test method and device of circuit board and test equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011290125.4A CN112463478A (en) | 2020-11-17 | 2020-11-17 | Interface test method and device of circuit board and test equipment |
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| CN112463478A true CN112463478A (en) | 2021-03-09 |
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| CN202011290125.4A Pending CN112463478A (en) | 2020-11-17 | 2020-11-17 | Interface test method and device of circuit board and test equipment |
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