CN112463110B - Method and device for identifying empty and full working states of asynchronous FIFO (first in first out) and readable storage medium - Google Patents
Method and device for identifying empty and full working states of asynchronous FIFO (first in first out) and readable storage medium Download PDFInfo
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Abstract
The application discloses a method and a device for identifying an empty and full working state of an asynchronous FIFO (first in first out) and a computer readable storage medium. The method comprises the step of respectively defining a full state used for indicating the working state of the asynchronous FIFO and an empty state used for indicating the working state of the asynchronous FIFO in advance based on the actual clock frequency of a clock domain where a read-write pointer is located, a read bit corresponding to a read-write pointer generation mode and the state when the read bit does not reach the storage bit width. Calculating the residual read bits or the residual writable bits in the asynchronous FIFO, and if the residual read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0, generating the information that the working state of the asynchronous FIFO is a to-be-empty state; and if the remaining writable bits in the asynchronous FIFO are less than or equal to the preset threshold and greater than 0, generating the information that the working state of the asynchronous FIFO is the full state. The method and the device can accurately judge whether the asynchronous FIFO reaches the working empty-full state, not only can effectively reduce the probability of the problem that the FIFO works and makes mistakes due to the working empty-full state of the asynchronous FIFO, but also can not increase the system overhead.
Description
Technical Field
The present disclosure relates to the field of circuit design technologies, and in particular, to a method and an apparatus for identifying an empty/full working state of an asynchronous FIFO, and a computer readable storage medium.
Background
A FIFO (First In First Out) circuit is a memory device capable of realizing data First In First Out, and is generally used as a data buffer. The FIFO device working under the multi-clock domain system is called as asynchronous FIFO, and the asynchronous FIFO can well solve the problem that the input and output data of the data under the multi-clock domain system are difficult to match. Therefore, the interface is often used as a data transmission interface for storing and buffering data between two asynchronous clock domains in a multi-clock domain system, and as a reliable interface between the asynchronous clock domains, and has wide application in large-scale integrated circuit design.
The standard structure of the asynchronous FIFO comprises a storage module, a write pointer generation module, a read pointer generation module, a status bit generation module and a pointer comparison module, and fig. 1 is a schematic diagram of a structural framework of the asynchronous FIFO. As shown in fig. 1, the storage module is a main module for data storage, and has different storage capacities according to different storage requirements. The storage module controls data input to different storage positions based on the write pointer, and controls data at different positions to be output through the read pointer. And the write pointer generation module is used for generating write pointers aiming at different bits according to the depth of the storage module through the write clock control of the write clock domain and indicating the input of write data. When the full status generated by the status bit indicates valid, the write pointer generation module should pause and stop writing. And the read pointer generating module generates read pointers aiming at different bits according to the depth of the storage module through read clock control of a read clock domain and indicates data reading. When the empty status generated by the status bit indicates valid, the read pointer generation module should pause and stop reading. The logic of the pointer comparison module and the state bit generation module is interdependent, the states of the read pointer and the write pointer are compared through corresponding algorithms to generate different state bits, and an empty state effective bit or a full state effective bit is output.
The pointer comparison module has several algorithms, and the read-write pointer is expressed with Gray code for comparison and calculation. A common method for avoiding the error problem caused by the empty/full state is to change the definition of the empty/full state, i.e. to reserve an additional valid unit in the empty/full state, and to determine that the empty/full state is empty or full when the valid unit is not actually empty or full but is empty or full when the reserved valid unit is reached. However, although this approach can avoid the error caused by the empty-full state, it will cause a valid cell not to be read or written, and needs additional detection mechanism logic to repair, resulting in larger overhead.
Disclosure of Invention
The application provides a method and a device for identifying the empty and full working states of asynchronous FIFO and a computer readable storage medium, which can effectively reduce the probability of the problem of FIFO working errors caused by the empty and full working states of the asynchronous FIFO and can not increase the system overhead.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
an embodiment of the present invention provides a method for identifying an empty/full operating state of an asynchronous FIFO, including:
defining a full state and an empty state of a read bit corresponding to a read-write pointer generation mode and a state when the storage bit width is not reached on the basis of the actual clock frequency of a clock domain where the read-write pointer is located in advance; the full state is used for indicating that the asynchronous FIFO is to be in a working full state, and the empty state is used for indicating that the asynchronous FIFO is to be in a working empty state;
calculating the residual read bits or the residual writable bits in the asynchronous FIFO;
if the residual reading bit in the asynchronous FIFO is less than or equal to a preset threshold and greater than 0, generating the information that the working state of the asynchronous FIFO is a to-be-empty state;
and if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating the information that the working state of the asynchronous FIFO is a to-be-full state.
Optionally, the state definition of the read bit corresponding to the read-write pointer generation mode and the state definition of the read bit not reaching the storage bit width, based on the actual clock frequency of the clock domain where the read-write pointer is located in advance, includes a full state and an empty state:
if and only if the actual clock frequency of the clock domain where the write pointer is located is higher than the clock frequency of the clock domain where the read pointer is located, the written bit corresponding to the write pointer generation mode is larger than the read bit corresponding to the read pointer, and the state when the storage bit width is not reached is defined as the to-be-empty state;
and if and only if the actual clock frequency of the clock domain where the read pointer is located is higher than the actual clock frequency of the clock domain where the write pointer is located, the read bit corresponding to the read pointer generation mode is larger than the write bit corresponding to the write pointer, and the state when the storage bit width is not reached is defined as the to-full state.
Optionally, the calculating process of the actual clock frequency includes:
if an effective clock signal occurs every a null periods during the propagation process, the actual clock frequency f t Is f t = f/(1 + a); f is the clock frequency;
if the proportion of the effective propagation to the total period in the periodic propagation is b, the actual clock frequency f t Is f t = f × b; f is the clock frequency;
if the proportion of the time of the effective enabling signal of the clock in the whole transmission process is c, the actual clock frequency f t Is f t = f × c; f is the clock frequency.
Optionally, the calculating process of the actual clock frequency includes:
if an effective clock signal occurs every a null periods in the transmission process, and the proportion of effective transmission in the periodic transmission to the total period is b, the actual clock frequency is calculated based on the least common multiple of a and 1/b and the clock frequency;
if an effective clock signal occurs every a null period in the transmission process, and the proportion of the effective enabling signal of the clock in the transmission process to the time of the whole transmission is c, the least common multiple of the actual clock frequency a and 1/c and the clock frequency are calculated;
if the proportion of effective propagation in the periodic propagation to the total period is b, and the proportion of time of an effective enabling signal of a clock to the whole transmission in the propagation process is c, calculating the actual clock frequency based on the least common multiple of b and c and the clock frequency;
if an effective clock signal occurs every a null cycles in the propagation process, the proportion of the effective propagation in the total cycle in the periodic propagation is b, and the proportion of the effective enabling signal of the clock in the propagation process in the whole transmission time is c, the actual clock frequency is calculated based on the least common multiple of a, 1/b and 1/c and the clock frequency.
Optionally, before the remaining read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0, the method further includes:
calculating actual clock frequencies of a high clock frequency and a low clock frequency of the asynchronous clock domain;
and calculating the preset threshold according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency and the number of synchronous registers used for degrading the metastable state influence.
Optionally, the calculating the preset threshold according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency, and the number of synchronization registers used for degrading the metastable state influence includes:
calling a threshold calculation relation to calculate the preset threshold, wherein the threshold calculation relation is as follows:
wherein Th is the preset threshold, ceil represents rounding up, f tf Actual clock frequency, f, being said high clock frequency f For said high clock frequency, f ts Rt is the number of synchronous registers used to degrade the meta-stability effect for the actual clock frequency of the low clock frequency.
Another aspect of the embodiments of the present invention provides an apparatus for identifying an empty/full operating state of an asynchronous FIFO, including:
the state self-defining module is used for defining a full state and an empty state in advance based on the actual clock frequency of the clock domain where the read-write pointer is located and the states of the read bit corresponding to the read-write pointer generation mode and the read bit not reaching the storage bit width; the full state is used for indicating that the asynchronous FIFO is to be in a working full state, and the empty state is used for indicating that the asynchronous FIFO is to be in a working empty state;
the calculation module is used for calculating the residual read bits or the residual writable bits in the asynchronous FIFO;
a status indication information generating module, configured to generate information that the working status of the asynchronous FIFO is to be empty if the remaining read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0; and if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating the information that the working state of the asynchronous FIFO is a to-be-full state.
Optionally, the state customization module includes:
a null state definition submodule, configured to define a state in which a written bit corresponding to the write pointer generation mode is greater than a read bit corresponding to the read pointer and a storage bit width is not reached as the null state if and only if the actual clock frequency of the clock domain in which the write pointer is located is higher than the clock frequency of the clock domain in which the read pointer is located;
and the full state definition submodule is used for defining the state as the full state when the read pointer generates a read bit which is larger than a written bit which corresponds to the write pointer and does not reach the storage bit width if and only if the actual clock frequency of the clock domain where the read pointer is positioned is higher than the actual clock frequency of the clock domain where the write pointer is positioned.
The embodiment of the present invention further provides an empty and full working state identification apparatus for an asynchronous FIFO, including a processor, where the processor is configured to implement the steps of the method for identifying an empty and full working state of an asynchronous FIFO when executing a computer program stored in a memory.
Finally, an embodiment of the present invention provides a computer-readable storage medium, where an empty and full operation state identification program of an asynchronous FIFO is stored on the computer-readable storage medium, and when the empty and full operation state identification program of the asynchronous FIFO is executed by a processor, the method for identifying an empty and full operation state of an asynchronous FIFO is implemented as any one of the foregoing steps.
The technical scheme provided by the application has the advantages that the two states of the asynchronous FIFO which are about to reach the empty working state and the full working state are predefined, whether the asynchronous FIFO is empty or full is judged in real time by calculating the residual reading bit and the residual writable bit in the asynchronous FIFO and comparing the numerical relation between the residual reading bit and the residual writable bit and the preset threshold value, so that whether the current working state of the asynchronous FIFO reaches the empty-full state or not can be accurately judged, the problem probability that the FIFO works and goes wrong due to the empty-full state of the asynchronous FIFO can be effectively reduced, the resource utilization rate and the circuit stability are improved, the whole implementation process is simple, reliable and efficient, and the system overhead cannot be increased. According to the obtained to-empty and to-full states, the correct work of the FIFO can be protected, the maximum utilization rate of the circuit performance can be achieved, and the added logic required by combining the pointer generation mode of the FIFO per se is minimized.
In addition, the embodiment of the invention also provides a corresponding implementation device and a computer readable storage medium for the method for identifying the empty and full working states of the asynchronous FIFO, so that the method has higher practicability, and the device and the computer readable storage medium have corresponding advantages.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the related art, the drawings required to be used in the description of the embodiments or the related art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of a standard architectural framework for an asynchronous FIFO according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a method for identifying an empty/full working state of an asynchronous FIFO according to an embodiment of the present invention;
FIG. 3 is a block diagram of an asynchronous FIFO according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a logic implementation of the pointer comparison module of FIG. 3 according to an embodiment of the present invention;
fig. 5 is a structural diagram of an embodiment of an apparatus for identifying an empty/full operating state of an asynchronous FIFO according to an embodiment of the present invention;
fig. 6 is a block diagram of another embodiment of an apparatus for identifying an empty/full operating state of an asynchronous FIFO according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and claims of this application and in the foregoing drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
In common asynchronous circuit work, in order to judge whether the working state of an asynchronous FIFO is empty or will be full, the reading and writing states of the FIFO need to be counted, a triggering threshold value is set, and when the working state of the asynchronous FIFO is empty or will be full, the triggering is carried out to send information such as Error and the like so as to terminate the work. According to the method and the device, the empty state and the full state are judged, the state machine is used for automatically carrying out targeted processing, the empty state and the full state are avoided, and the requirement for normal work of a circuit is met. Various non-limiting embodiments of the present application are described in detail below.
Referring to fig. 2, fig. 2 is a schematic flow chart of a method for identifying an empty/full working state of an asynchronous FIFO according to an embodiment of the present invention, where the embodiment of the present invention may include the following:
s201: and defining a full state and an empty state of the read bit corresponding to the read-write pointer generation mode and the state of the read bit not reaching the storage bit width in advance based on the actual clock frequency of the clock domain where the read-write pointer is located.
In this step, the full state may be used to indicate that the asynchronous FIFO will be in a working full state, and the empty state may be used to indicate that the asynchronous FIFO will be in a working empty state. That is, if the asynchronous FIFO is in the near-full state, indicating that the asynchronous FIFO is soon to enter the full operation state, some measures may be taken to prevent the asynchronous FIFO from entering the full state. If the asynchronous FIFO is in the idle state, it indicates that the asynchronous FIFO is about to enter the idle state immediately, and measures can be taken to prevent the asynchronous FIFO from entering the idle state. The generation of the full state is based on different read-write pointer generation modes, and different judgment modes exist, but the judgment definitions are the same. The definition of the null state may be: and if and only if the actual clock frequency of the clock domain where the read pointer is located is higher than the actual clock frequency of the clock domain where the write pointer is located, the read bit corresponding to the read pointer generation mode is larger than the write bit corresponding to the write pointer, and the state definition does not reach the storage bit width. The full state may be defined as: and if and only if the actual clock frequency of the clock domain where the write pointer is located is higher than the clock frequency of the clock domain where the read pointer is located, the written bit corresponding to the write pointer generation mode is larger than the read bit corresponding to the read pointer, and the state of the memory bit width is not reached.
S202: the remaining read bits or the remaining writeable bits in the asynchronous FIFO are counted.
It will be appreciated that the empty state or the full state is directed to the fast clock domain in the asynchronous clock domain, and that the full state only occurs when the write clock frequency is higher than the read clock frequency. Conversely, when the read clock frequency is higher than the write clock frequency, only the going to empty state will occur. In other words, either the calculated remaining read bits or the calculated remaining writeable bits are calculated in this step. And under different system working conditions, when the residual readable or writable position of the asynchronous FIFO judged by the read pointer or the write pointer is less than or equal to the empty or full state and the empty or full state is not reached, judging that the asynchronous FIFO is in the empty or full state. The skilled person can set the threshold value in advance according to the actual application scenario, and can also calculate the threshold value before the steps S203 and S204, which does not affect the implementation of the present application.
S203: and if the residual reading bits in the asynchronous FIFO are less than or equal to the preset threshold and greater than 0, generating the information that the working state of the asynchronous FIFO is the to-be-empty state.
S204: and if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating the information that the working state of the asynchronous FIFO is the full state.
After the remaining read bits or the remaining writable bits in the asynchronous FIFO are obtained by calculation, for example, by gray code or other means in S202, it can be known whether the asynchronous FIFO will be in an empty state or a full state based on a numerical relationship between the remaining read bits and a preset threshold, a set signal can be preset, if the remaining read bits in the asynchronous FIFO are less than or equal to the preset threshold and greater than 0, a set signal that the working state of the asynchronous FIFO is in an empty state is generated, the empty bits are valid by the asynchronous FIFO, and the asynchronous FIFO enters the empty state; and if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating a set signal that the working state of the asynchronous FIFO is a full state, enabling the full set of the asynchronous FIFO, and enabling the asynchronous FIFO to enter the full state.
In the technical scheme provided by the embodiment of the invention, two states of an idle working state and a full working state of the asynchronous FIFO are predefined, and whether the asynchronous FIFO is empty or full is judged in real time by calculating the residual reading bit and the residual writable bit in the asynchronous FIFO and comparing the numerical relationship between the residual reading bit and the residual writable bit and a preset threshold value, so that the working idle-full state of the asynchronous FIFO can be accurately judged, the probability of the problem of FIFO working errors caused by the working idle-full state of the asynchronous FIFO can be effectively reduced, the resource utilization rate and the circuit stability are improved, the whole implementation process is simple, reliable and efficient, and the system overhead can not be increased. According to the obtained status of going to be empty and full, the correct operation of the FIFO can be protected, the maximum utilization rate of the circuit performance can be achieved, and the added logic required by combining the pointer generation mode of the FIFO per se is minimized.
It should be noted that, in the present application, there is no strict sequential execution order among the steps, and as long as the logical order is met, the steps may be executed simultaneously or according to a certain preset order, and fig. 1 is only an exemplary manner, and does not represent that only the execution order is the order.
It is understood that, the empty state is defined based on the actual clock frequency in the asynchronous clock domain, and the present application also provides a method for calculating the actual clock frequency, where the clock frequency is f, the clock frequency here may be a high clock frequency in the asynchronous clock domain, or a high clock frequency in the asynchronous clock domain, and the calculation process of the actual clock frequency of the clock frequency may include:
a: if every a null periods in the transmission process, sendingGenerating an effective clock signal at the actual clock frequency f t Can be based on the calculation of the relation f t Calculated as = f/(1+a).
B: if the ratio of effective propagation to total period in periodic propagation is b, the actual clock frequency f t Can be based on the calculation of the relation f t And = f × b.
C: if the time proportion of the enabled signal with effective clock in the transmission process is c, the actual clock frequency f t Can be based on the calculation of the relation f t And = f × c.
Inevitably, the above situations may exist simultaneously or partially, or the propagation has no law, and for the two situations, the application also provides corresponding calculation methods:
for an application scene with partial or all situations, the least common multiple of the existing situations can be taken as a parameter for calculation. Where the b and c parameter values are calculated as parameters whose values are raised to the power of-1 as the least common multiple. For example, when A and B exist simultaneously, if the least common multiple of a and 1/B is x, the actual clock frequency ft at this time is f t And (= f/x). Specifically, the method comprises the following steps:
if an effective clock signal occurs every a null periods in the transmission process, and the proportion of effective transmission in the periodic transmission to the total period is b, the actual clock frequency is calculated based on the clock frequency and the least common multiple of a and 1/b;
if an effective clock signal occurs once every a null periods in the transmission process, and the proportion of the effective enabling signal of the clock to the whole transmission time in the transmission process is c, the actual clock frequency is calculated based on the clock frequency and the least common multiple of a and 1/c;
if the proportion of effective transmission in the periodic transmission to the total period is b, and the proportion of the effective enabling signal of the clock to the whole transmission time in the transmission process is c, the actual clock frequency is calculated based on the clock frequency and the least common multiple of b and c;
if an effective clock signal occurs every a null cycles in the propagation process, the proportion of the effective propagation in the total cycle in the periodic propagation is b, and the proportion of the effective enabling signal of the clock in the propagation process in the whole transmission time is c, the actual clock frequency is calculated based on the least common multiple of the clock frequency, a, 1/b and 1/c.
If the propagation has no rule, the clock frequency under the worst condition is considered, and the calculation is carried out according to the calculation mode of the actual clock frequency corresponding to the clock frequency under the worst condition.
In the foregoing embodiment, the setting manner of the preset threshold is not limited, and this embodiment also provides a calculation manner of the preset threshold, before comparing the numerical relationship between the remaining read bits or the remaining writable bits in the asynchronous FIFO and the preset threshold, the method may further include:
acquiring a high clock frequency and a low clock frequency of an asynchronous clock domain;
the actual clock frequencies of the high clock frequency and the low clock frequency of the asynchronous clock domain may be calculated, for example, according to the practical application scenario in combination with the calculation methods listed in the above embodiments.
And calculating a preset threshold value according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency and the number of synchronous registers used by degrading metastable state influence. The step can be calculated by directly calling the packaged functional module, a threshold calculation relation is packaged in the functional module, a preset threshold is calculated by calling the threshold calculation relation, and the threshold calculation relation can be expressed as:
where Th is a predetermined threshold, ceil is rounded up, f tf Actual clock frequency, f, being a high clock frequency f At a high clock frequency, f ts For practical clock frequencies at low clock frequencies, rt is the number of synchronous registers used to degrade metastability effects.
In order to make the technical solutions of the present application more obvious to those skilled in the art, the present application also provides an illustrative example to describe the technical solutions of the present application based on the standard asynchronous FIFO structure shown in the prior art, i.e. the structure shown in fig. 1, please refer to fig. 3 and fig. 4, which may include:
and adding an empty-to-full generation module in an asynchronous FIFO standard structure circuit, modifying the implementation logic of the pointer comparison module, finishing the technical scheme in the embodiment by the empty-to-full generation module and the pointer comparison module together, preprocessing different states, and realizing the avoidance function of the empty-to-full state. The empty to full generation module determines a generation stimulus mechanism for the empty to full state bit based on a preset threshold. The threshold generation here can be obtained completely by those skilled in the art according to the actual application scenario configuration, or dynamically adjusted by logic circuits according to the algorithm. The empty-to-full state is generated before the empty state or the full state is generated, so that the early warning effect is achieved, and the pre-adjustment for reducing the error probability of the circuit is realized. The generated empty or full status bits are applied to the read pointer generation module and the write pointer generation module, respectively. Furthermore, the realization part of the application depending on a computer program and a pointer generation module can be combined, optimization is carried out from the initial value input stage of the algorithm, the dispersion of the operation is achieved, and the asynchronous FIFO circuit can have better control capability.
The embodiment of the invention also provides a corresponding device for the method for identifying the empty and full working states of the asynchronous FIFO, so that the method has higher practicability. Wherein the means may be described separately from a functional block point of view and a hardware point of view. The following describes an apparatus for identifying an empty/full operating state of an asynchronous FIFO according to an embodiment of the present invention, and the apparatus for identifying an empty/full operating state of an asynchronous FIFO described below and the method for identifying an empty/full operating state of an asynchronous FIFO described above may be referred to in correspondence with each other.
Based on the angle of the functional module, referring to fig. 5, fig. 5 is a block diagram of an embodiment of an apparatus for identifying an empty/full working status of an asynchronous FIFO, where the apparatus may include:
a state self-defining module 501, configured to define a full state and an empty state in advance based on an actual clock frequency of a clock domain where the read-write pointer is located, and a state corresponding to a read-write pointer generation manner and a state when the read bit does not reach the storage bit width; the full state is used to indicate that the asynchronous FIFO will be in a working full state and the empty state is used to indicate that the asynchronous FIFO will be in a working empty state.
And a calculating module 502 for calculating the remaining read bits or the remaining writable bits in the asynchronous FIFO.
A status indication information generating module 503, configured to generate information that the working status of the asynchronous FIFO is a to-be-empty status if the remaining read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0; and if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating the information that the working state of the asynchronous FIFO is the full state.
Optionally, in some embodiments of this embodiment, the state customization module 501 may include:
the empty state definition submodule is used for defining the state when the actual clock frequency of the clock domain where the write pointer is located is higher than the clock frequency of the clock domain where the read pointer is located, the written bit corresponding to the write pointer generation mode is larger than the read bit corresponding to the read pointer, and the storage bit width is not reached as the empty state;
and the full state definition submodule is used for defining the state as the full state when the read pointer generates a read bit which is larger than a written bit which corresponds to the write pointer and does not reach the storage bit width if and only if the actual clock frequency of the clock domain where the read pointer is positioned is higher than the actual clock frequency of the clock domain where the write pointer is positioned.
As some optional implementations of this embodiment, the state customization module 501 may include an actual clock frequency calculation submodule, which may be configured to:
if an effective clock signal occurs every a null periods during the propagation process, the actual clock frequency f t Is f t = f/(1 + a); f is the clock frequency;
if the ratio of effective propagation to total period in periodic propagation is b, the actual clock frequency f t Is f t = f × b; f is the clock frequency;
if in the process of propagationThe proportion of the effective enable signal of the middle clock to the whole transmission time is c, and the actual clock frequency f t Is f t = f × c; f is the clock frequency.
As other optional implementations of this embodiment, the actual clock frequency calculating submodule may further be configured to:
if an effective clock signal occurs every a null periods in the transmission process, and the proportion of effective transmission in the periodic transmission to the total period is b, the actual clock frequency is calculated based on the clock frequency and the least common multiple of a and 1/b;
if an effective clock signal occurs once every a null periods in the transmission process, and the proportion of the effective enabling signal of the clock to the whole transmission time in the transmission process is c, the actual clock frequency is calculated based on the clock frequency and the least common multiple of a and 1/c;
if the proportion of effective transmission in the periodic transmission to the total period is b, and the proportion of the effective enabling signal of the clock to the whole transmission time in the transmission process is c, the actual clock frequency is calculated based on the clock frequency and the least common multiple of b and c;
if an effective clock signal occurs every a null cycles in the propagation process, the proportion of the effective propagation in the total cycle in the periodic propagation is b, and the proportion of the effective enabling signal of the clock in the propagation process in the whole transmission time is c, the actual clock frequency is calculated based on the least common multiple of the clock frequency, a, 1/b and 1/c.
Optionally, in some embodiments of this embodiment, the apparatus may further include a threshold calculation module, where the threshold calculation module is configured to calculate an actual clock frequency of the high clock frequency and the low clock frequency of the asynchronous clock domain; and calculating a preset threshold value according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency and the number of synchronous registers used for degrading the metastable state influence.
As an optional implementation manner of this embodiment, the threshold calculation module may be further configured to invoke a threshold calculation relation to calculate the preset threshold, where the threshold calculation relation may be represented as:
where Th is a predetermined threshold, ceil is rounded up, f tf Actual clock frequency, f, being a high clock frequency f At a high clock frequency, f ts For practical clock frequencies at low clock frequencies, rt is the number of synchronous registers used to degrade metastability effects.
The functions of the functional modules of the empty and full working state identification apparatus of the asynchronous FIFO according to the embodiment of the present invention may be specifically implemented according to the method in the embodiment of the method, and the specific implementation process may refer to the description related to the embodiment of the method, which is not described herein again.
Therefore, the embodiment of the invention not only can effectively reduce the problem probability of FIFO working errors caused by the empty and full states of asynchronous FIFO working, but also can not increase the system overhead.
The above mentioned empty and full working status recognition device of the asynchronous FIFO is described from the perspective of the functional module, and further, the present application also provides an empty and full working status recognition device of the asynchronous FIFO, which is described from the perspective of hardware. Fig. 6 is a block diagram of another apparatus for identifying an empty/full operation state of an asynchronous FIFO according to an embodiment of the present application. As shown in fig. 6, the apparatus comprises a memory 60 for storing a computer program; a processor 61, configured to execute the computer program to implement the steps of the method for identifying the empty/full operation state of the asynchronous FIFO as mentioned in the above embodiment.
Processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so forth. The processor 61 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 61 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in a wake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 61 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 61 may further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.
Memory 60 may include one or more computer-readable storage media, which may be non-transitory. Memory 60 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used for storing a computer program 601, wherein after being loaded and executed by the processor 61, the computer program can implement the relevant steps of the method for identifying the empty/full operation status of the asynchronous FIFO disclosed in any of the foregoing embodiments. In addition, the resources stored by the memory 60 may also include an operating system 602, data 603, and the like, which may be in a transient or persistent form. Operating system 602 may include Windows, unix, linux, etc., among others. The data 603 may include, but is not limited to, data corresponding to the empty/full operation state recognition result of the asynchronous FIFO, and the like.
In some embodiments, the device for identifying the empty/full operation status of the asynchronous FIFO may further include a display 62, an input/output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.
Those skilled in the art will appreciate that the configuration shown in fig. 6 does not constitute a limitation of the means for identifying an empty-full operating condition of an asynchronous FIFO and may include more or fewer components than those shown, such as a sensor 67.
The functions of the functional modules of the empty and full working state identification apparatus of the asynchronous FIFO according to the embodiment of the present invention may be specifically implemented according to the method in the embodiment of the method, and the specific implementation process may refer to the description related to the embodiment of the method, which is not described herein again.
Therefore, the embodiment of the invention not only can effectively reduce the problem probability of FIFO working errors caused by the empty and full states of asynchronous FIFO working, but also can not increase the system overhead.
It is understood that, if the method for identifying the empty/full operation state of the asynchronous FIFO in the above embodiment is implemented in the form of a software functional unit and sold or used as a separate product, it may be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application may be substantially or partially implemented in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods of the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), an electrically erasable programmable ROM, a register, a hard disk, a removable magnetic disk, a CD-ROM, a magnetic or optical disk, and other various media capable of storing program codes.
Based on this, the embodiment of the present invention further provides a computer-readable storage medium, in which an empty and full operation state identification program of an asynchronous FIFO is stored, and the empty and full operation state identification program of the asynchronous FIFO is executed by a processor, and the steps of the empty and full operation state identification method of the asynchronous FIFO according to any one of the above embodiments are provided.
The functions of the functional modules of the computer-readable storage medium according to the embodiment of the present invention may be specifically implemented according to the method in the foregoing method embodiment, and the specific implementation process may refer to the related description of the foregoing method embodiment, which is not described herein again.
Therefore, the embodiment of the invention not only can effectively reduce the problem probability of FIFO working errors caused by the empty and full states of asynchronous FIFO working, but also can not increase the system overhead.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The above detailed description is provided for a method, an apparatus, and a computer-readable storage medium for identifying an empty/full working status of an asynchronous FIFO. The principles and embodiments of the present invention have been described herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it can make several improvements and modifications to the present application, and those improvements and modifications also fall into the protection scope of the claims of the present application.
Claims (9)
1. A method for identifying the empty and full working state of an asynchronous FIFO is characterized by comprising the following steps:
defining a full state and an empty state of a read bit corresponding to a read-write pointer generation mode and a state when the storage bit width is not reached based on the actual clock frequency of a clock domain where the read-write pointer is located in advance; the full state is used for indicating that the asynchronous FIFO is to be in a working full state, and the empty state is used for indicating that the asynchronous FIFO is to be in a working empty state;
calculating the residual read bits or the residual writable bits in the asynchronous FIFO;
if the residual reading bit in the asynchronous FIFO is less than or equal to a preset threshold and greater than 0, generating the information that the working state of the asynchronous FIFO is a to-be-empty state;
if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating information that the working state of the asynchronous FIFO is a to-be-full state;
wherein if the remaining read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0, the method further comprises:
calculating actual clock frequencies of a high clock frequency and a low clock frequency of the asynchronous clock domain;
and calculating the preset threshold according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency and the number of synchronous registers used by degrading metastable state influence.
2. The method according to claim 1, wherein the defining the full state and the empty state of the read bit and the state that does not reach the storage bit width corresponding to the generation manner of the read/write pointer based on the actual clock frequency of the clock domain where the read/write pointer is located in advance comprises:
if and only if the actual clock frequency of the clock domain where the write pointer is located is higher than the clock frequency of the clock domain where the read pointer is located, the written bit corresponding to the write pointer generation mode is larger than the read bit corresponding to the read pointer, and the state when the storage bit width is not reached is defined as the to-be-empty state;
and if and only if the actual clock frequency of the clock domain where the read pointer is located is higher than the actual clock frequency of the clock domain where the write pointer is located, the read bit corresponding to the read pointer generation mode is larger than the write bit corresponding to the write pointer, and the state when the storage bit width is not reached is defined as the to-full state.
3. The method for identifying the empty/full operation status of an asynchronous FIFO as recited in claim 1, wherein the calculation of the actual clock frequency comprises:
if every other time in the propagation processaOne empty cycle, one occurrence of an active clock signal, soSaid actual clock frequencyf t Is composed off t =f/(1+a)；fIs the clock frequency;
if the ratio of effective propagation to total period in periodic propagation isbSaid actual clock frequencyf t Is composed off t =f×b；fIs the clock frequency;
the enable signal, if the clock is active during propagation, accounts for a proportion of the total transmission timecSaid actual clock frequencyf t Is composed off t =f×c；fIs the clock frequency.
4. The method for identifying the empty/full operation status of an asynchronous FIFO as recited in claim 3, wherein the calculation of the actual clock frequency comprises:
if every other time in the propagation processaOne effective clock signal is generated in one empty period, and the proportion of effective propagation in the periodic propagation to the total period isbThe actual clock frequency is based onaAnd 1bThe minimum common multiple of the clock frequency is obtained by calculation;
if every other time in the propagation processaOne effective clock signal occurs in one empty period, and the effective enabling signal of the clock accounts for the proportion of the time of the whole transmission in the process of propagationcSaid actual clock frequencyaAnd 1cThe minimum common multiple of the clock frequency is obtained by calculation;
if the ratio of effective propagation to total period in periodic propagation isbWhile the clock-active enable signal accounts for a proportion of the total transmission time during propagationcThe actual clock frequency is based onbAndcthe minimum common multiple of the clock frequency is obtained by calculation;
if every other time in the propagation processaThe effective clock signal occurs once in each null period, and the effective propagation accounts for the total period in the periodic propagationbAnd the effective enabling signal of the clock accounts for the proportion of the time of the whole transmission in the process of propagationcSaid actual clock frequencyRate is based ona、1/bAnd 1+cThe least common multiple of (c), the clock frequency calculation.
5. The method for identifying an empty/full operation status of an asynchronous FIFO according to claim 1, wherein said calculating said preset threshold value according to said high clock frequency and its actual clock frequency, said actual clock frequency of said low clock frequency, and the number of synchronous registers used for degrading the meta-stability effect comprises:
calling a threshold calculation relation to calculate the preset threshold, wherein the threshold calculation relation is as follows:
in the formula (I), the compound is shown in the specification,Ththe threshold value is set to be the preset threshold value,ceilwhich means that the rounding is made up,f tf is the actual clock frequency of said high clock frequency,f f in order for the high clock frequency to be the same,f ts is the actual clock frequency of said low clock frequency,Rtthe number of synchronization registers used to degrade metastability effects.
6. An empty-full operation status recognition apparatus for an asynchronous FIFO, comprising:
the state self-defining module is used for defining a full state and an empty state in advance based on the actual clock frequency of the clock domain where the read-write pointer is located and the states of the read bit corresponding to the generation mode of the read-write pointer and the state of the read bit not reaching the storage bit width; the active full state is used for indicating that the asynchronous FIFO is to be in an active full state, and the active empty state is used for indicating that the asynchronous FIFO is to be in an active empty state;
the calculation module is used for calculating the residual read bits or the residual writable bits in the asynchronous FIFO;
a status indication information generating module, configured to generate information that a working status of the asynchronous FIFO is a to-be-empty status if remaining read bits in the asynchronous FIFO are less than or equal to a preset threshold and greater than 0; if the remaining writable bits in the asynchronous FIFO are not more than the preset threshold and are more than 0, generating information that the working state of the asynchronous FIFO is a to-be-full state;
a threshold calculation module for calculating actual clock frequencies of the high clock frequency and the low clock frequency of the asynchronous clock domain; and calculating the preset threshold according to the high clock frequency and the actual clock frequency thereof, the actual clock frequency of the low clock frequency and the number of synchronous registers used for degrading the metastable state influence.
7. The apparatus for identifying the empty and full operation status of the asynchronous FIFO as recited in claim 6, wherein the status customizing module comprises:
a null state definition submodule, configured to define a state in which a written bit corresponding to the write pointer generation mode is greater than a read bit corresponding to the read pointer and a storage bit width is not reached as the null state if and only if the actual clock frequency of the clock domain in which the write pointer is located is higher than the clock frequency of the clock domain in which the read pointer is located;
and the full state definition submodule is used for defining the state of the read pointer which is larger than the written bit corresponding to the write pointer and does not reach the storage bit width as the full state if and only if the actual clock frequency of the clock domain where the read pointer is located is higher than the actual clock frequency of the clock domain where the write pointer is located, and the read bit corresponding to the read pointer generation mode is larger than the written bit corresponding to the write pointer.
8. An empty-full operation status recognition apparatus for an asynchronous FIFO, comprising a processor for implementing the steps of the method for recognizing an empty-full operation status of an asynchronous FIFO according to any one of claims 1 to 5 when executing a computer program stored in a memory.
9. A computer-readable storage medium, wherein the computer-readable storage medium has stored thereon an empty-full operation status recognition program of an asynchronous FIFO, which when executed by a processor implements the steps of the empty-full operation status recognition method of an asynchronous FIFO according to any one of claims 1 to 5.
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