CN112458427A - Preparation method of chip stewing layer, chip stewing layer and chip - Google Patents

Preparation method of chip stewing layer, chip stewing layer and chip Download PDF

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Publication number
CN112458427A
CN112458427A CN202011226912.2A CN202011226912A CN112458427A CN 112458427 A CN112458427 A CN 112458427A CN 202011226912 A CN202011226912 A CN 202011226912A CN 112458427 A CN112458427 A CN 112458427A
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silicon oxide
chip
layer
silicon
etching
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CN112458427B (en
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丁凯文
冷群文
邹泉波
赵海轮
安琪
周汪洋
周良
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Goertek Microelectronics Inc
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Goertek Microelectronics Inc
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    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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Abstract

The invention discloses a preparation method of a chip stewing layer, the chip stewing layer and a chip, wherein silicon nitride or silicon oxide is deposited on a hard mask substrate to obtain a first structure; growing amorphous silicon on the surface of the first structure to obtain a second structure; depositing silicon oxide on the upper surface of the second structure to obtain a third structure; patterning the silicon oxide layer in the third structure to obtain a fourth structure; performing silicon etching on the fourth structure to obtain a fifth structure; and releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer. Therefore, the chip passivation layer with high process integration level, good reliability and compatibility is obtained through operations of deposition, growth, redeposition, patterning, etching and release.

Description

Preparation method of chip stewing layer, chip stewing layer and chip
Technical Field
The invention belongs to the field of chip preparation, and particularly relates to a preparation method of a chip stewing layer, the chip stewing layer and a chip.
Background
The chip of the microphone is generally a Micro-Electro-Mechanical System (MEMS). The passivation layer of the current MEMS is generally a silicon nitride material, but the conventional silicon nitride material is not resistant to the corrosion of hydrofluoric acid, and the silicon nitride material resistant to the corrosion of hydrofluoric acid needs to be at a higher growth temperature, so that the integration of devices which are not resistant to high temperature on the MEMS is limited. And MEMS of silicon nitride materials require thicker materials during etching to prevent attack by hydrofluoric acid. And thus the reliability and compatibility of the chip are limited.
Disclosure of Invention
The invention provides a preparation method of a chip stewing layer, the chip stewing layer and a chip, and aims to improve the reliability and compatibility of a chip passivation layer.
In order to achieve the above object, the present invention provides a method for preparing a chip-stewed layer, the method comprising:
depositing silicon nitride or silicon oxide on the hard mask substrate to obtain a first structure;
growing amorphous silicon on the surface of the first structure to obtain a second structure;
depositing silicon oxide on the upper surface of the second structure to obtain a third structure;
patterning the silicon oxide layer in the third structure to obtain a fourth structure;
performing silicon etching on the fourth structure to obtain a fifth structure;
and releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer.
Optionally, the depositing silicon nitride or silicon oxide on the hard mask substrate to obtain a first structure includes:
depositing silicon nitride or silicon oxide on the hard mask substrate by Plasma Enhanced Chemical Vapor Deposition (PECVD) method to obtain the first structure, wherein the reaction gas is SiH4And N2Or SiH4And N2O。
Optionally, the growing amorphous silicon on the surface of the first structure to obtain a second structure includes:
growing amorphous silicon on the surface of the first structure by adopting a PECVD method to obtain the second structure, wherein the growth conditions of the amorphous silicon are as follows: reaction chamber pressure 1Torr at 200 ℃ and reaction gas SiH4And H2In a dilution ratio of 1: 1to 1:12, wherein SiH4The flow rate was 100 sccm.
Optionally, the depositing of silicon oxide on the upper surface of the second structure to obtain a third structure includes:
and performing silicon oxide deposition on the upper surface of the second structure by adopting a PECVD method to obtain a third structure, wherein the uppermost layer of the third structure is a silicon oxide layer, and the silicon oxide deposition conditions are as follows: SiH as a reaction gas4And N2Dilution ratio of O is 1:3, wherein N2The flow rate of O was 200 cm/min.
Optionally, the patterning the silicon oxide layer in the third structure to obtain a fourth structure includes:
and printing the pattern on the mask plate to the silicon oxide layer in the third structure through a photoetching machine to obtain a fourth structure with the pattern.
Optionally, the performing silicon etching on the fourth structure to obtain a fifth structure includes:
and etching the line width control areas of the silicon oxide layer and the amorphous silicon layer in the fourth structure by using sulfur hexafluoride to obtain a fifth structure with an etching effect.
Optionally, the releasing the hard mask in the fifth structure to obtain a chip passivation layer includes:
and releasing the silicon nitride and/or the silicon oxide in the fifth structure by using hydrofluoric acid as etching liquid through a wet etching method to obtain the chip passivation layer.
Optionally, the depositing silicon nitride or silicon oxide on the hard mask substrate to obtain a first structure includes:
and depositing silicon nitride or silicon oxide on the hard mask substrate by adopting any one method of thermal oxidation, inductively coupled plasma chemical vapor deposition and laser plasma vapor chemical deposition to obtain the first structure.
In addition, in order to achieve the purpose, the invention also provides a chip stewing layer, and the chip passivation layer is prepared by the preparation method of the chip stewing layer.
In addition, in order to achieve the purpose, the invention also provides a chip which comprises the chip passivation layer prepared by the preparation method of the chip stewing layer.
Compared with the prior art, the invention provides the preparation method of the chip stewing layer, the chip stewing layer and the chip, wherein silicon nitride or silicon oxide is deposited on the hard mask substrate to obtain the first structure; growing amorphous silicon on the surface of the first structure to obtain a second structure; depositing silicon oxide on the upper surface of the second structure to obtain a third structure; patterning the silicon oxide layer in the third structure to obtain a fourth structure; performing silicon etching on the fourth structure to obtain a fifth structure; and releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer. Therefore, the chip passivation layer with high process integration level, good reliability and compatibility is obtained through operations of deposition, growth, redeposition, patterning, etching and release.
Drawings
FIG. 1 is a schematic flow chart of a first embodiment of the method for preparing a chip stewing layer according to the present invention.
Fig. 2 is a schematic diagram of a passivation layer of a chip according to a first embodiment of the method for preparing a stew layer of a chip of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The preparation method of the chip stewing layer mainly related to the embodiment of the invention comprises the following steps:
step S101: depositing silicon nitride or silicon oxide on the hard mask substrate to obtain a first structure;
in this embodiment, the hard mask substrate may be made of silicon dioxide, so that the dry etching selectivity can be improved, the process size resolution can be improved, and the chip sensitivity can be improved.
In this embodiment, a plasma enhanced chemical vapor deposition method is used to deposit silicon nitride or silicon oxide on the hard mask substrate to obtain the first structure, wherein the reaction gas is SiH4And N2Or SiH4And N2O。
The Plasma Enhanced Chemical Vapor Deposition (PECVD) method is a method of forming a Plasma locally by ionizing a gas containing atoms of a film component by means of microwave or radio frequency, etc., and the Plasma is chemically very active and easily reacts to deposit a desired film on a substrate. The film prepared by utilizing the plasma enhanced chemical vapor deposition has low basic temperature; the deposition rate is high; good film forming quality, less pinholes, difficult cracking and the like.
Specifically, the frequency of the RF power supply was set to 13.56MHz, and the pressure in the reaction chamber was controlled to 1X 10 by the throttle valve-3Pa, fixing the temperature of the hard mask substrate at 200-260 ℃. If silicon nitride is deposited, the reactant gas is SiH4And N2，SiH4And N2In a dilution ratio of 1:3, wherein N is2The flow rate of (2) is 200 cm/min. If silicon nitride is deposited, the reactant gas is SiH4And N2O，SiH4And N2Dilution ratio of O is 1:3, wherein N2The flow rate of O was 200 cm/min. In order to ensure the operation safety, a large amount of inert gases such as argon, nitrogen and the like are injected into the reaction chamber after the deposition is finished.
In the embodiment, the temperature of the hard mask substrate is fixed at 200-260 ℃, and silicon nitride or silicon oxide can be deposited even under the condition of lower than 200 ℃, so that the manufactured chip passivation layer can be compatible with a plurality of devices which are not high in temperature resistance.
In other embodiments, the first structure may be obtained by depositing silicon nitride or silicon oxide on the hard mask substrate by any one of thermal oxidation, inductively coupled plasma chemical vapor deposition, and laser plasma vapor chemical deposition. Thermal oxidation refers to the process by which silicon oxidizes in air to form a native oxide layer. Inductively coupled plasma chemical vapor deposition is chemical vapor deposition using inductively coupled generated plasma. Inductively coupled plasma has received increasing attention in the fields of deep submicron etching, thin film material preparation, etc. of microelectronic device manufacturing processes. The basic principle is as follows: when the induction coil passes through radio frequency current, a changing magnetic field is excited in the vacuum chamber (discharge tube), the changing magnetic field induces an electric field, and electrons in the gas acquire energy from the electromagnetic field and are ionized, so that high-density plasma is generated. Laser plasma is a novel method for emitting laser by combining laser characteristics with plasma technology.
Step S102: growing amorphous silicon on the surface of the first structure to obtain a second structure;
in this embodiment, a PECVD method is used to grow amorphous silicon on the surface of the first structure to obtain the second structure, where the growth conditions of the amorphous silicon are: reaction chamber pressure 1Torr at 200 ℃ and reaction gas SiH4And H2In a dilution ratio of 1: 1to 1:12, wherein SiH4The flow rate was 100 sccm. Further, the radio frequency power supply frequency is 13.56 MHz.
Generally, in SiH4And H2Dilution ratio, radio frequency power, growth temperatureUnder the condition of unchanged temperature, the pressure of the reaction chamber is increased, and the growth rate of the amorphous silicon is increased. Under the condition of keeping other conditions unchanged, the growth temperature is increased within 150-200 ℃ to increase the growth rate of the amorphous silicon.
In addition, in the process of growing the amorphous silicon, the three-dimensional structural shape of the obtained amorphous silicon can be adjusted by controlling the growth temperature, the pressure of the reaction chamber, and the dilution ratio. So that chips with different structural stresses can be obtained.
Step S103: depositing silicon oxide on the upper surface of the second structure to obtain a third structure;
in this embodiment, a PECVD method is used to deposit silicon oxide on the upper surface of the second structure to obtain a third structure, wherein the uppermost layer of the third structure is a silicon oxide layer, and the silicon oxide deposition conditions are as follows: SiH as a reaction gas4And N2Dilution ratio of O is 1:3, wherein N2The flow rate of O was 200 cm/min. The deposition method is similar to step S101 and is not described herein again.
Step S104: patterning the silicon oxide layer in the third structure to obtain a fourth structure;
specifically, a pattern on the mask is printed on the silicon oxide layer in the third structure through a photoetching machine, and a fourth structure with the pattern is obtained. A Mask Aligner (Mask Aligner), also called a Mask alignment exposure machine, an exposure system, a lithography system, etc., is a core equipment for manufacturing a chip, which prints a fine pattern on a Mask plate onto a silicon wafer by exposure of light using a technique similar to photo lithography. The pattern on the reticle may be customized as desired.
Step S105: performing silicon etching on the fourth structure to obtain a fifth structure;
in this embodiment, the line width control regions of the silicon oxide layer and the amorphous silicon layer in the fourth structure are etched by using sulfur hexafluoride, so as to obtain a fifth structure having an etching effect.
Sulfur hexafluoride is a stable gas which is colorless, odorless, nontoxic and noncombustible. The sulfur hexafluoride molecular structure is arranged in an octahedron shape, the bonding distance is small, the bonding energy is high, the stability is high, and the compatibility of the sulfur hexafluoride molecular structure with the electrical structure material is similar to that of nitrogen when the temperature is not more than 180 ℃. The mixed gas of sulfur hexafluoride and oxygen can be used for etching silicon. In other embodiments, since the corrosion rate of sulfur hexafluoride to silicon is fast, the problems of too much lateral corrosion and glue scraping can occur when the deep trench is corroded. Therefore, the mixed gas of sulfur hexafluoride and oxygen can be used for etching silicon, so that the activity of fluorine can be increased, and the corrosion is more uniform.
In the actual operation process, accurate exposure needs to be carried out on the line width control area, the alignment precision is higher in the middle, and otherwise, etching deviation can occur. After etching, the fifth structure with the required etching effect can be obtained.
Step S106: releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer
Specifically, hydrofluoric acid is used as etching liquid by a wet etching method, and the silicon nitride and/or the silicon oxide in the fifth structure are released to obtain the chip passivation layer.
The wet etching is to put the wafer into liquid chemical etching liquid for etching, and in the etching process, the etching liquid will gradually etch and dissolve the materials contacted with the wafer through chemical reaction.
The aqueous solution of hydrofluoric acid and hydrogen fluoride gas is clear, colorless and fuming corrosive liquid and has severe pungent smell. Hydrofluoric acid is a weak acid, is extremely corrosive, and can aggressively corrode metals, glass, and silicon-containing objects.
And placing the fifth structure in hydrofluoric acid, wherein the silicon nitride or the silicon oxide in the fifth structure can be completely and partially corroded, and a chip passivation layer with high process integration is obtained. The chip passivation layer mainly comprises crystalline silicon and amorphous silicon. The prepared chip stewing layer has excellent performance of resisting corrosion of hydrofluoric acid and good reliability.
Based on the above steps, the structures of the manufactured chip passivation layer are shown in fig. 2. Fig. 2 is a schematic diagram of a passivation layer of a chip according to a first embodiment of the method for preparing a stew layer of a chip of the present invention. As shown in fig. 2, a chip passivation layer coated with silicon oxide by crystalline silicon and single crystal silicon is obtained on a substrate through deposition, growth, redeposition, patterning, etching, and release operations.
In addition, the invention also provides a chip stewing layer, and the chip passivation layer is prepared by the method.
In addition, the invention also provides a chip which comprises the chip passivation layer prepared by the method.
Compared with the prior art, the invention discloses a preparation method of a chip stewing layer, the chip stewing layer and a chip, wherein silicon nitride or silicon oxide is deposited on a hard mask substrate to obtain a first structure; growing amorphous silicon on the surface of the first structure to obtain a second structure; depositing silicon oxide on the upper surface of the second structure to obtain a third structure; patterning the silicon oxide layer in the third structure to obtain a fourth structure; performing silicon etching on the fourth structure to obtain a fifth structure; and releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer. Therefore, the chip passivation layer with high process integration level, good reliability and compatibility is obtained through operations of deposition, growth, redeposition, patterning, etching and release.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and all equivalent structures or flow transformations made by the present specification and drawings, or applied directly or indirectly to other related arts, are included in the scope of the present invention.

Claims (10)

1. A method of preparing a chip stewing layer, comprising:
depositing silicon nitride or silicon oxide on the hard mask substrate to obtain a first structure;
growing amorphous silicon on the surface of the first structure to obtain a second structure;
depositing silicon oxide on the upper surface of the second structure to obtain a third structure;
patterning the silicon oxide layer in the third structure to obtain a fourth structure;
performing silicon etching on the fourth structure to obtain a fifth structure;
and releasing the silicon nitride and/or the silicon oxide in the fifth structure to obtain a chip passivation layer.
2. The method of claim 1, wherein depositing silicon nitride or silicon oxide on a hard mask substrate to obtain a first structure comprises:
depositing silicon nitride or silicon oxide on the hard mask substrate by Plasma Enhanced Chemical Vapor Deposition (PECVD) method to obtain the first structure, wherein the reaction gas is SiH4And N2Or SiH4And N2O。
3. The method of claim 1, wherein growing amorphous silicon on the surface of the first structure to obtain a second structure comprises:
growing amorphous silicon on the surface of the first structure by adopting a PECVD method to obtain the second structure, wherein the growth conditions of the amorphous silicon are as follows: reaction chamber pressure 1Torr at 200 ℃ and reaction gas SiH4And H2In a dilution ratio of 1: 1to 1:12, wherein SiH4The flow rate was 100 sccm.
4. The method of claim 1, wherein said depositing silicon oxide on the upper surface of the second structure to obtain a third structure comprises:
and performing silicon oxide deposition on the upper surface of the second structure by adopting a PECVD method to obtain a third structure, wherein the uppermost layer of the third structure is a silicon oxide layer, and the silicon oxide deposition conditions are as follows: SiH as a reaction gas4And N2Dilution ratio of O is 1:3, wherein N2The flow rate of O was 200 cm/min.
5. The method of claim 1, wherein the patterning the silicon oxide layer in the third structure to obtain a fourth structure comprises:
and printing the pattern on the mask plate to the silicon oxide layer in the third structure through a photoetching machine to obtain a fourth structure with the pattern.
6. The method of claim 1, wherein the silicon etching the fourth structure to obtain a fifth structure comprises:
and etching the line width control areas of the silicon oxide layer and the amorphous silicon layer in the fourth structure by using sulfur hexafluoride to obtain a fifth structure with an etching effect.
7. The method of claim 1, wherein the releasing the hard mask in the fifth structure to obtain a chip passivation layer comprises:
and releasing the silicon nitride and/or the silicon oxide in the fifth structure by using hydrofluoric acid as etching liquid through a wet etching method to obtain the chip passivation layer.
8. The method of claim 1, wherein depositing silicon nitride or silicon oxide on a hard mask substrate to obtain a first structure comprises:
and depositing silicon nitride or silicon oxide on the hard mask substrate by adopting any one method of thermal oxidation, inductively coupled plasma chemical vapor deposition and laser plasma vapor chemical deposition to obtain the first structure.
9. A chip passivation layer, characterized in that the chip passivation layer is prepared by the method of any of claims 1-8.
10. A chip comprising a chip passivation layer prepared by the method of preparing a chip handle layer according to any one of claims 1to 8.
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