CN112449695A

CN112449695A - Multiple integration scheme using bonding of ASIC or FPGA chips to 3D crosspoint chips

Info

Publication number: CN112449695A
Application number: CN202080002721.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-12
Filing date: 2020-10-12
Publication date: 2021-03-05
Also published as: WO2022077148A1

Abstract

SSDs, methods and integrated architectures for bonding ASIC or FPGA chips to 3D Xpoint chips are disclosed. 3D Xpoint memory cells are introduced into both volatile and non-volatile memory systems to reduce circuit area. Registers in the FPGA and on-chip memory (BRAM) belong to respective control logic units to perform the elimination of unnecessary arbitration/caching. The logic cell connections of the FPGA to the surrounding logic cells are determined at the reprogramming/programming time without communication through the shared memory. The Xtacking technique bonds the master control ASIC and/or FPGA chip to the SSD to reduce circuit area. By this architecture, the SRAM cache is eliminated, reducing circuit area and critical path connection distance, thereby reducing latency and power consumption. Data processing/access speed and efficiency are significantly improved by such an integrated architecture. The bonding technique also reduces the wiring distance and parasitic RC influence, improves the system integration, shortens the process manufacturing period, reduces the PCB ratio and increases the circuit design process window.

Description

Multiple integration scheme using bonding of ASIC or FPGA chips to 3D crosspoint chips

Technical Field

The present disclosure relates generally to an improved computing architecture for improved data processing speed.

Background

With the rapid growth of internet users, the amount of data has expanded dramatically, and the demand for computing in data centers has also increased rapidly. Such as deep learning online prediction, live video transcoding, image compression decompression, and hypertext transfer protocol secure (HTTPS) encryption, among others. The need for high performance computing has far exceeded the capabilities of conventional Central Processing Unit (CPU) processors. Such a need has exceeded previous expectations for computational performance, such as moore's law dictates that a doubled number of transistors are always available for use in integrated circuits. Attention now being directed to the development of computing processes is directed to improved designs for computing architectures. However, such designs still have limitations in their ability to handle high data volumes because inefficient use of the surface area on the wafer of circuits in the computing architecture and the resulting increase in distance between each circuit may result in increased signal delay.

Thus, there remains a need for a computing architecture that is capable of more efficiently handling high data volumes by minimizing the surface area used per block of circuitry.

Disclosure of Invention

According to one aspect, a single chip stacked integrated architecture system and method of manufacturing the same are disclosed. The system includes an interface, a controller chip that may include an Application Specific Integrated Circuit (ASIC) chip and/or a Field Programmable Gate Array (FPGA) chip, and a 3D cross point memory chip bonded to the controller chip through the interface. An integrated architecture with an ASIC or FPGA (microprocessor) chip is bonded to the 3D Xpoint chip. Furthermore, 3D Xpoint has been introduced into both Volatile Memory (VM) systems and non-volatile memory (NVM) systems.

According to another aspect, a small single chip processing system and method of making the same includes a host interface, a master control chip (including but not limited to an integrated ASIC and/or FPGA custom circuit or a plurality of discrete small circuits), and a 3D Xpoint chip that is a non-volatile solid state drive memory (e.g., as NVM, resulting in high endurance, stackable and faster than NAND) and a volatile solid state drive memory (e.g., VM, resulting in lower cost than DRAM). Registers in the FPGA and on-chip memory (BRAM) belong to their respective control logic units for the need to save state, eliminating the need for unnecessary arbitration and caching. For communication requirements, the connection of each logic cell of the FPGA to surrounding logic cells is determined at the time of reprogramming and/or programming and no communication through shared memory is required.

In addition, the main control ASIC and/or FPGA chip is bonded to the solid state disk by adopting the XBacking technology, which reduces the circuit area to some extent. For example, wiring architectures typically occupy 60-70% of the total area of an FPGA chip. In terms of delay, the ratio is higher. Instead of writing to the read-write cache, there is no need to write to the read-write cache of the ASIC and/or FPGA or to store updated records of the logical-physical address table. The need for an SRAM cache is eliminated, which further reduces circuit area and reduces critical path connection distance between the memory chip and the main control chip. Thus, there is a reduction in latency and power consumption, and the speed and efficiency of data processing/access is significantly improved. The bonding technique greatly shortens the wiring distance, reduces the influence of parasitic Resistance Capacitance (RC), obviously improves the system integration, shortens the process manufacturing period, reduces the PCB ratio and increases the process window of circuit design.

According to another aspect, a solid-state storage device is disclosed, comprising: a controller chip comprising a controller wafer; a first set of connectors of the plurality of connectors, the first set of connectors having a first portion and a second portion; a circuit block wafer bonded to the controller through the first portion of the first set of connectors; an interface engaged with the second portion of the first set of connectors by a plurality of interconnects; and a memory chip bonded with the interface of the controller chip, the memory chip comprising: a memory wafer; a first memory array comprising a plurality of memory cells; a plurality of selectors; a plurality of word lines coupled to the selector, a first word line of the plurality of word lines adjacent a first end of a first memory array and a second word line of the plurality of word lines adjacent a second end of the memory array; and a plurality of bit lines coupled to the memory cells; a plurality of word lines are coupled to a plurality of word line contacts of the memory wafer, and a plurality of bit lines are coupled to a first plurality of bit line contacts of the plurality of connectors. Further, the first memory array of the memory chip may be a three-dimensional memory array in which a plurality of memory cells have first and second ends, a plurality of selectors have first and second ends, the second ends of the plurality of selectors are coupled to the first ends of the plurality of memory cells, a plurality of word lines are coupled to the first ends of the plurality of selectors, and the first plurality of bit lines are coupled to the second ends of the plurality of memory cells. Further, the first plurality of bitline contacts may run along a length of the memory wafer defined by the first wordline and the second wordline. Additionally, the controller chip may further include a portion of logic adjacent to the circuit block, the portion of logic including a second set of connectors of the plurality of connectors, the second set of connectors having a first portion and a second portion, the first portion of the second set of connectors engaged with the controller die and the second portion of the second set of connectors engaged with the plurality of interconnects. In addition, the controller chip may further include a second memory array, wherein the first set of connectors has a third portion, and the second memory array is joined with the third portion of the first set of connectors by a second plurality of bit line contacts. Further, the second storage array may be a three-dimensional storage array comprising: a plurality of memory cells having a first end and a second end; a plurality of selectors having first and second ends, the second ends of the plurality of selectors coupled to the first ends of the plurality of memory cells; a plurality of word lines coupled to first ends of the plurality of selectors; and a plurality of bit lines coupled to second ends of the plurality of memory cells, the second plurality of bit line contacts being adjacent to the plurality of bit lines of the second memory array.

According to another aspect, a method of forming a stacked architecture system is disclosed, comprising: forming a controller chip on a first wafer, the controller chip comprising: a controller wafer; a first set of connectors of the plurality of connectors, the first set of connectors having a first portion and a second portion; a circuit block wafer bonded to the controller through the first portion of the first set of connectors; and an interface engaged with the second portion of the first set of connectors by a plurality of interconnects; forming a memory chip on a second wafer, the memory chip comprising: a memory wafer; a first storage array, comprising: a plurality of memory cells, a plurality of selectors, a plurality of word lines coupled to the selectors, a first word line of the plurality of word lines adjacent a first end of the first memory array and a second word line of the plurality of word lines adjacent a second end of the memory array; and a plurality of bit lines coupled to the memory cells; coupling a plurality of word lines to a plurality of word line contacts of a memory wafer; and a first plurality of bit line contacts coupling the plurality of bit lines to the plurality of connectors; and bonding the first wafer and the second wafer to form a stacked architecture system. In addition, the controller chip may be formed through a CMOS process. In addition, the first memory array of the memory chip may be a three-dimensional memory array in which a plurality of memory cells have first and second ends, a plurality of selectors have first and second ends, the second ends of the plurality of selectors are coupled to the first ends of the plurality of memory cells, a plurality of word lines are coupled to the first ends of the plurality of selectors, and a plurality of bit lines are coupled to the second ends of the plurality of memory cells. In addition, the memory chip may be a nonvolatile memory and a volatile memory. Moreover, the method may further include at least one of forming a portion of the first logic circuit on the first wafer or forming a portion of the second logic circuit on the second wafer. Further, the portion of the first logic circuit and/or the portion of the second logic circuit may be formed by a CMOS process. In addition, the method may further include dicing at least one of the first wafer and the second wafer prior to the bonding step. Moreover, the method may further include dicing the stacked architecture system.

According to another aspect, a computing device is disclosed, comprising: a controller chip, comprising: a controller wafer; a first set of connectors of the plurality of connectors, the first set of connectors having a first portion and a second portion; a circuit block wafer bonded to the controller through a first portion of the first set of connectors; an interface engaged with the second portion of the first set of connectors by a plurality of interconnects; and a memory chip interfacing with the controller chip, the memory chip comprising: a memory wafer; a first storage array, comprising: a plurality of memory cells, a plurality of selectors, a plurality of word lines coupled to the selectors, a first word line of the plurality of word lines adjacent a first end of the first memory array and a second word line of the plurality of word lines adjacent a second end of the memory array; and a plurality of bit lines coupled to the memory cells; coupling a plurality of word lines to a plurality of word line contacts of a memory wafer; and a first plurality of bit line contacts coupling the plurality of bit lines to the plurality of connectors.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In the description of the exemplary embodiments of the present disclosure, specific terminology may be used for the sake of clarity. However, there is no intention that aspects of the disclosure be limited to the specific terminology used.

Fig. 1 is an isometric view of a section of a three-dimensional cross-point memory according to various aspects of the present disclosure.

FIG. 2 is a functional diagram of a computing device according to various aspects of the present disclosure.

FIG. 3 is a functional diagram of a memory device according to various aspects of the present disclosure.

Fig. 4 is a top view of a segment of a memory chip according to aspects of the present disclosure.

Fig. 5 is a functional diagram of a master controller chip according to various aspects of the present disclosure.

Fig. 6 is a top view of a section of memory according to various aspects of the present disclosure.

Fig. 7 is a side view of a segment of the memory chip of fig. 6.

Fig. 8 is a top view of a master controller chip according to various aspects of the present disclosure.

FIG. 9 is a cross-sectional view of a portion of the master controller of FIG. 8.

Fig. 10 is a cross-sectional view of a portion of a master controller chip according to various aspects of the present disclosure.

Fig. 11 is a cross-sectional view of a portion of an integrated architecture system according to aspects of the present disclosure.

Fig. 12 is a cross-sectional view of a portion of an integrated architecture system according to aspects of the present disclosure.

Fig. 13 is a cross-sectional view of a portion of an integrated architecture system according to aspects of the present disclosure.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be applied to a variety of other applications.

The present disclosure relates generally to improved computing architectures for improved data processing speed, including improved memory chips and controller chips. A generalized example of a memory array used in a memory chip is shown in fig. 1. Specifically, fig. 1 is an isometric view of a section of a three-dimensional cross-point memory array. The memory array 10 includes

memory cells

12a, 12b and

selectors

11a, 11 b. Between the memory cell 12a and the selector 11b are a certain number of word lines 13 extending in the X direction. Above the selector 11a are a number of bit lines 14a extending in the Y-direction, and below the memory cell 12b are a number of bit lines 14b extending in the Y-direction. Furthermore, as can be seen from fig. 1, the sequential structure of bit line-memory cell-selector-word line can be repeated in the Z-direction to achieve a stacked configuration. This stacked configuration allows for an increase in the density of memory cells used in each memory chip.

The first length along the Y-axis may be defined by a first word line adjacent a first end of the memory array 10 and a second word line adjacent a second end of the memory array 10, the second end being opposite the first end. The second length along the X-axis may be defined by a first bit line adjacent a third end of the memory array 10 and a second bit line adjacent a fourth end of the memory array 10, the fourth end opposite the third end. The surface area occupied by the memory array 10 may be defined by a first length x and a second length.

In use, activating the word line 13 and

bit lines

14a, 14b enables access to the values stored within the

individual memory cells

12a, 12 b. The accessed value can then be read or changed. The

corresponding selector

11a, 11b stacked on the

individual memory element

12a, 12b can then transmit the value of the

memory element

12a, 12b for use in computer operation.

Fig. 2 shows an exemplary computing device (or host system) 20 having a Central Processing Unit (CPU)21 and a main memory 22 attached to a circuit board 23. The main memory 22 may include at least one of volatile memory chips and/or non-volatile memory chips. The circuit board 23 may be a printed circuit board or a motherboard or the like. The size of the CPU 21 and the main memory 22 affects how far the CPU 21 and the main memory 22 are from each other on the circuit board 23. This distance, in turn, affects the logic efficiency, performance, and operating frequency of the computing device 20. For example, the greater the distance between the CPU 21 and the main memory 22, the slower the rate at which data and state is transferred and processed, and in addition, the reduced cache size. Further, the longer the distance, the greater the trace delay of the signal transmitted between the main memory 22 and the CPU 21, the lower the operating frequency of the computing device 20. Conversely, the smaller the distance between the central processing unit 21 and the main memory 22, the faster the transfer and processing of data and status, the larger the available cache size, and the lower the signal trace delay. The CPU 21 may alternatively be a Graphics Processing Unit (GPU).

Fig. 3 shows an exemplary storage device 30 having a controller 31 and a main memory 32 attached to a circuit board 33. The storage device 30 may be a flash memory drive or a Solid State Drive (SSD), or the like. The controller 31 may be a CPU or a GPU, and may include a bus interface unit (not shown). The main memory 32 may include at least one of volatile memory chips and/or non-volatile memory chips. The circuit board 33 may be a printed circuit board or a motherboard or the like. Similar to the CPU 21 and the main memory 22 of the computing device 20, the size of the controller 31 and the main memory 32 affects how far apart the controller 31 and the main memory 32 are on the circuit board 33. This distance affects both the system speed of the storage device 30 and the size of the circuit board 33. For example, the larger the distance between the controller 31 and the main memory 32, the slower the system speed of the storage device 30, and the larger the circuit board 33 that must accommodate the distance. As with the computing device 20, the longer the distance, the greater the trace delay of the signals transmitted between the main memory 32 and the CPU 31, and the lower the operating frequency of the storage device 30. Conversely, the smaller the distance between the controller 31 and the main memory 32 (and particularly the distance between the main memory 32 and the bus interface units within the controller 31), the faster the system speed of the storage device 30, the lower the signal trace delay, and the smaller the circuit board 33 may be. The circuit board 33 may be particularly advantageous because it will allow the storage device 30 to be smaller and more portable. The storage device 30 may be keyed to the computing device 20 so that both systems may be used simultaneously and cooperatively.

Fig. 4 shows a top view (from the Z direction) of a section of a memory chip 100 having a prior configuration. The section of memory chip 100 includes a memory array 110 and a wafer 120. Memory array 110 is similar to memory array 10 depicted in FIG. 1 and includes bit lines 114 similar to

bit lines

14a, 14b and word lines (not shown) similar to word line 13. Bit lines 114 extend in the Y-direction on memory chip 100 and include visible bit lines at the top layer as shown in fig. 1 and bit lines at the bottom line layer (not shown). The underlying bitlines are connected to the wafer 120 through bitline contacts 130. The word lines extend in the X-direction over the memory chip 100 and include underlying word lines connected to the wafer 120 by word line contacts (not shown) along the word line contacts 140. The total amount of occupied surface area of the wafer 120 is determined by the length in the Y-direction of the bitline contacts 130 extending from both vertical ends of the memory array 110 and the length in the X-direction of the wordline contacts 140 extending from both horizontal ends of the memory array 110. This may be, for example, a 20nm/20nm line/space (L/S) pattern.

Fig. 5 shows an exemplary illustration of a master controller 40 of a prior art configuration. Conventionally, the main controller 40 is used as a CPU, GPU or controller in a computing or storage device, as shown in fig. 2 and 3. The host controller 40 has a bus interface 41 and a memory cache 42 connected to a wafer 43. Bus interface 41 includes a number of interfaces (not shown) that interact with other portions of the computing or memory devices to which master controller 40 is connected, as is understood in the art. The memory cache 42 may be a Static Random Access Memory (SRAM) cache buffer.

As illustrated in fig. 4 and 5, respectively, the conventional memory chip 100 and the main controller chip 40 are inefficient due to their use of space on the

respective wafers

120, 43. For example, turning to fig. 4, memory chip 100 is inefficient because the occupied surface area consumes a significant portion of the area of wafer 120 because bitline contact 130 is spaced a distance along the Y-axis from the end of memory array 110. Referring to fig. 2 and 3, this distance may have a number of drawbacks in the case of including the memory chip 100 into the main memory 22 of the computing device 20 or the main memory 32 of the storage device 30. Due to the space consumed by the bit line contacts 130, the

main memory

22, 32 must be larger and correspondingly spaced further from the central processing unit 23 and the controller 33, thereby introducing many drawbacks to both the computing device 20 and the storage device 30, as described above. The improvement to the memory chip configuration over the prior memory chip configuration shown in fig. 4 can be seen in fig. 6 and 7.

Fig. 6 and 7 show a section of a memory chip 400 with a vertical connection configuration. Fig. 6 shows a top view (from the Z-direction) of a section of a memory chip 400. The segment of memory chip 400 includes a memory array 410 and a wafer 420 similar to memory array 110 and wafer 120 described above. Fig. 7 shows a cross-sectional side view (from the X-direction) of a section of memory chip 400 depicting only the bottom ones of bit lines 414. The underlying bitlines 414 are connected to the wafer 420 by a vertical connection arrangement in the Z-direction by means of bitline contacts 430. In this manner, the amount of occupied surface area of wafer 420 is determined by the shorter length in the Y-direction of only memory array 410 and the length in the X-direction of word line contacts 440 extending from both horizontal ends of memory array 410, as compared to the prior memory chip configuration of fig. 4.

Note that the substrate 420 may be formed of silicon, a silicon compound, a germanium compound, or the like. The bit line contacts 430 may be vertical interconnect VIAs (VIAs), such as through silicon VIAs, pads, or any other contact structure. The bit line contact 5n may be formed of an oxide layer. As used herein, the term "oxide" of an element should be understood to include additional elements in addition to the element and oxygen, including but not limited to dopants or impurities. As used herein, the term "nitride" of an element should be understood to include additional elements in addition to the element and nitrogen, including but not limited to dopants or impurities. Examples of such materials include, but are not limited to, metal nitrides such as TiN, TiAlN, TaN, BN, metal oxynitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with or without doping), reduced metal oxides such as TiOx (x <2 denotes reduction), metals such as W, Ni, CO, or carbon-based materials. According to an embodiment, the deposition may be accomplished by Chemical Vapor Deposition (CVD). In the process, a vacuum deposition method is adopted to generate a high-quality and high-performance solid material. In typical CVD, a wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposition.

As mentioned above, the reduction in the amount of occupied surface area of the wafer provides many improvements over existing memory chip configurations. Referring to fig. 2, implementing the memory chip 400 into the computing device 20 enables a reduction in the distance between the main memory 22 and the central processing unit 21 (e.g., from a separation on the order of centimeters to a separation on the order of micrometers). This reduced distance allows computing device 20 to have faster data and state transfer and processing rates, while increasing cache size. In the case of additionally using a 3D cross point memory array as shown in fig. 1 as at least one of the volatile and/or non-volatile memories in the main memory 22, the smaller the occupied area of the wafer, the more 3D cross point memory arrays are allowed to be fabricated on each wafer; thus, allowing for a denser memory array configuration per memory chip and reducing the cost per bit of manufacture compared to existing configurations, such as Direct Random Access Memory (DRAM).

In one example, a central processing unit chip may be bonded to a memory chip 400 having a 3D cross-point memory array. The central processing unit chip may have a core fabricated using a logic Complementary Metal Oxide Semiconductor (CMOS) process. The CMOS process is capable of producing a core comprising a metal oxide semiconductor field effect transistor. Complementary Metal Oxide Semiconductor (CMOS) processes, also known as complementary symmetric metal oxide semiconductor (COS-MOS), are one type of MOSFET (metal oxide semiconductor field effect transistor) fabrication process that uses complementary and symmetric pairs of p-type and n-type MOSFETs to implement logic functions. The primary function of a CMOS device is to process and store configuration settings of the basic input/output system (BIOS) of the device (such as, but not limited to, a computer). The CMOS devices are physical parts of the motherboard. Which is a memory chip that houses the arrangement configuration and is powered by an on-board battery. The CMOS is reset and all custom settings are lost in the case of battery power. When the CMOS loses power, the system clock is also reset. If the CMOS does not get power from the battery, it will revert to "factory set". Typically, the CMOS menu is accessed from the BIOS startup screen. The CMOS menu contains motherboard-enabled hardware customization options, uses a simple graphical interface and is controlled through a keyboard or other user interface. Custom features include, but are not limited to, memory manipulation, expansion port speed configuration, boot device sequencing, and power control. CMOS can also modify the device start-up process. This is important for system recovery, as CMOS may need to change boot priority from a hard drive to an optical drive, flash drive, or other drive to launch an operating system installer or to adjust which hard drive to use to load the operating system for a reboot. The central processing unit chip and the memory chip 200 may be bonded together by means of electrical interconnects formed at the bonding interface.

Referring to fig. 3, in the case where the vertical connection configuration is implemented in the storage device 30, the shortened distance between the main memory 32 and the controller 31 including the bus interface unit increases the system speed while allowing the size of the circuit board 33 to be reduced. With the additional use of 3D cross-point memory as shown in fig. 1 as at least one of the volatile and/or non-volatile memory in the main memory 32, the vertical connection configuration and 3D cross-point memory stack architecture results in faster storage than with some forms of memory, such as NAND flash memory, while having higher data storage capacity than other forms of memory, such as DRAM. Furthermore, the use of the vertical connection configuration and the 3D cross-point memory enables shorter fabrication cycle times with higher die-to-chip yield. This is because there is less interaction or dependency between the manufacturing process of a wafer for a central processing unit and a wafer for SSDs used in memory chip manufacturing, first. Second, the final yield of memory chips of the memory device can be improved with the vertically stacked memory structure by using a die hybrid bonding process known in the art.

Turning back to FIG. 5, the host controller chip 40 is inefficient because the surface area occupied by the memory cache 43 and the several of the bus interfaces 41 increases the size of the host controller chip 40. Referring to fig. 2 and 3, in the case where the main controller chip 40 is used as the CPU 21 of the computing device 20 or the controller 31 of the storage device 30, this increased size may have many drawbacks. For example, the increased size of the main controller chip 40 may increase the size of the CPU 31 or the controller 31, which would result in an increased distance between the CPU 21 and the main memory 22 or between the controller 31 and the main memory 32. This increased distance introduces a number of drawbacks to both the computing device 20 and the storage device 30, as described above. In the following, an improvement of the main controller chip configuration over the existing main controller chip shown in fig. 5 can be seen from fig. 8 and 9 by a combination of Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) configuration.

An ASIC chip is an integrated circuit chip designed and manufactured for specific and customized purposes, such as to meet the needs of a particular user or a particular electronic system, etc. When compared to other electronic circuit chips (such as FPGA chips), execution speeds may be faster, some unused logic implementations may be eliminated, and batch manufacturing costs may be lower. In most cases, ASIC chips are capable of achieving higher performance, lower power consumption, better thermal performance, and improved radiation immunity.

An FPGA chip is an integrated circuit chip that is further developed on the basis of programmable logic devices such as Programmable Array Logic (PAL), Generic Array Logic (GAL), and Complex Programmable Logic Devices (CPLD). FPGAs have a high degree of functional flexibility due to their programmable capabilities, which can be configured with their programmable architecture to implement any desired combination of logic gates (e.g., and, or, xor, not) or more complex functions (e.g., decoding or mathematical equations). The editable components in most FPGA chips also contain memory components, such as flip-flops or other more complete memory blocks. Furthermore, the algorithms may be implemented in a parallel manner, thereby subjecting large amounts of data to faster, more efficient processing.

Fig. 8 and 9 show a main controller chip 200 having an ASIC or FPGA configuration. Specifically, FIG. 8 shows a top view of the main controller chip 200. The master controller chip 200 has a substantially rectangular configuration with the surface area of the wafer 207 occupied by

circuit rows

205a, 205b, 205c, 205d extending in the X-direction and

circuit columns

206a, 206b extending in the Y-direction. Wafer 207 is similar to wafer 420 discussed above in connection with fig. 6 and 7. The

circuit rows

205a, 205b, 205c, 205d and

circuit columns

206a, 206b include a circuit block 204 and several logic circuits including a low power double data rate memory (LPDDR)201, interrupt line 202 and clock management circuit 203. The circuit column 206a is separated from the circuit column 206b by the clock management circuit 203. Circuit block 204 may be at least one of a configurable logic block or a 3D cross-point memory array similar to memory array 10 as shown in fig. 1.

In an alternative aspect, there may be any number or combination of circuit blocks 204 and logic circuits. For example, the master controller chip 200 may only have LPDDR 201 spaced between every three smaller columns of circuit blocks 204 without interrupt lines 202 or clock management circuitry 203. In another example, the memory chip 200 may have more or less than four

circuit rows

205a, 205b, 205c, 205d, or more or less than two

circuit columns

206a, 206b, such as five, six, seven, or any other number. In yet another example, there may be any number of smaller circuit rows within

circuit rows

205a, 205b, 205c, 205d and smaller circuit columns within

circuit columns

206a, 206 b.

Fig. 9 shows a cross-sectional view of a portion of a main controller chip 200 having a circuit block area 210, a logic area 220, a wafer area 230, and a back end of line (BEOL) area 240. The circuit block area 210 corresponds to a cross-sectional view of a portion of the circuit block 204, wherein the circuit block 204 is a configurable logic block. The logic area 220 corresponds to a cross-sectional view of a portion of logic circuitry, such as LPDDR 201, interrupt line 202, and clock management circuitry 203. The wafer area 230 corresponds to a cross-sectional view of a portion of the wafer 207.

The BEOL area 240 includes an interface 211 connected to the wafer 230 through the interconnects 208 and connectors 209. The connectors 209 generally extend away from the wafer 230 and include segments that extend in various directions parallel to the wafer 230, but only the connectors 209 and their segments are shown extending along the interface of the cross-section shown in fig. 7. The connectors 209 extend to the interconnects 208 arranged in a substantially two-dimensional grid on the interface 122 parallel to the wafer 207. Connector 209 may be a contact adapted for use with a cross-point memory array, an electrical element adapted to interface with elements of the circuit block area 210 and logic area 220, or any other conductive feature. Typically, a large number of interconnects 208 will be associated with any wafer. For example, one million or more interconnects 208 may be associated with the wafer 207.

Interface 211 has a planar structure that retains interconnect 208 such that interconnect 208 extends through interface 211 so as to be accessible on both sides of the structure. Each connector 209 is in contact with and in electrical communication with at least one interconnect 208. The interconnect 208 is a conductive element that may be composed of any sufficiently conductive material (e.g., copper) and may be a vertical interconnect VIA (VIA). Additional circuitry may be bonded on top of interface 211 through interconnect 208. For example, a memory chip (e.g., memory chip 400) may be bonded to the host controller chip 200 by bonding with the interconnect 208 and the interface 211.

Although FIG. 9 shows portions of master controller chip 200 including both circuit block area 210 and logic area 220, in an alternative aspect, master controller chip 200 may include only circuit block area 210. For example, fig. 9 shows a cross-sectional view of a portion of a main controller chip 300 having a BEOL area 340 and a wafer area 330 as described above. In this aspect, the main controller chip 300 has no logic area and includes only the circuit block area 310. In another alternative aspect, only a portion of the logic area 220 is formed on the main controller chip.

As briefly discussed, it is desirable to have as high a circuit operating frequency as possible (within an ASIC or FPGA chip). The operating frequency of the circuit is primarily related to register-to-register signal propagation delay and "clock skew". Clock skew (sometimes referred to as timing skew) is a phenomenon in synchronous digital circuitry, such as computer systems, in which clock signals of the same source arrive at different components at different times. The instantaneous difference between the readings of any two clocks is referred to as their skew. If the clock is long in the FPGA, the clock skew is small and substantially negligible. For simplicity, only signal propagation delay factors are considered herein, including the switching delay of the registers and combinational logic cells (determined by the physical characteristics of the device). Delays, especially trace delays, can be reduced by improving the layout of the floor plan (reducing latency by reasonable design, reduced combinational logic cells, and avoiding large combinational logic cells). For example by adding appropriate constraints to the synthesizer (typically adding a 5% margin is more appropriate, such as adding a constraint to 105Mhz when the circuit is operating at 100 Mhz). However, adding too much influence is disadvantageous to the entire system because it greatly increases the synthesis time. Therefore, having the relevant logic cells as close to the wiring as possible will reduce the delay of the traces. One reason FPGAs are mainly used in medium and low-volume chips and have not replaced high-capacity, high-volume chips is the high cost. On the other hand, 3D Xpoint as a main memory also has a problem that the bit line contact occupies an excessive silicon area and a floor plan.

Thus, with reference to fig. 2 and 3, implementing the master controller chip 200 as a CPU 21 or controller 31 in the computing device 20 and the memory device 30 allows for greater data processing capabilities (especially when processing large amounts of data), lower power consumption, better thermal performance, and improved radiation immunity. This is due at least in part to the reduction in occupied surface area of the wafer 207 of the master controller chip 200 as compared to the prior configuration of the wafer 43 of the master controller chip 40 as shown in fig. 5. In particular, the configuration of the main controller chip 200 allows the elimination of traditional SRAM memory cache buffers, such as the memory cache 42, because there is no need to write to the read-write cache or store an update record of the logical-physical address table. Further, the number of interfaces (e.g., those within bus interface 41) may be reduced. In this way, the die size of the main controller chip 200 can be reduced compared to the existing configuration of the main memory chip 40. This brings about a decrease in connection distance between elements of the circuit within the computing device 20 or the memory device 30, a decrease in signal delay and power consumption, an increase in data processing and data access speed, and an improvement in integration of the main controller chip 200 with the

main memories

22, 33.

Fig. 11-13 illustrate a method for forming a 3D cross-point memory chip 500, for example, to be used as the circuit block 204 in the main controller chip 200. Fig. 11 illustrates the formation of a wafer region 530 having a circuit block region 510 and a logic region 520 similar to the corresponding structure depicted in fig. 9.

Fig. 12 illustrates the deposition of a BEOL region 540 on the circuit block region 510 of the wafer region 530. The BEOL regions 540, as well as other BEOL regions mentioned throughout this disclosure, may be deposited according to any suitable method, for example, using a CMOS die process, which may create a hybrid bonded CMOS die. The BEOL area 540 includes several connectors 509a that extend generally away from the wafer 530. Similar to the corresponding structures depicted in fig. 6, 7, and 9, the 3D cross-point memory array 550 extends from the connector 509a through bit line contacts 512.

FIG. 13 shows that connectors 509b are arranged in layers over connectors 509a in logic area 520 such that connectors 509b are suspended above memory array 550. Interface 511 is then connected to connector 509b by millions of interconnects 508, similar to the corresponding structure depicted in fig. 9. In an alternative aspect, the 3D cross-point memory chip 500 may be fabricated without the logic region 520 or with only a portion of the logic region 520.

In another method of manufacture, a memory chip (e.g., memory chip 500) may be bonded to a master controller chip (such as master controller chip 200) to form a single chip stacked integrated architecture system, such as by using Yangtze river memory technologies, Inc. as

The technique of push-out.

The wafer-level 3D IC technology platform is used for directly bonding a plurality of wafers by utilizing a semiconductor nanoscale interconnection technology. In this way, the single chip stacked integrated architecture system further shortens the distance between the control chip and the memory of the system by enabling the memory chip and the control chip to be vertically stacked on top of each other to form a single chip.This in turn reduces the undesirable parasitic resistance capacitance effects, further improves system integration, shortens the manufacturing process, reduces PCB board ratios, and increases the process window for circuit design of the computing device 20 and memory device 30.

Referring to fig. 9 and 13, the wafer area 530 of the memory chip may be bonded to the interface 211 through the interconnect 208 of the master controller chip 200, thereby forming a single-chip stacked integrated architecture system. The memory chip 500 may be incorporated into both volatile and non-volatile memory systems to allow faster data processing and transfer with greater efficiency. In an alternative aspect, the memory chip 500 is introduced into only one of the volatile or nonvolatile memories.

The bonding process described above may be accomplished by wafer level bonding, wherein a single chip stacked integrated architecture is formed by bonding all printed wafers prior to dicing into chips and/or dies for packaging. Alternatively, a single chip stacked integrated architecture system may be formed by chip-level bonding, wherein all wafers are diced into individual chips and/or dies prior to undergoing the bonding process. In yet another alternative aspect, a single chip stacked integrated architecture may be formed by chip/die to wafer level bonding, where at least one wafer is divided into chips and/or dies before bonding to at least one complete wafer, and then subjected to further dicing for packaging.

Most of the foregoing alternative examples are not mutually exclusive and may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features described above can be employed without departing from the subject matter defined in the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined in the claims. As an example, the foregoing operations do not necessarily have to be performed in the exact order described above. Rather, the various steps may be manipulated in a different order, such as reverse order or simultaneously. Steps may also be omitted unless otherwise indicated. Furthermore, the provision of examples described herein and terms expressed as "such as … …," "including … …," etc., should not be construed as limiting the claimed subject matter to specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Moreover, the same reference numbers may be used throughout the different drawings to refer to the same or like elements.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A solid state storage device comprising:

a controller chip comprising:

a controller wafer;

a first set of connectors of the plurality of connectors, the first set of connectors having a first portion and a second portion;

a circuit block wafer bonded to the controller through the first portion of the first set of connectors;

an interface engaged with the second portion of the first set of connectors by a plurality of interconnects; and

a memory chip engaged with the interface of the controller chip, the memory chip comprising:

a memory wafer;

a first storage array comprising:

a plurality of memory cells;

a plurality of selectors;

a plurality of word lines coupled to the selector, a first word line of the plurality of word lines adjacent a first end of the first memory array and a second word line of the plurality of word lines adjacent a second end of the memory array; and

a plurality of bit lines coupled to the memory cells;

a plurality of word line contacts coupling the plurality of word lines to the memory wafer; and

coupling the plurality of bit lines to a first plurality of bit line contacts of the plurality of connectors.

2. The memory device of claim 1, wherein the first memory array of the memory chip is a three-dimensional memory array, wherein:

the plurality of memory cells having a first end and a second end;

the plurality of selectors having first and second ends, the second ends of the plurality of selectors coupled to the first ends of the plurality of memory cells;

the plurality of word lines are coupled to the first ends of the plurality of selectors; and is

The first plurality of bit lines are coupled to the second ends of the plurality of memory cells.

3. The memory device of claim 1, wherein the first plurality of bitline contacts runs along a length of the memory wafer defined by the first wordline and the second wordline.

4. The memory device of claim 1, wherein the controller chip further comprises a portion of logic circuitry adjacent to the circuit block, the portion of logic circuitry comprising:

a second set of connectors of the plurality of connectors, the second set of connectors having a first portion and a second portion, the first portion of the second set of connectors engaged with the controller die and the second portion of the second set of connectors engaged with the plurality of interconnects.

5. The memory device of claim 1, wherein the controller chip further comprises a second memory array, wherein the first set of connectors has a third portion, and the second memory array is joined with the third portion of the first set of connectors by a second plurality of bit line contacts.

6. The storage device of claim 5, wherein the second storage array is a three-dimensional storage array comprising:

a plurality of memory cells having a first end and a second end;

a plurality of selectors having first and second ends, the second ends of the plurality of selectors coupled to the first ends of the plurality of memory cells;

a plurality of word lines coupled to the first ends of the plurality of selectors; and

a plurality of bit lines coupled to the second ends of the plurality of memory cells, the second plurality of bit line contacts adjacent to the plurality of bit lines of the second memory array.

7. A method of forming a stacked architecture system, comprising:

forming a controller chip on a first wafer, the controller chip comprising:

a controller wafer;

a circuit block wafer bonded to the controller through the first portion of the first set of connectors; and

an interface engaged with the second portion of the first set of connectors by a plurality of interconnects;

forming a memory chip on a second wafer, the memory chip comprising:

a memory wafer;

a first storage array comprising:

a plurality of memory cells;

a plurality of selectors;

a plurality of bit lines coupled to the memory cells;

coupling the plurality of bit lines to a first plurality of bit line contacts of the plurality of connectors; and

bonding the first wafer to the second wafer to form the stacked architecture system.

8. The method of claim 7, wherein the controller chip is formed by a CMOS process.

9. The method of claim 7, wherein the first storage array of the memory chip is a three-dimensional storage array, wherein:

the plurality of memory cells having a first end and a second end;

10. The method of claim 9, wherein the memory chip is a non-volatile memory and a volatile memory.

11. The method of claim 7, wherein the method further comprises at least one of:

forming a portion of a first logic circuit on the first wafer; or

A portion of a second logic circuit is formed on the second wafer.

12. The method of claim 11, wherein a portion of the first logic circuit and/or a portion of the second logic circuit is formed by a CMOS process.

13. The method of claim 7, wherein the method further comprises dicing at least one of the first and second wafers prior to the bonding step.

14. The method of claim 7, wherein the method further comprises dicing the stacked architecture system.

15. A computing device, comprising:

a controller chip comprising:

a controller wafer;

a memory wafer;

a first storage array comprising:

a plurality of memory cells;

a plurality of selectors;

a plurality of bit lines coupled to the memory cells;