CN112448365B - Short-circuit protection circuit and method and electronic equipment - Google Patents

Short-circuit protection circuit and method and electronic equipment Download PDF

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CN112448365B
CN112448365B CN202011270805.XA CN202011270805A CN112448365B CN 112448365 B CN112448365 B CN 112448365B CN 202011270805 A CN202011270805 A CN 202011270805A CN 112448365 B CN112448365 B CN 112448365B
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node
circuit
waveform
short
bus
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CN112448365A (en
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邵枝晖
崔博
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Beijing Neuron Network Technology Co ltd
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Beijing Neuron Network Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/50—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to the appearance of abnormal wave forms, e.g. ac in dc installations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • General Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

The application provides a short-circuit protection circuit and a short-circuit protection method, and electronic equipment. The short-circuit protection circuit is applied to nodes of a two-wire system bus, the two-wire system bus comprises a control node and a user node which are connected to the bus in parallel, a transmission port of the node is connected to the two-wire system bus in parallel, the short-circuit protection circuit comprises a protection switch and a control circuit, and the protection switch is connected between the node and the bus; the control circuit outputs standard waveforms of nodes, couples the standard waveforms of the nodes to the nodes through a bus, recovers the waveforms of the nodes, controls the on-off of the protection switch according to the recovered waveform amplitude of the nodes, and switches on or off the connection between the nodes and the bus so as to perform short-circuit protection.

Description

Short-circuit protection circuit and method and electronic equipment
Technical Field
The application relates to the technical field of high-speed industrial communication system communication, in particular to a short-circuit protection circuit and method of a user node interface and electronic equipment.
Background
The current two-wire industrial control bus interface generally comprises a parallel loop formed by a control node and a user node. A long line topology is generally formed by adopting a section of differential line, and two ends of the long line topology are open or are matched with terminating resistors. Or a closed loop configuration.
In general bus interface short-circuit protection, a fuse or an overcurrent protection circuit is added on a path connecting a node and a bus, and the fuse or the overcurrent protection circuit is adopted to block signal output so as to achieve the purpose of limiting short-circuit current, so that a power device or an internal circuit is prevented from being burnt, and the safety of a corresponding circuit module is protected.
However, this protection, fuse or overcurrent protection circuit range is not precise enough or it is difficult to completely disconnect the short-circuit node from the line. The interface short-circuit fault of the node may cause signal transmission faults of other nodes, cause a whole network fault or a partial fault, and cause network breakdown.
Therefore, the short-circuit protection design of the communication node interface has very important significance for the continuous operation of the system after the line is accidentally short-circuited.
Disclosure of Invention
The embodiment of the application provides a short-circuit protection circuit, which is applied to a node on a two-wire bus, wherein a transmission port of the node is connected to the two-wire bus, the short-circuit protection circuit comprises a protection switch and a control circuit, and the protection switch is connected between the node and the bus; the control circuit outputs standard waveforms of nodes, couples the standard waveforms of the nodes to the nodes through a bus, recovers the waveforms of the nodes, controls the on-off of the protection switch according to the recovered waveform amplitude of the nodes, and switches on or off the connection between the nodes and the bus so as to perform short-circuit protection.
According to some embodiments, the control circuit comprises a controller, a signal output circuit, a signal acquisition circuit and a transformer, the controller outputs a standard waveform of a node to the signal output circuit, the signal acquisition circuit acquires the waveform of the node, the on-off of the protection switch is controlled according to the waveform amplitude of the acquired node, and the node is connected with or disconnected from the bus so as to perform short-circuit protection; the signal output circuit is connected with a second secondary winding of the transformer and the controller, the signal output circuit transmits the standard waveform of the node output by the controller to the second secondary winding of the transformer, and the standard waveform of the node is coupled to the node through the second secondary winding and the primary winding of the transformer; the signal acquisition circuit is connected with a first secondary winding of a transformer and the controller, the waveform of the node is coupled to the first secondary winding of the transformer through a primary winding of the transformer, and the signal acquisition circuit acquires the waveform of the node from the first secondary winding of the transformer and transmits the waveform to the controller; the transformer comprises the primary winding, the first secondary winding and the second secondary winding.
According to some embodiments, the short-circuit protection circuit is disposed in the node.
According to some embodiments, the controller controls the protection switch to be closed to turn on the node and the bus when the amplitude of the input waveform is normal, and controls the protection switch to be opened to turn off the node and the bus when the amplitude of the input waveform is abnormal or no signal exists.
According to some embodiments, the two-wire bus comprises at least one of a non-ring network bus, a single ring network bus, or a dual ring network bus.
According to some embodiments, the signal bandwidth of the protection switch is greater than 35MHz, and the slew rate is 440-4400V/us.
According to a second aspect of the present application, there is provided a short-circuit protection method applied to the short-circuit protection circuit described above, where the short-circuit protection method is executed at a controller startup stage of the control circuit, and the short-circuit protection method includes: the control circuit outputs a standard waveform of a node and is coupled to the node; the waveform of the extraction node; and controlling the on-off of the protection switch according to the waveform amplitude of the recovered node, and switching on or off the connection between the node and the bus so as to perform short-circuit protection.
According to some embodiments, the control circuit outputs a standard waveform at a node and is coupled to the node, including: the controller outputs the standard waveform of the node to a signal output circuit, the signal output circuit transmits the standard waveform of the node to a second secondary winding of the transformer, and the standard waveform of the node is coupled to the node through the second secondary winding and a primary winding of the transformer.
According to some embodiments, the waveform of the extraction node comprises: the waveform of the node is coupled to a first secondary winding of the transformer through a primary winding of the transformer, and the signal acquisition circuit acquires the waveform of the node from the first secondary winding of the transformer and sends the waveform to the controller.
According to a third aspect of the present application, there is provided an electronic device comprising one or more processors, memory for storing one or more programs; when executed by the one or more processors, cause the one or more processors to perform the method as described above.
According to the technical scheme provided by the embodiment of the application, after the node interface of the two-wire bus is short-circuited, whether the node interface has the short circuit or not can be judged by measuring the waveform amplitude of the node of the two-wire bus, the fault node can be accurately and quickly disconnected during the short circuit, and the operation of other normal nodes on the bus is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a two-wire bus of a single-ring network according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a dual-ring network two-wire bus according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a connection between two-wire bus nodes in a single ring network according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a dual-ring network two-wire bus node connection according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a short-circuit protection circuit according to an embodiment of the present disclosure.
Fig. 6 is a second circuit diagram of a short-circuit protection circuit according to an embodiment of the present application.
Fig. 7 is a schematic flowchart of a short-circuit protection method according to an embodiment of the present disclosure.
Fig. 8 is a second schematic flowchart of a short-circuit protection method according to an embodiment of the present application.
Fig. 9 is a functional block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be understood that the terms "first", "second", etc. in the claims, description, and drawings of the present application are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
A two-wire bus, also known as a fieldbus broadband bus, a two-wire industrial control bus or an AUTBUS bus.
Fig. 1 is a schematic view of a two-wire bus of a single ring network provided in an embodiment of the present application, and fig. 2 is a schematic view of a two-wire bus of a dual ring network provided in the embodiment of the present application.
The two-wire industrial control bus interface consists of a control node CN and more than one user node TN n Forming a loop. And a section of differential line connection is adopted, as shown in figures 1 and 2.
The two-wire bus may be a non-ring network bus, a single ring network, or a bus including two ring networks.
Referring to fig. 1, a two-wire industrial control bus in the form of a single ring network. The bus is formed by a differential pair ring bus, the Transmitter (TX) and Receiver (RX) of each node device form a first transmission port through a differential pair twisted pair, and the node devices are connected to the two-wire ring field bus through the first transmission port, as shown in fig. 3.
When the differential line of one node on the two-wire bus of the ring network is short-circuited, the differential line of the ring network bus is short-circuited, so that the differential lines of other nodes are short-circuited, a power device or an internal circuit is easily burnt, the ring network fails, the impedance of a short-circuit point is 0, signals of other nodes cannot be transmitted, and the fault of the whole network is caused.
Further, as shown in fig. 2, the bus may also adopt a dual-ring network two-wire ring topology. Specifically, the first transmission port is converted into two second transmission ports through three one-to-two connectors, and the two second transmission ports are respectively connected with the two ring network buses. The one-to-two connector includes, but is not limited to, a one-to-two T-type connector or a one-to-two Y-type connector.
According to some embodiments, each node device is connected to the two-wire ring field bus via a T-connector, as shown in FIG. 4. The first transmission port of the node device is connected to a first two-wire ring field bus through a one-to-two T-type head connector A and a one-to-two T-type head connector B, and is connected to a second two-wire ring field bus through a one-to-two T-type head connector A and a one-to-two T-type head connector C. Specifically, one outlet of the one-to-two T-shaped head connector A is connected with an inlet of the one-to-two T-shaped head connector B, the other outlet of the one-to-two T-shaped head connector A is connected with an inlet of the one-to-two T-shaped head connector C, two outlets of the one-to-two T-shaped head connector B are connected to one two-wire ring-shaped field bus, and two outlets of the one-to-two T-shaped head connector C are connected to the other two-wire ring-shaped field bus.
When a node on the two-wire bus of the dual-ring network is short-circuited, that is, a differential line of the node is short-circuited, a short circuit also occurs between two ring network buses of the dual-ring network bus, which easily causes burning of a power device or an internal circuit, the ring network fails, the impedance of a short circuit point is 0, and signals of other nodes cannot be transmitted, thereby causing a fault of the whole network.
As can be seen, short circuit protection is very important to increase the reliability of the bus. In general bus interface short-circuit protection, a fuse or an overcurrent protection circuit is added on a path connecting a node and a bus to block signal output, so that the purpose of limiting short-circuit current is achieved, and the safety of a corresponding circuit module is protected. But the fuse or overcurrent protection circuit range is not accurate enough. The interface short-circuit fault of the node may cause signal transmission faults of other nodes, cause a whole network fault or a partial fault, and cause network breakdown.
Fig. 5 is a schematic diagram of a short-circuit protection circuit provided in the present application.
As shown in fig. 5, the short-circuit protection circuit is applied in a node on a two-wire ring fieldbus. The two-wire bus comprises a control node CN and a user node TN which are connected in parallel on the bus n And the transmission ports of the nodes are connected to the two-wire bus in parallel.
The short-circuit protection circuit is provided in the node. The short-circuit protection circuit comprises a protection switch K1 and a control circuit. The protection switch K1 is connected between the node and the bus. The control circuit outputs standard waveforms of the nodes, the standard waveforms of the nodes are coupled to the nodes through the bus, the waveforms of the nodes are recovered, the on-off of the protection switch is controlled according to the waveform amplitude of the recovered nodes, and the connection between the nodes and the bus is switched on or off to carry out short-circuit protection.
According to the technical scheme provided by the embodiment, after the node interface of the two-wire bus is short-circuited, whether the node interface has a short circuit can be judged by measuring the waveform amplitude of the node of the two-wire bus, and a fault node can be accurately and quickly disconnected during short circuit, so that the operation of other normal nodes on the bus is ensured.
Fig. 6 is a second circuit diagram of a short-circuit protection circuit provided in the present application.
As shown in fig. 6, the short-circuit protection circuit is applied to a node of a two-wire bus. Optionally, the two-wire bus is a single ring network bus, a dual ring network bus, or a non-ring network bus, but not limited thereto. The two-wire bus comprises a control node CN and a user node TN which are connected in parallel on the bus n 。
The short-circuit protection circuit of the user node interface comprises a protection switch K 1 And a control circuit.
Protective switch K 1 Connected between the node and the bus. The control circuit outputs the standard waveform of the node, couples the standard waveform of the node to the node through a bus, recovers the waveform of the node, controls the on-off of a protection switch according to the waveform amplitude of the recovered node, and switches on or off the connection between the node and the bus to carry out short circuitAnd (4) protecting.
The control circuit comprises a transformer BALUN, a controller KY3000S, a signal output circuit and a signal acquisition circuit.
The transformer BALUN includes a primary winding zTs, a first secondary winding xTs, and a second secondary winding yTs. The primary winding zTs, the first secondary winding xTs, and the second secondary winding yTs are all coupled to a bus at a node.
The controller KY3000S outputs the standard waveform of the node to the signal output circuit. The signal output circuit is connected with the second secondary winding yTs of the transformer and the controller, the signal output circuit transmits the standard waveform of the node output by the controller to the second secondary winding yTs of the transformer, and the standard waveform of the node is coupled to the node through the second secondary winding yTs and the primary winding zTs of the transformer. The signal acquisition circuit is connected with the first secondary winding xTs of the transformer and the controller, the waveform of a node is coupled to the first secondary winding xTs of the transformer through the primary winding zTs of the transformer, and the signal acquisition circuit acquires the waveform of the node from the first secondary winding xTs of the transformer and sends the waveform to the controller. The controller KY3000S utilizes the waveform of the signal acquisition circuit extraction node to control the on-off of the protection switch according to the waveform amplitude of the extraction node, and the connection between the node and the bus is switched on or off to perform short-circuit protection.
The controller KY3000S includes a waveform output port and a waveform input port. The controller KY3000S controls to output the standard waveform to the waveform output port TX _ out, and collects the input waveform from the waveform input port RX _ in.
The signal output circuit is connected with the second secondary winding yTs and the waveform output port TX _ out of the controller KY3000S, and outputs the standard waveform to the signal output circuit from the waveform output port TX _ out of the controller KY 3000S. The signal output circuit comprises a switch K, a third capacitor C3, a fourth capacitor C4, a line driver LINEDRIVER, a third resistor R3 and a fourth resistor R4.
As shown in fig. 6, one end of the double-throw switch K is connected to both ends of the second secondary winding yTs, and the other end is connected to the third capacitor C3 and the fourth capacitor C4, respectively. The other ends of the third capacitor C3 and the fourth capacitor C4 are connected to the line driver LINEDRIVER. The other end of the line driver LINEDRIVER is connected to the third resistor R3 and the fourth resistor R4, respectively. The other ends of the third resistor R3 and the fourth resistor R4 are respectively connected to a waveform output port TX _ out of the controller KY 3000S. The standard waveform output from the waveform output port TX _ out is subjected to primary amplification by a line driver LINEDRIVER, and reaches the second secondary winding yTs.
The signal acquisition circuit is connected with the first secondary winding xTs and a waveform input port RX _ in of a controller KY3000S, and acquires a waveform of the first secondary winding xTs. The signal acquisition circuit comprises a third capacitor C1, a fourth capacitor C2, a third resistor R1 and a fourth resistor R2.
As shown in fig. 6, two ends of the first secondary winding xTs are respectively connected to one ends of the third capacitor C1 and the fourth capacitor C2, the other ends of the third capacitor C1 and the fourth capacitor C2 are respectively connected to one ends of the third resistor R1 and the fourth resistor R2, and the other ends of the third resistor R1 and the fourth resistor R2 are respectively connected to two ends of the waveform input port RX _ in of the controller KY 3000S.
When the amplitude of the input waveform is normal, the controller KY3000S outputs a control protection switch K through a switch signal SW2 1 And the node and the bus are closed and conducted, and external communication can be realized. The controller KY3000S outputs the control protection switch K through the switch signal SW2 when the amplitude of the input waveform is abnormal (such as short circuit or low resistance) or no signal (such as open circuit) 1 And (4) disconnecting the node and the bus, and not communicating externally. Meanwhile, the normal communication of other nodes on the bus is not influenced by the fault of the interface.
Optionally, a protection switch K 1 Including, but not limited to, analog switches.
In the present embodiment, the protection switch K 1 An analog switch was selected, model MAX4546. The bus adopts CAT5 twisted pair, CN is the main node, TN is the slave node, each node includes controller KY3000S and protection switch K 1 Protection switch K 1 The signal bandwidth of (2) is more than 35MHz, and the slew rate is between 440 and 4400V/us.
Through a plurality of tests, the bus communication can normally and accurately detect the short-circuit condition of the node and reliably disconnect the node in the power-on self-test stage, and normal networking of other nodes is guaranteed.
Fig. 7 is a schematic flow chart of a short-circuit protection method provided in the present application. The short-circuit protection method is applied to the short-circuit protection circuit as described above.
In S110, the control circuit outputs the standard waveform of the node and couples the standard waveform of the node to the node.
Specifically, self-test is performed during the boot-up phase, and the control circuit outputs the standard waveform of the node and couples the standard waveform of the node to the node.
In S120, the waveform of the node is extracted.
The control circuit extracts the waveform of the node.
In S130, the control circuit controls the on/off of the protection switch according to the waveform amplitude of the retrieved node, and turns on or off the connection between the node and the two-wire bus to perform short-circuit protection.
The control circuit judges whether the node is short-circuited according to the amplitude of the node waveform, controls the protection switch to be closed when the amplitude of the input node waveform is normal, conducts the node and the two-wire bus, and controls the protection switch K when the amplitude of the input node waveform is abnormal or no signal 1 And disconnecting the node and the two-wire bus.
Fig. 8 is a schematic flow chart of a short-circuit protection method provided in the present application.
In S210, the controller outputs the standard waveform of the node and couples the standard waveform to the node through the signal output circuit.
Specifically, self-test is carried out in the startup stage of the controller, a standard waveform of a waveform output port TX _ out output node of the controller KY3000S is output to a signal output circuit, the signal output circuit transmits the standard waveform of the node output by the controller KY3000S to a second secondary winding yTs of the transformer BALUN, and the standard waveform of the node is coupled to the node through a second secondary winding yTs and a primary winding zTs of the transformer BALUN.
In S220, the signal acquisition circuit acquires a waveform of the node.
The waveform of the node is coupled to a first secondary winding xTs of the transformer through a primary winding zTs of the transformer BALUN, and a signal acquisition circuit acquires the waveform of the node from a first secondary winding xTs of the transformer BALUN and sends the waveform to a waveform input port RX _ out of a controller KY 3000S.
In S230, the controller controls the on/off of the protection switch according to the waveform amplitude of the retrieved node, and turns on or off the connection between the node and the two-wire bus to perform short-circuit protection.
The controller judges whether the node is short-circuited according to the amplitude of the node waveform input from the waveform input port RX _ out, the controller KY3000S controls the protection switch to be closed when the amplitude of the input node waveform is normal, the node and the two-wire bus are conducted, and controls the protection switch K when the amplitude of the input node waveform is abnormal or no signal exists 1 And disconnecting the node and the two-wire bus.
Fig. 9 is a functional block diagram of an electronic device according to an embodiment of the present disclosure.
The electronic device may include an output unit 301, an input unit 302, a processor 303, a storage 304, a communication interface 305, and a memory unit 306.
The memory 304, which is a non-transitory computer-readable memory, may be used to store software programs, computer-executable programs, and modules. The one or more programs, when executed by the one or more processors 303, cause the one or more processors 303 to implement the methods as described above.
The memory 304 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the electronic device, and the like. Further, the memory 304 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 304 may optionally include memory located remotely from the processor 303, which may be connected to the electronic device via a network.
The foregoing embodiments have been described in detail to illustrate the principles and implementations of the present application, and the foregoing embodiments are only used to help understand the method and its core idea of the present application. Meanwhile, a person skilled in the art should, according to the idea of the present application, change or modify the embodiments and applications of the present application based on the scope of the present application. In view of the above, the description should not be taken as limiting the application.

Claims (9)

1. A short-circuit protection circuit for use in a node on a two-wire bus, a transmit port of the node being coupled to the two-wire bus, the short-circuit protection circuit comprising:
a protection switch connected between the node and the bus;
the control circuit outputs the standard waveform of the node, couples the standard waveform of the node to the node through a bus, recovers the waveform of the node, controls the on-off of the protection switch according to the recovered waveform amplitude of the node, and switches on or off the connection between the node and the bus so as to perform short-circuit protection;
the control circuit includes:
the controller outputs the standard waveform of the node to the signal output circuit, and controls the on-off of the protection switch by utilizing the waveform of the node recovered by the signal acquisition circuit according to the waveform amplitude of the recovered node, so as to switch on or off the connection between the node and the bus and carry out short-circuit protection;
the signal output circuit is connected with a second secondary winding of the transformer and the controller, the signal output circuit transmits the standard waveform of the node output by the controller to the second secondary winding of the transformer, and the standard waveform of the node is coupled to the node through the second secondary winding and the primary winding of the transformer;
the signal acquisition circuit is connected with a first secondary winding of a transformer and the controller, the waveform of the node is coupled to the first secondary winding of the transformer through the primary winding of the transformer, and the signal acquisition circuit acquires the waveform of the node from the first secondary winding of the transformer and transmits the waveform to the controller;
and the transformer comprises the primary winding, the first secondary winding and the second secondary winding.
2. The short-circuit protection circuit of claim 1, wherein the control circuit is disposed in a two-wire bus chip.
3. The short-circuit protection circuit of claim 1, wherein the controller controls the protection switch to be closed to turn on the node and the bus when the amplitude of the input waveform is normal, and controls the protection switch to be opened to turn off the node and the bus when the amplitude of the input waveform is abnormal or no signal exists.
4. The short-circuit protection circuit of claim 1, wherein the two-wire bus comprises at least one of a non-ring bus, a single ring bus, or a dual ring bus.
5. The short-circuit protection circuit of claim 1, wherein the signal bandwidth of the protection switch is greater than 35MHz, and the slew rate is 440-4400V/us.
6. A short-circuit protection method applied to the short-circuit protection circuit of any one of claims 1 to 5, the short-circuit protection method being executed during a controller boot-up phase of the control circuit, the short-circuit protection method comprising:
the control circuit outputs a standard waveform of a node and is coupled to the node;
the waveform of the extraction node;
and controlling the on-off of the protection switch according to the waveform amplitude of the recovered node, and switching on or off the connection between the node and the bus so as to perform short-circuit protection.
7. The short-circuit protection method of claim 6, wherein the control circuit outputs a standard waveform at a node and is coupled to the node, comprising:
the controller outputs the standard waveform of the node to a signal output circuit, the signal output circuit transmits the standard waveform of the node to a second secondary winding of the transformer, and the standard waveform of the node is coupled to the node through the second secondary winding and a primary winding of the transformer.
8. The short-circuit protection method of claim 6, wherein the waveform of the extraction node comprises:
the waveform of the node is coupled to a first secondary winding of the transformer through a primary winding of the transformer, and the signal acquisition circuit acquires the waveform of the node from the first secondary winding of the transformer and transmits the waveform to the controller.
9. An electronic device, comprising:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to perform the method of any one of claims 6-8.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101227077A (en) * 2007-12-30 2008-07-23 人民电器集团有限公司 Breaker for voltage transformer and operating method thereof
CN104833939A (en) * 2015-05-29 2015-08-12 广东电网有限责任公司佛山供电局 Voltage transient fault detector based on electric energy quality monitor
CN111007770A (en) * 2019-12-18 2020-04-14 中国兵器装备集团自动化研究所 Waveform generation and recovery system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101227077A (en) * 2007-12-30 2008-07-23 人民电器集团有限公司 Breaker for voltage transformer and operating method thereof
CN104833939A (en) * 2015-05-29 2015-08-12 广东电网有限责任公司佛山供电局 Voltage transient fault detector based on electric energy quality monitor
CN111007770A (en) * 2019-12-18 2020-04-14 中国兵器装备集团自动化研究所 Waveform generation and recovery system

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