CN112448268A - VCSEL chip with lens structure and preparation method thereof - Google Patents
VCSEL chip with lens structure and preparation method thereof Download PDFInfo
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- CN112448268A CN112448268A CN202011328645.XA CN202011328645A CN112448268A CN 112448268 A CN112448268 A CN 112448268A CN 202011328645 A CN202011328645 A CN 202011328645A CN 112448268 A CN112448268 A CN 112448268A
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- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 25
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- 229920001721 polyimide Polymers 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
- 238000009616 inductively coupled plasma Methods 0.000 claims description 19
- 238000011161 development Methods 0.000 claims description 7
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- 238000000576 coating method Methods 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
- H01S2304/04—MOCVD or MOVPE
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- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention discloses a VCSEL chip with a lens structure and a preparation method thereof, wherein the VCSEL chip comprises a GaAs substrate; the NDBR layer, the MQW layer, the oxide layer, the PDBR layer and the P contact layer are sequentially grown on the GaAs substrate; a P electrode disposed on the P contact layer of the light emitting hole region; an N electrode disposed on a surface of the GaAs substrate near the NDBR layer; a SIN passivation layer disposed on at least a portion of a surface of the VCSEL chip; a lens disposed on a surface of the SIN passivation layer of the light exit aperture region. The invention not only can effectively reduce the divergence angle of the VCSEL chip, but also can effectively protect the light-emitting cavity surface, thereby ensuring that the VCSEL chip has good appearance.
Description
Technical Field
The invention relates to the fields of photoelectrons, microelectronics and power device technology, in particular to a VCSEL chip with a lens structure and a preparation method thereof.
Background
A Vertical Cavity Surface Emitting Laser (VCSEL) is different from other Light sources such as an LED (Light Emitting Diode) and an LD (Laser Diode), has the advantages of small volume, circular output Light spot, single longitudinal mode output, small threshold current, easy integration of a large-area array, and the like, and is widely applied to the fields of optical communication, optical interconnection, optical storage, and the like. With the continuous development of science and technology, various VCSEL chips are widely applied to daily life, work and industry of people, and bring great convenience to the life of people.
Since the divergence angle of a vertical cavity surface emitting semiconductor laser (VCSEL) is mainly determined by the size of the epitaxial structure and the oxide aperture, the larger the oxide aperture, the smaller the divergence angle, but the larger the oxide aperture, the worse the LIV characteristics of the chip, and therefore, a technical scheme for reducing the divergence angle without changing the oxide aperture is urgently needed.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. To this end, an object of the present invention is to propose a VCSEL chip with a lens structure and a method for manufacturing the same. Through set up lens at the light-emitting cavity face (being light-emitting hole region), not only can effectively reduce the divergence angle of VCSEL chip, simultaneously because the lens after the solidification has the characteristics of preventing steam and wear-resisting and resistant mechanical shock, can also effectively protect the light-emitting cavity face to guarantee that the VCSEL chip has good outward appearance.
In one aspect of the invention, the invention provides a VCSEL chip structure with a lens structure. According to an embodiment of the present invention, the VCSEL chip structure having a lens structure includes:
a GaAs substrate;
the NDBR layer, the MQW layer, the oxide layer, the PDBR layer and the P contact layer are sequentially grown on the GaAs substrate;
the oxide layer comprises a first oxide layer and a second oxide layer, the first oxide layer corresponds to the light-emitting hole region, and the second oxide layer is arranged on two sides of the light-emitting hole region;
the P electrode is arranged on the P contact layer of the light-emitting hole area;
the N electrode is arranged on the surface, close to the NDBR layer, of the GaAs substrate;
a SIN passivation layer disposed on at least a portion of a surface of the VCSEL chip;
the lens is arranged on the surface of the SIN passivation layer of the light-emitting hole area, and the lens completely covers the light-emitting hole area.
According to the VCSEL chip structure with the lens structure, the lens is arranged on the light-emitting cavity surface (namely the light-emitting hole region), so that the divergence angle of the VCSEL chip can be effectively reduced, and meanwhile, the cured lens has the characteristics of water vapor resistance, wear resistance and mechanical impact resistance and can effectively protect the light-emitting cavity surface, so that the VCSEL chip is ensured to have good appearance.
In addition, the VCSEL chip structure with lens structure according to the above embodiment of the present invention may also have the following additional technical features:
in some embodiments of the present invention, the material of the lens is a photosensitive polyimide glue. Therefore, the photosensitive polyimide has good fluidity at high temperature, can form a uniform film on the light emergent cavity surface of the chip through a coating technology, and has better permeability, water vapor resistance, wear resistance and mechanical impact resistance after the photoresist is cured.
In some embodiments of the invention, the diameter of the circle on which the lens is located is 13-17 μm.
In some embodiments of the invention, the height of the top of the lens from the pcontact layer is 6.0-6.5 μm.
In some embodiments of the invention, the diameter of the light exit aperture is 7-10 μm.
In some embodiments of the invention, the NDBR layer has a thickness of 3.5 to 4.0 μm.
In some embodiments of the invention, the thickness of the MQW layer is from 180nm to 220 nm.
In some embodiments of the present invention, the oxide layer has a thickness of 80-120 nm.
In some embodiments of the invention, the thickness of the PDBR layer is 3.5-4.0 μm.
In some embodiments of the present invention, the P-contact layer has a thickness of 30-40 nm.
In some embodiments of the present invention, the thickness of the SIN passivation layer is 200-400 nm.
In some embodiments of the invention, the lens is prepared by the following method:
coating a photosensitive polyimide photoresist on the surface of the SIN passivation layer in the light emergent hole area through step exposure and development so as to form a circular step-shaped polyimide photoresist;
and carrying out oven curing on the circular step-shaped polyimide adhesive so as to form a circular lens.
In some embodiments of the present invention, a photosensitive polyimide photoresist is coated on the surface of the SIN passivation layer in the light-extraction hole region through 4-8 steps of exposure and development, so as to form a circular step-shaped polyimide photoresist.
In another aspect of the present invention, the present invention provides a method for preparing the VCSEL chip with the lens structure, including:
(1) sequentially growing an NDBR layer, an MQW layer, an oxide layer, a PDBR layer and a P contact layer on a GaAs substrate according to a layered structure;
(2) preparing a P electrode on the P contact layer in the light-emitting hole area by adopting a photoresist stripping method;
(3) etching the epitaxial layer to the bottom of the oxide layer by adopting an ICP (inductively coupled plasma) etching method so as to obtain a first oxide layer corresponding to the light-emitting hole area and second oxide layers on two sides of the light-emitting hole area;
(4) etching an epitaxial layer to the surface of the GaAs substrate close to the NDBR layer by adopting an ICP (inductively coupled plasma) etching method, and preparing an N electrode on the surface of the GaAs substrate close to the NDBR layer by utilizing a photoresist stripping method;
(5) preparing an SIN passivation layer on at least part of the surface of the VCSEL chip by adopting a PECVD method;
(6) and preparing a lens on the surface of the SIN passivation layer in the light-emitting hole area, and enabling the lens to completely cover the light-emitting hole area.
According to the method for preparing the VCSEL chip with the lens structure, disclosed by the embodiment of the invention, the lens is arranged on the light emergent cavity surface (namely the light emergent hole region), so that the divergence angle of the VCSEL chip can be effectively reduced, and meanwhile, the cured lens has the characteristics of water vapor resistance, wear resistance and mechanical impact resistance, and can also effectively protect the light emergent cavity surface, thereby ensuring that the VCSEL chip has good appearance.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a VCSEL chip according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a VCSEL chip epitaxial structure according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, four, five, six, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In one aspect of the invention, the invention provides a VCSEL chip structure with a lens structure. Referring to fig. 1 and 2, the VCSEL chip having a lens structure according to an embodiment of the present invention includes a GaAs substrate 1, an NDBR layer 2, an MQW layer 3, an oxide layer 4, a PDBR layer 5, a P contact layer 6, a P electrode 7, an N electrode 8, a SIN passivation layer 9, and a lens 10.
According to an embodiment of the present invention, referring to fig. 1 and 2, an NDBR layer 2, an MQW layer 3, an oxide layer 4, a PDBR layer 5, and a P-contact layer 6 are sequentially grown on a GaAs substrate 1 in a layered structure. The NDBR layer 2 serves to form a mirror having a thickness of 3.5 to 4.0 μm. The MQW layer 3 functions as a light emitting region and has a thickness of 180nm to 220 nm. The oxide layer 4 serves to limit current and light and has a thickness of 80-120 nm. The PDBR layer 5 serves to form a mirror having a thickness of 3.5-4.0. mu.m. The P contact layer 6 is used for forming a P-type ohmic contact and has a thickness of 30-40 nm. The GaAs substrate is a conductive substrate.
According to an embodiment of the present invention, referring to fig. 1, the oxide layer 4 includes a first oxide layer 41 and a second oxide layer 42, the first oxide layer 41 corresponds to the light exit hole region a, and the second oxide layer 42 is disposed on two sides of the light exit hole region. In the embodiment of the invention, the epitaxial layer is etched to the bottom of the oxide layer (etching through the oxide layer) by utilizing an ICP etching technology, two grooves are formed on two sides of the light-emitting hole area A, the oxide layer near the grooves is oxidized by a wet method by utilizing an oxidation furnace, and the other areas are not oxidized.
According to an embodiment of the present invention, referring to fig. 1, a P-electrode 7, the P-electrode 7 being disposed on the P-contact layer 6 of the light exit hole area a. The P electrode 7 is a ring structure, and the function of the P electrode is to form a current injection channel.
According to an embodiment of the present invention, referring to fig. 1, an N-electrode 8, where the N-electrode 8 is disposed on a surface of the GaAs substrate 1 adjacent to the NDBR layer 2. The function of the N-electrode 8 is to form a current output channel. In the embodiment of the invention, an epitaxial layer is etched to the GaAs substrate by utilizing an ICP etching technology (namely, the NDBR layer 2, the MQW layer 3, the oxidation layer 4, the PDBR layer 5 and the P contact layer 6 on the GaAs substrate are all etched away), and then an N electrode 8 is prepared on the exposed GaAs substrate by utilizing a photoresist stripping technology.
According to an embodiment of the invention, referring to fig. 1, a SIN passivation layer 9 is disposed on at least a portion of a surface of the VCSEL chip. The SIN passivation layer 9 serves to passivate the surface, with a thickness of 200-400 nm. And removing the SIN passivation layer on the P electrode and the N electrode by using an ICP (inductively coupled plasma) etching technology so as to leak the P electrode and the N electrode.
According to an embodiment of the present invention, referring to fig. 1, a lens 10, the lens 10 is disposed on the surface of the SIN passivation layer 9 of the light exit hole region a, and the lens completely covers the light exit hole region, then the lens 10 also necessarily completely covers the ring-shaped P electrode 7. Through set up lens at the light-emitting cavity face (being light-emitting hole region), not only can effectively reduce the divergence angle of VCSEL chip, simultaneously because the lens after the solidification has the characteristics of preventing steam and wear-resisting and resistant mechanical shock, can also effectively protect the light-emitting cavity face to guarantee that the VCSEL chip has good outward appearance.
According to a specific embodiment of the invention, the material of the lens is photosensitive polyimide glue, the photosensitive polyimide has good fluidity at high temperature, a uniform film can be formed on the light emergent cavity surface of the chip through a coating technology, and the photoresist has good permeability, water vapor resistance, wear resistance and mechanical impact resistance after being cured.
According to a further embodiment of the invention, the diameter of the circle on which the lenses are located is 13-17 μm. Therefore, the lens with the diameter range can better reduce the divergence angle of the VCSEL chip and protect the light emergent cavity surface. The inventors found that if the diameter is less than 13 μm, the facet is not well protected; if it is higher than 17 μm, the appearance that the edge of the lens is too close to the mesa is difficult to control.
According to a further embodiment of the invention, the height of the top of the lens from the pcontact layer is 6.0-6.5 μm. Therefore, the lens in the height range can better reduce the divergence angle of the VCSEL chip and protect the light emergent cavity surface. The inventors found that, if it is less than 6 μm, the mechanical impact resistance is lowered; if it is higher than 6.5 μm, stress increases while affecting light extraction efficiency.
According to yet another embodiment of the present invention, the lens is prepared as follows:
firstly, coating a photosensitive polyimide photoresist on the surface of the SIN passivation layer in the light-emitting hole area through step exposure and development so as to form the circular step-shaped polyimide photoresist.
And then, carrying out oven curing on the polyimide adhesive with the circular step shape so as to form a circular lens.
According to another embodiment of the invention, through 4-8 steps of exposure, a photosensitive polyimide photoresist can be coated on the surface of the SIN passivation layer in the light-extraction hole area through development and precise control of the developed appearance, so as to form the circular step-shaped polyimide photoresist.
According to the VCSEL chip structure with the lens structure, the lens is arranged on the light-emitting cavity surface (namely the light-emitting hole region), so that the divergence angle of the VCSEL chip can be effectively reduced, and meanwhile, the cured lens has the characteristics of water vapor resistance, wear resistance and mechanical impact resistance and can effectively protect the light-emitting cavity surface, so that the VCSEL chip is ensured to have good appearance.
In another aspect of the present invention, the present invention provides a method for preparing the VCSEL chip with the lens structure, including:
s1: an NDBR layer, an MQW layer, an oxide layer, a PDBR layer and a P contact layer are sequentially grown on a GaAs substrate according to a layered structure, as shown in figure 2. The above layers are grown by MOCVD epitaxial growth.
S2: and preparing a P electrode on the P contact layer in the light-emitting hole region by adopting a photoresist stripping method.
S3: and etching the epitaxial layer to the bottom of the oxide layer by adopting an ICP (inductively coupled plasma) etching method so as to obtain a first oxide layer corresponding to the light-emitting hole region and second oxide layers on two sides of the light-emitting hole region. In the embodiment of the invention, an ICP etching technology is utilized to etch the epitaxial layer to the bottom of the oxide layer (to etch through the oxide layer), two grooves are formed on two sides of the light-emitting hole area A, and then an oxidation furnace is utilized to carry out wet oxidation on the oxide layer near the two sides of the groove; while the other regions are not oxidized. The oxidized oxide layer is insulated and has no light transmittance, while the oxidized oxide layer without oxidation has light transmittance. In the light exit hole region a, only a portion near the groove is oxidized, and most other regions are not oxidized and have light transmittance.
S4: and etching an epitaxial layer to the surface of the GaAs substrate close to the NDBR layer by adopting an ICP (inductively coupled plasma) etching method, and preparing an N electrode on the surface of the GaAs substrate close to the NDBR layer by utilizing a photoresist stripping method. In the embodiment of the invention, an epitaxial layer is etched to the GaAs substrate by utilizing an ICP etching technology (namely, the NDBR layer 2, the MQW layer 3, the oxidation layer 4, the PDBR layer 5 and the P contact layer 6 on the GaAs substrate are all etched away), and then an N electrode 8 is prepared on the exposed GaAs substrate by utilizing a photoresist stripping technology.
S5: and preparing a SIN passivation layer on at least part of the surface of the VCSEL chip by adopting a PECVD method. And etching the SIN on the P electrode and the N electrode by using an ICP etching technology to leak the P electrode and the N electrode respectively.
S6: and preparing a lens on the surface of the SIN passivation layer in the light-emitting hole area, and enabling the lens to completely cover the light-emitting hole area. In the embodiment of the invention, the surface of the photosensitive polyimide photoresist is coated, the redundant photosensitive polyimide photoresist on the surface is removed by utilizing the multi-time photoetching technology, only the photosensitive polyimide glue on the light emergent cavity surface is reserved, and the photosensitive polyimide glue reserved on the cavity surface forms a plurality of steps. And then, an oxygen-free oven is used for curing, and the photosensitive polyimide on the cavity surface is cured into the lens by utilizing the fluidity of the photosensitive polyimide in the step heating process. The total thickness of the photosensitive polyimide photoresist (namely the height from the top of the photosensitive polyimide photoresist to the P contact layer) is 9.0-9.5 mu m, and a lens with the thickness of 6.0-6.5 mu m (namely the height from the top of the lens to the P contact layer) is formed after some solvent in the cured photoresist is volatilized.
According to the method for preparing the VCSEL chip with the lens structure, disclosed by the embodiment of the invention, the lens is arranged on the light emergent cavity surface (namely the light emergent hole region), so that the divergence angle of the VCSEL chip can be effectively reduced, and meanwhile, the cured lens has the characteristics of water vapor resistance, wear resistance and mechanical impact resistance, and can also effectively protect the light emergent cavity surface, thereby ensuring that the VCSEL chip has good appearance.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A VCSEL chip having a lens structure, comprising:
a GaAs substrate;
the NDBR layer, the MQW layer, the oxide layer, the PDBR layer and the P contact layer are sequentially grown on the GaAs substrate;
the oxide layer comprises a first oxide layer and a second oxide layer, the first oxide layer corresponds to the light-emitting hole region, and the second oxide layer is arranged on two sides of the light-emitting hole region;
the P electrode is arranged on the P contact layer of the light-emitting hole area;
the N electrode is arranged on the surface, close to the NDBR layer, of the GaAs substrate;
a SIN passivation layer disposed on at least a portion of a surface of the VCSEL chip;
the lens is arranged on the surface of the SIN passivation layer of the light-emitting hole area, and the lens completely covers the light-emitting hole area.
2. A VCSEL chip with lens structure according to claim 1, wherein the material of said lens is photosensitive polyimide glue.
3. A VCSEL chip with lens structure according to claim 1, wherein the diameter of the circle on which the lens is located is 13-17 μm.
4. A VCSEL chip with lens structure according to claim 1, wherein the height of the top of the lens from the pcontact layer is 6.0-6.5 μm.
5. A VCSEL chip with lens structure according to claim 1, wherein the diameter of the light exit aperture is 7-10 μm.
6. A VCSEL chip with lens structure according to claim 1, wherein the thickness of the NDBR layer is 3.5-4.0 μm;
optionally, the thickness of the MQW layer is 180nm to 220 nm;
optionally, the oxide layer has a thickness of 80-120 nm.
7. A VCSEL chip with lens structure according to claim 1, wherein said PDBR layer has a thickness of 3.5-4.0 μm;
optionally, the thickness of the P-contact layer is 30-40 nm;
optionally, the thickness of the SIN passivation layer is 200-400 nm.
8. A VCSEL chip with lens structure according to claim 1, wherein said lens is prepared by the following steps:
coating a photosensitive polyimide photoresist on the surface of the SIN passivation layer in the light emergent hole area through step exposure and development so as to form a circular step-shaped polyimide photoresist;
and carrying out oven curing on the circular step-shaped polyimide adhesive so as to form a circular lens.
9. A VCSEL chip with a lens structure as claimed in claim 8, wherein a photosensitive polyimide photoresist is coated on the surface of the SIN passivation layer in the light exit hole region by 4-8 steps of exposure and development to form a circular step-like polyimide photoresist.
10. A method of manufacturing a VCSEL chip with a lens structure of any of claims 1-9, comprising:
(1) sequentially growing an NDBR layer, an MQW layer, an oxide layer, a PDBR layer and a P contact layer on a GaAs substrate according to a layered structure;
(2) preparing a P electrode on the P contact layer in the light-emitting hole area by adopting a photoresist stripping method;
(3) etching the epitaxial layer to the bottom of the oxide layer by adopting an ICP (inductively coupled plasma) etching method so as to obtain a first oxide layer corresponding to the light-emitting hole area and second oxide layers on two sides of the light-emitting hole area;
(4) etching an epitaxial layer to the surface of the GaAs substrate close to the NDBR layer by adopting an ICP (inductively coupled plasma) etching method, and preparing an N electrode on the surface of the GaAs substrate close to the NDBR layer by utilizing a photoresist stripping method;
(5) preparing an SIN passivation layer on at least part of the surface of the VCSEL chip by adopting a PECVD method;
(6) and preparing a lens on the surface of the SIN passivation layer in the light-emitting hole area, and enabling the lens to completely cover the light-emitting hole area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011328645.XA CN112448268A (en) | 2020-11-24 | 2020-11-24 | VCSEL chip with lens structure and preparation method thereof |
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| CN202011328645.XA CN112448268A (en) | 2020-11-24 | 2020-11-24 | VCSEL chip with lens structure and preparation method thereof |
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| CN112448268A true CN112448268A (en) | 2021-03-05 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097864A (en) * | 2021-06-10 | 2021-07-09 | 常州纵慧芯光半导体科技有限公司 | Vertical-cavity surface-emitting laser array and preparation method thereof |
| CN113314952A (en) * | 2021-07-30 | 2021-08-27 | 华芯半导体研究院(北京)有限公司 | VCSEL chip with slope PIA structure and preparation method thereof |
| CN113394656A (en) * | 2021-04-27 | 2021-09-14 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL |
| CN113690730A (en) * | 2021-07-12 | 2021-11-23 | 华芯半导体研究院(北京)有限公司 | Vertical cavity surface emitting laser |
| CN113948963A (en) * | 2021-09-30 | 2022-01-18 | 武汉光迅科技股份有限公司 | Laser chip and preparation method thereof |
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2020
- 2020-11-24 CN CN202011328645.XA patent/CN112448268A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113394656A (en) * | 2021-04-27 | 2021-09-14 | 威科赛乐微电子股份有限公司 | Preparation method of VCSEL |
| CN113097864A (en) * | 2021-06-10 | 2021-07-09 | 常州纵慧芯光半导体科技有限公司 | Vertical-cavity surface-emitting laser array and preparation method thereof |
| CN113690730A (en) * | 2021-07-12 | 2021-11-23 | 华芯半导体研究院(北京)有限公司 | Vertical cavity surface emitting laser |
| CN113314952A (en) * | 2021-07-30 | 2021-08-27 | 华芯半导体研究院(北京)有限公司 | VCSEL chip with slope PIA structure and preparation method thereof |
| CN113314952B (en) * | 2021-07-30 | 2021-11-09 | 华芯半导体研究院(北京)有限公司 | VCSEL chip with slope PIA structure and preparation method thereof |
| CN113948963A (en) * | 2021-09-30 | 2022-01-18 | 武汉光迅科技股份有限公司 | Laser chip and preparation method thereof |
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