CN112447826B - Planar IGBT structure - Google Patents
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
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Abstract
The invention discloses a planar IGBT structure, which comprises a chip main body, wherein a plurality of P wells distributed in parallel are arranged on the chip main body, the step pitch among the P wells is set from the center of the chip main body to the edge from small to large, and the P wells surround the center of the chip main body. The arrangement makes the on-state voltage drop of the central area of the chip slightly higher and the on-state voltage drop of the peripheral area lower, effectively improves the condition of uneven current distribution caused by uneven temperature distribution on the chip and the heat dissipation performance of the chip, and the conductivity of the chip is also improved by the conduction of the channel along the <100> crystal direction of the (100) crystal face. The design of the invention ensures that the planar IGBT has excellent heat dissipation consistency, prevents the chip from being burnt out and damaging the whole chip due to uneven temperature distribution and overheating of a certain point, and greatly improves the reliability of the chip.
Description
Technical Field
The invention relates to the technical field of power semiconductor device structures in the technical field of semiconductors, in particular to a planar IGBT structure.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a voltage control type device, has both MOSFET and Bipolar power Transistor structures, and has the advantages of simple driving, high switching frequency, reduced on-state voltage, high current density, high voltage resistance, and the like.
The planar IGBT is a classic IGBT structure, and plays an important role in various fields up to now. For a planar IGBT chip, if its P wells are uniformly distributed, after conduction, the chip temperature distribution is "high at the center temperature and low at the edge temperature", which is because the heat dissipation in the center region of the chip is slower than that in the peripheral region due to its overall structure. On one hand, the heat dissipation surface of the central area is the smallest, the heat dissipation direction is mainly conducted downwards to the base, and the heat dissipation surface of the peripheral area can be larger in a mode of dissipating heat to the periphery. On the other hand, during the on-state operation of the chip, the heat emitted from the peripheral region is conducted to the central region and coupled with the heat emitted from the central region, thereby further increasing the temperature of the central region. When the chip works for a long time, the temperature distribution of the whole chip is high at the center and low at the periphery, the current distribution of the whole chip is also in an uneven state, under the state, various performances of the chip can be influenced, even the chip is burnt out from a certain serious heating point of the chip due to uneven heat dissipation, and the whole chip is damaged.
Thus, the prior art designs have drawbacks and need improvement.
Disclosure of Invention
In order to solve the technical problems, the invention provides a planar IGBT structure, wherein the step pitch between P wells is gradually increased from the center of a chip to the periphery, the arrangement enables the on-state voltage drop of the central area of the chip to be slightly higher, the on-state voltage drop of the peripheral area to be reduced, and the trends of easy heating at the center and uneven current can be counteracted to a certain extent.
The technical scheme of the invention is as follows: the invention provides a planar IGBT structure, which comprises a chip main body, wherein a plurality of P wells distributed in parallel are arranged on the chip main body, the step pitch among the P wells is set from the center of the chip main body to the edge from small to large, and the P wells surround the center of the chip main body.
Further, the active region of the chip body is disposed on the (100) crystal plane, the channel is conductive along the <100> crystal direction of the (100) crystal plane, and the P-well is disposed perpendicular to the conductive direction of the channel.
Further, the P-well is a ring-shaped structure surrounded by the bars.
Further, the P-well is in a shape of a circular ring, a square ring, a rectangular ring, a diamond ring, a regular polygonal ring or an irregular ring.
Further, the chip main body further includes: and the grid bonding pad is arranged at the corner, the edge or the center of the chip main body, and is communicated with the periphery of the chip main body or the periphery and the inside of the chip main body through the grid bus bar.
Further, when the grid pad is communicated with the periphery of the chip main body through the grid bus bar, the grid bus bar is a non-grid-finger bus bar which is arranged around the periphery of the active region and does not extend out of the finger-shaped bus bar towards the inside of the chip main body.
Further, when the grid pad is communicated with the periphery and the interior of the chip main body through the grid bus bar, the grid bus bar is an oblique diagonal grid finger bus bar, and the oblique diagonal grid finger bus bar extends out of the finger-shaped bus bar towards the interior of the chip main body except the oblique diagonal grid finger bus bar which is arranged around the periphery of the active area.
By adopting the scheme, the invention provides the plane type IGBT structure, the step pitch among the plurality of P wells distributed in parallel is set, so that the step pitch among the plurality of P wells is increased from the center to the edge of the IGBT chip main body, the distribution of the plurality of P wells on the chip is changed from the center to the edge of the IGBT chip main body from dense to sparse, the on-state voltage drop of the central area of the chip is slightly higher, the on-state voltage of the peripheral area is reduced, the tendency that the center is easy to heat and the current is uneven can be counteracted to a certain degree, the current distribution is effectively prevented from being uneven, the heat dissipation is not even, the chip is burnt from a certain serious heating point, and the safety performance of the chip is greatly improved.
Drawings
Fig. 1 is a graph of the on-state voltage drop of the planar IGBT structure of the present invention as a function of the pitch between P wells.
Fig. 2 is a schematic crystal plane diagram of a wafer silicon wafer on which the planar IGBT structure of the present invention is located.
Fig. 3 is a schematic crystal orientation diagram of a wafer silicon wafer on which the planar IGBT structure of the present invention is located.
Fig. 4 is a schematic diagram of the position of the P-well on the crystal plane (100) of the planar IGBT structure according to the present invention.
Fig. 5A is a schematic structural diagram of a planar IGBT with a circular ring P-well and a non-gate finger bus structure according to embodiment 1 of the present invention.
Fig. 5B is a schematic structural diagram of a planar IGBT with a circular ring P-well and a non-gate finger bus structure according to embodiment 1 of the present invention.
Fig. 5C is a schematic structural diagram of a planar IGBT with a circular ring P-well and a non-gate finger bus structure according to embodiment 1 of the present invention.
Fig. 5D is a schematic diagram of a planar IGBT structure with an inclined diagonal gate finger bus structure of a circular ring P well according to embodiment 1 of the present invention.
Fig. 5E is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate-finger bus structure of a circular ring P-well according to embodiment 1 of the present invention.
Fig. 5F is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate-finger bus structure of a circular ring P-well according to embodiment 1 of the present invention.
Fig. 6A is a schematic structural diagram of a planar IGBT with a rhombus-shaped ring P-well and a non-gate finger bus structure according to embodiment 2 of the present invention.
Fig. 6B is a schematic view of a planar IGBT structure with a non-gate finger bus structure of a diamond ring P-well according to embodiment 2 of the present invention.
Fig. 6C is a schematic structural diagram of a planar IGBT with a rhombus-shaped ring P-well and a non-gate finger bus structure according to embodiment 2 of the present invention.
Fig. 6D is a schematic view of a planar IGBT structure with an inclined diagonal gate finger bus structure of a diamond ring P-well according to embodiment 2 of the present invention.
Fig. 6E is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a diamond ring P-well according to embodiment 2 of the present invention.
Fig. 6F is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a diamond ring P-well according to embodiment 2 of the present invention.
Fig. 7A is a schematic view of a planar IGBT structure of an octagon ring P-well non-gate finger bus structure according to embodiment 3 of the present invention.
Fig. 7B is a schematic view of a planar IGBT structure with an octagonal ring P-well and without a gate finger bus structure according to embodiment 3 of the present invention.
Fig. 7C is a schematic structural diagram of a planar IGBT with a quad-ring P-well and a non-gate finger bus structure according to embodiment 3 of the present invention.
Fig. 7D is a schematic view of a planar IGBT structure with an octagonal ring P-well diagonal gate finger bus structure according to embodiment 3 of the present invention.
Fig. 7E is a schematic diagram of a planar IGBT structure combined with an octagonal ring P-well diagonal gate finger bus structure according to embodiment 3 of the present invention.
Fig. 7F is a schematic view of a planar IGBT structure combined with an octagonal ring P-well diagonal gate finger bus structure according to embodiment 3 of the present invention.
Fig. 8A is a schematic structural diagram of a planar IGBT with a quad-ring P-well and a non-gate finger bus structure according to embodiment 4 of the present invention.
Fig. 8B is a schematic structural diagram of a planar IGBT with a quad-ring P-well and a non-gate finger bus structure according to embodiment 4 of the present invention.
Fig. 8C is a schematic structural diagram of a planar IGBT with a quad-ring P-well and a non-gate finger bus structure according to embodiment 4 of the present invention.
Fig. 8D is a schematic view of a planar IGBT structure with an oblique diagonal gate finger bus structure of a square ring P-well according to embodiment 4 of the present invention.
Fig. 8E is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a square ring P-well according to embodiment 4 of the present invention.
Fig. 8F is a schematic view of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a square ring P-well according to embodiment 4 of the present invention.
Fig. 9A is a schematic structural view of a planar IGBT with a circular structure and a ring P-well having a straight middle section and having a non-gate finger bus structure according to embodiment 5 of the present invention.
Fig. 9B is a schematic structural view of a planar IGBT with a circular non-gate-finger bus structure, in which the middle section of the planar IGBT has a straight-sided ring P-well according to embodiment 5 of the present invention.
Fig. 9C is a schematic structural view of a planar IGBT with a circular non-gate-finger bus structure, in which the middle section of the planar IGBT has a straight-sided ring P-well according to embodiment 5 of the present invention.
Fig. 9D is a schematic structural diagram of a planar IGBT with a circular shape and a diagonal gate-finger bus structure having a straight-sided ring P-well in the middle section according to embodiment 5 of the present invention.
Fig. 9E is a schematic view of a planar IGBT structure combined with a circular diagonal gate-finger bus structure with a straight-sided ring P-well in the middle section according to embodiment 5 of the present invention.
Fig. 9F is a schematic view of a planar IGBT structure combined with a circular diagonal gate-finger bus structure having a straight-sided ring P-well in the middle section according to embodiment 5 of the present invention.
Fig. 10A is a schematic view of a planar IGBT structure with a ring having a P-well with a square-shaped inner side and a square-shaped outer side according to embodiment 6 of the present invention.
Fig. 10B is a schematic view of a planar IGBT structure with a ring having a P-well with a square fillet on the inner side and a square outer side, and having a non-gate finger bus structure according to embodiment 6 of the present invention.
Fig. 10C is a schematic view of a planar IGBT structure of a non-gate finger bus structure with a square inner side and a square outer side according to embodiment 6 of the present invention.
Fig. 10D is a schematic view of a planar IGBT structure with a diagonal gate-finger bus structure having a square fillet on the inner side and a square on the outer side according to embodiment 6 of the present invention.
Fig. 10E is a schematic view of a planar IGBT structure combining a diagonal gate-finger bus structure with a square fillet inside and a square outside according to embodiment 6 of the present invention.
Fig. 10F is a schematic diagram of a planar IGBT structure combining a diagonal gate finger bus structure with a square-shaped rounded inside and a square-shaped P-well outside in embodiment 6 of the present invention.
Fig. 11A is a schematic structural view of a planar IGBT with a square-shaped circular-angle-ring P-well and without a gate finger bus structure according to embodiment 7 of the present invention.
Fig. 11B is a schematic structural diagram of a planar IGBT with a square-shaped circular-angle-ring P-well structure and without a gate finger bus bar structure according to embodiment 7 of the present invention.
Fig. 11C is a schematic view of a planar IGBT structure of a square-shaped circular-angle-ring P-well without gate finger bus structure according to embodiment 7 of the present invention.
Fig. 11D is a schematic diagram of a planar IGBT structure with an inclined diagonal gate finger bus structure of a square-shaped circular-corner ring P-well according to embodiment 7 of the present invention.
Fig. 11E is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a square circular-angle ring P-well according to embodiment 7 of the present invention.
Fig. 11F is a schematic diagram of a planar IGBT structure combined with an inclined diagonal gate finger bus structure of a square circular ring P-well according to embodiment 7 of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Example 1
As shown in fig. 5A to 5F, which are schematic diagrams of the planar IGBT structure of this embodiment, it can be seen that a plurality of P wells 10 distributed in parallel are disposed on the chip body, the P wells 10 are circular rings, and the step distance between the plurality of P wells 10 is set from the center of the chip body to the edge, and the step distance is gradually increased from the center to the edge. The value of the inter-P-well step distance can be obtained by the following method: and determining an optimal value A according to the voltage grade of the chip, wherein if the step distance between two P wells closest to the center of the IGBT chip is B, the step distance between two P wells closer to the edge of the IGBT structure is closer to the optimal value A, so that the arrangement of the step distances among the P wells distributed in parallel is realized. As shown in fig. 1, it is a graph of the on-state voltage drop of the planar IGBT structure of this embodiment with the pitch between P wells, where the X-axis is the pitch (unit um) and the Y-axis is the on-state voltage drop (unit V). To the left of an optimum value a, the on-state pressure drop decreases with increasing step size. Therefore, the step pitch of the P-well 10 is set to be left of the optimal value a, the center is set to be the minimum value B of the step pitch, and the step pitch from the center of the chip body to the periphery is set to be closer to the optimal value a. In the left half curve of the optimal value A to the left, the excessive carriers in the chip will be attenuated when meeting the P trap, and when the P trap step pitch becomes larger, the area of attenuation in the unit chip area will be reduced, so that the overall conduction modulation is enhanced, and the on-state voltage drop is reduced. Through the dense P trap setting around, at the center for the logical attitude pressure drop at chip main part center is slightly higher, and the logical attitude pressure drop on every side reduces, offsets "the center easily generates heat" and the inhomogeneous trend of electric current to a certain extent, can alleviate the too high condition of chip main part central point position temperature greatly, improves the degree of safety of chip main part.
As shown in fig. 2, which is a schematic view of a crystal plane on a wafer silicon chip where a chip main body is located, it can be seen that an upper surface of the wafer silicon chip is a (100) crystal plane. Wafers produced according to international standards typically have a flat edge or notch (notch) that is aligned during subsequent photolithography processes. Under the condition of no special requirement, the crystal plane where the flat edge or the notch 200 is located is a (110) crystal plane, and the (110) crystal plane is vertical to the (100) crystal plane. Fig. 3 shows a schematic crystal orientation diagram, the directions indicated by four arrows are <100> crystal orientation, i.e. the conduction direction of the channel, and the plane where the oblique lines are located is the (110) crystal plane in fig. 3. In the interior of the chip, the mobility of channel electrons is the largest in the (100) plane, and among the multiple crystal orientations of the (100) plane, the mobility of electrons in the <100> crystal orientation is the largest, which is most beneficial for the conduction of channel electrons, so in this embodiment, the active region of the chip is disposed on the (100) plane, and the channel is made to conduct along the <100> crystal orientation of the (100) plane, and the conduction direction of the channel is perpendicular to the P-well, i.e., forms an angle of 45 degrees with the flat side. The arrangement also reduces the problem of uneven current distribution to a certain extent, and lightens the heating condition of the central position of the chip main body. To help understanding, referring to fig. 4, fig. 4 is a schematic diagram of the conduction directions of the P-well 10 and the channel on a wafer, 200 is a flat edge of the wafer, and the conduction direction of the channel is perpendicular to the P-well, which schematically shows the positions of the P-well 10 and the <100> crystal orientation.
The cell of the invention is a strip-shaped cell, so the P trap is also strip-shaped, and then the strip-shaped structure forms a ring-shaped structure, and the P trap in the embodiment is designed in a ring shape. The chip main body further includes: and the gate pad 20 is arranged on the active region, the gate pad 20 is communicated with the periphery and the interior of the chip main body through a gate bus bar 30, and the gate bus bar 30 can be a non-gate finger bus bar structure or an oblique diagonal gate finger bus bar structure or a combination of the two structures. The IGBT is used for realizing the on-off of a device by applying a gate driving signal externally, the external gate driving signal is connected with an outer terminal through a compression welding wire or a compression connection thimble structure, therefore, an area without an effective cellular is designed and is placed at one corner, the edge or the center of an active area of a chip, and the area is connected with a square metal gate electrode which is arranged above the active area of the chip through a contact hole, and the square metal gate electrode is a gate bonding pad. In the embodiment of the present invention, a finger-free bus bar structure may be adopted, and the finger-free bus bar is a design in which only one circle of the finger-shaped bus bar is designed to surround the periphery of the active region, and does not protrude toward the inside of the chip, and an oblique diagonal bus bar structure or other forms may also be adopted.
As shown in fig. 5A-5C, the planar IGBT structure is a planar IGBT structure with a non-gate finger bus structure, which is a circular ring P-well, and the distance between two adjacent P-wells can be guaranteed to be equal everywhere. The difference between the three figures is that the gate pads are respectively arranged on the corners of the chip main body, the middle position of one side and the central position of the chip main body, and the gate bus bars are arranged around the periphery of the active region.
As shown in fig. 5D-5F, the planar IGBT structure is a diagonal gate finger bus structure with a circular ring P well, and the difference is that the gate pads are respectively disposed on one corner, the middle of one side, and the center of the chip body, and the gate bus fingers are diagonally disposed on the chip body.
Example 2
The difference between this embodiment and embodiment 1 is that the P-well is a diamond-shaped ring, and as shown in fig. 6A to 6C, the planar IGBT structure is a schematic diagram of a non-gate-finger bus structure with diamond-shaped ring P-wells, and the difference is that the gate pads are respectively disposed at a corner, a middle of one side, and a center of the chip body, and the gate bus is disposed around the periphery of the active region.
As shown in fig. 6D-6F, the difference between the planar IGBT structure and the planar IGBT structure is that the gate pads are respectively disposed at the corners, the middle of one side, and the center of the chip body, and the gate fingers of the gate bus bar are diagonally disposed on the chip body.
Example 3
The difference between this embodiment and embodiment 1 is that the P-well is an octagonal ring, and the ring structure is octagonal, which ensures that the channel is conductive along the <100> direction on four of the sides of the octagon. As shown in fig. 7A-7C, the planar IGBT structure is a planar IGBT structure with a non-gate finger bus structure, which is an octagonal ring P-well, and is different in that gate pads are respectively disposed on one corner of a chip body, in the middle of one side, and in the center of the chip body, and a gate bus is disposed around the periphery of an active region.
As shown in fig. 7D-7F, the planar IGBT structure is a diagonal gate finger bus structure with an octagonal ring P-well, and the difference is that the gate pads are respectively disposed on one corner of the chip body, the middle of one side, and the center of the chip body, and the gate bus fingers are diagonally disposed on the chip body.
Example 4
The difference between this embodiment and embodiment 1 is that the P-well is a square ring, and the ring structure is square, which can ensure the conduction along the <100> direction at the channel. As shown in fig. 8A-8C, the planar IGBT structure is a planar IGBT structure with a non-gate finger bus structure, which is a square ring P-well, and is different in that gate pads are respectively disposed at a corner, a middle of one side, and a center of the chip body, and the gate bus is disposed around the periphery of the active region.
As shown in fig. 8D-8F, the planar IGBT structure is a diagonal gate finger bus structure with square P-wells, and the difference is that the gate pads are respectively disposed at the middle position of one corner and one side of the chip body and the center position of the chip body, and the gate bus fingers are diagonally disposed on the chip body.
Example 5
The difference between this embodiment and embodiment 1 is that the P-well is a ring shape with a generally circular shape and a straight edge in the middle section, which ensures that the distance between two adjacent rings is equal everywhere, and the channel is conductive along the <100> direction in the straight edge portion of the ring. As shown in fig. 9A-9C, the difference between the planar IGBT structure and the planar IGBT structure is that the gate pad is respectively disposed on one corner of the chip body, in the middle of one side, and in the center of the chip body, and the gate bus bar is disposed around the periphery of the active region.
As shown in fig. 9D-9F, the planar IGBT structure is a diagonal gate finger bus structure, which is circular and has a ring P well with a straight edge in the middle, and the difference is that the gate pad is respectively disposed on one corner, the middle of one side, and the center of the chip body, and the gate bus finger is diagonally disposed on the chip body.
Example 6
The difference between this embodiment and embodiment 1 is that the P-well is a ring with a square inner side and a square outer side, which can ensure that the distance between two adjacent rings is equal everywhere, and most of the channel can conduct along the <100> direction. As shown in fig. 10A-10C, all of the planar IGBT structure diagrams are a finger-free IGBT structure having a ring P-well with a square fillet inside and a square outside, and the difference is that the gate pads are respectively disposed on one corner, the middle of one side, and the center of the chip body, and the gate bus bars are disposed around the periphery of the active region.
As shown in fig. 10D-10F, all of the planar IGBT structures are planar IGBT structures having diagonal gate finger bus bar structures with a square fillet inside and a square ring P-well outside, and the differences are that gate pads are respectively disposed at a corner, a middle of one side, and a center of the chip body, and gate bus bar gate fingers are diagonally disposed on the chip body.
Example 7
This embodiment is different from embodiment 1 in that the P-well is a square circular ring. This embodiment is an improvement of embodiment 6 and a modification of embodiment 5, and is a preferable alternative to the embodiment 5 and embodiment 6. The ring formed by the P-well stripes is a square fillet, which is equivalent to that in embodiment 6, the outer side of the ring formed by the P-well stripes is changed to a fillet, which can ensure that the ring formed by the P-well stripes is uniform, and compared with embodiment 5, more part of the channel in this embodiment can conduct along the <100> direction. As shown in fig. 11A-11C, the planar IGBT structure is a non-gate finger bus structure, and all of them are square-corner ring P-wells, and the difference is that the gate pad is respectively disposed on one corner, the middle of one side and the center of the chip body, and the gate bus is disposed around the periphery of the active region.
As shown in fig. 11D-11F, the planar IGBT structure is a diagonal gate finger bus structure with a square P-well, and the difference is that the gate pads are respectively disposed on one corner and the middle of one side of the chip body, and the center of the chip body, and the gate bus fingers are diagonally disposed on the chip body.
It should be noted that, in the above embodiments, the wafer silicon wafer default in the international standard is taken as an example, and when a specially customized silicon wafer is used, the specific pattern may be changed accordingly according to the situation. Features of embodiments of the invention may be combined with each other without conflict. It will be appreciated by persons skilled in the art that the foregoing description is only a selection of exemplary embodiments and is not intended to limit the invention.
The planar IGBT structure of the invention enables the step pitch among the P wells distributed in parallel to be increased from the center to the edge of the chip body, so that the distribution of the P wells on the chip is changed from the center to the edge from dense to sparse, the arrangement enables the on-state voltage drop of the central area of the chip to be slightly higher and the on-state voltage of the peripheral area to be reduced, thereby effectively improving the heat radiation performance of the chip and the condition of uneven current distribution caused by uneven temperature distribution on the chip, and the conductivity of the chip is also improved by the conduction of the channel along the <100> crystal direction of the (100) crystal face. The design of the invention ensures that the planar IGBT has excellent heat dissipation consistency, prevents the chip from being burnt out and damaging the whole chip due to uneven temperature distribution and overheating of a certain point, and greatly improves the reliability of the chip.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A planar IGBT structure is characterized by comprising a chip main body, wherein a plurality of P wells distributed in parallel are arranged on the chip main body, the P wells are in an annular structure formed by a strip body in a surrounding mode, the step pitch among the P wells is set from the center of the chip main body to the edge from small to large, and the P wells surround the center of the chip main body, so that the current distribution is effectively prevented from being uneven; the value of the P-well inter-step distance adopts the following method: determining an optimal value A according to the voltage grade of the chip main body, wherein the step distance between two P wells closest to the center of the chip main body is B, and the step distance between the two P wells closer to the edge of the chip main body is closer to the optimal value A, so that the step distances among the P wells distributed in parallel are set; on the left side of the optimal value A, the on-state pressure drop is reduced along with the increase of the step pitch;
the active region of the chip main body is arranged on the (100) crystal plane, the channel conducts electricity along the <100> crystal direction of the (100) crystal plane, and the P well is arranged perpendicular to the conduction direction of the channel.
2. The planar IGBT structure of claim 1, wherein the P-well is a strip of a circular ring, a square ring, a rectangular ring, a diamond ring, a regular polygonal ring, or an irregular ring.
3. The planar IGBT structure of claim 2, wherein the chip body further comprises: and the grid bonding pad is arranged at the corner, the edge or the center of the chip main body, and is communicated with the periphery of the chip main body or the periphery and the inside of the chip main body through a grid bus bar.
4. The planar IGBT structure of claim 3, wherein the gate pads are connected to the periphery of the chip body by gate bus bars, and the gate bus bars are finger-less bus bars that are disposed around the periphery of the active region without protruding finger-shaped bus bars toward the inside of the chip body.
5. The planar IGBT structure of claim 3, wherein the gate pads are connected to the periphery and the inside of the chip body via gate bus bars, and the gate bus bars are diagonal gate finger bus bars that extend from the finger bus bars toward the inside of the chip body in addition to being disposed around the periphery of the active region.
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| WO2020208761A1 (en) * | 2019-04-11 | 2020-10-15 | 三菱電機株式会社 | Semiconductor device and power conversion device |
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| GB0122120D0 (en) * | 2001-09-13 | 2001-10-31 | Koninkl Philips Electronics Nv | Edge termination in MOS transistors |
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| US9184277B2 (en) * | 2012-10-31 | 2015-11-10 | Infineon Technologies Austria Ag | Super junction semiconductor device comprising a cell area and an edge area |
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