CN112447136A

CN112447136A - Scan driver and display device

Info

Publication number: CN112447136A
Application number: CN202010893556.3A
Authority: CN
Inventors: 金玄俊
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2019-09-04
Filing date: 2020-08-31
Publication date: 2021-03-05
Also published as: EP3789994B1; US11222596B2; JP2021039330A; US20210065632A1; US11694627B2; EP3789994A1; KR20210028774A; US20220130337A1

Abstract

A scan driver and a display device are disclosed. The scan driver includes stages, each of which receives first and second clock signals having a first low level as an active level and a third clock signal having a high level as an active level. Each of the stages includes: a logic circuit changing a voltage of the first node to a first low level based on the input signal and the first clock signal, and changing the voltage of the first node to a second low level lower than the first low level based on the second clock signal; a first output buffer outputting a second clock signal as an active low scan signal in response to a voltage of a first node; and a second output buffer outputting the third clock signal as an active high scan signal in response to a voltage of the first node.

Description

Scan driver and display device

Technical Field

Embodiments relate to a scan driver that can output an active low scan signal and an active high scan signal and a display device including the same.

Background

In a display device employed in a portable device such as a smartphone, a tablet computer, or the like, reduction in power consumption can be expected. Recently, in order to reduce power consumption of the display device, a low frequency driving technology has been developed. The low frequency drive technique drives or refreshes the display panel at a lower frequency than the input frame frequency of the input image data.

However, in a display device to which the low frequency driving technique can be applied, each pixel may include a different type of transistor. For example, each pixel of the display device may include not only a Low Temperature Polysilicon (LTPS) PMOS transistor but also an oxide NMOS transistor. The scan driver of the display device should include not only a P-type stage that can generate an active low scan signal for a PMOS transistor but also an N-type stage that can generate an active high scan signal for an NMOS transistor. Therefore, in order to generate scan signals for different types of transistors, the size and power consumption of the scan driver may be increased.

It will be appreciated that this background of the technical section is intended, in part, to provide a useful background for understanding the technology. This background of the technical section, however, may also include ideas, concepts or insights that are not part of what is known or understood by those of ordinary skill in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein.

Disclosure of Invention

Embodiments may provide a scan driver capable of having a reduced size and reduced power consumption.

Embodiments may provide a display device including a scan driver.

According to an embodiment, a scan driver may be provided that includes a plurality of stages receiving first and second clock signals having a first low level as an active level and a third clock signal having a high level as an active level. Each of the plurality of stages may include a logic circuit changing a voltage of the first node to a first low level based on the input signal and the first clock signal, and changing the voltage of the first node to a second low level based on the second clock signal. The voltage level of the second low level may be lower than the voltage level of the first low level. Each of the plurality of stages may include: a first output buffer outputting a second clock signal as an active low scan signal in response to a voltage of a first node; and a second output buffer outputting the third clock signal as an active high scan signal in response to a voltage of the first node.

In an embodiment, an effective period of the third clock signal from a rising edge of the third clock signal to a falling edge of the third clock signal may overlap with an effective period of the second clock signal from a falling edge of the second clock signal to a rising edge of the second clock signal.

In an embodiment, the active period of the third clock signal may partially overlap with the active period of the second clock signal.

In an embodiment, a rising edge of the third clock signal may lag a falling edge of the first clock signal. The falling edge of the third clock signal may lag the falling edge of the second clock signal and may lead the rising edge of the second clock signal.

In an embodiment, the logic circuit may include: an input part transmitting an input signal to a third node in response to a first clock signal; a stress relaxation section provided between the first node and the third node, the stress relaxation section transmitting an input signal from the third node to the first node so that a voltage of the first node can be changed to a first low level; a bootstrap section changing a voltage of the first node to a second low level by bootstrapping the first node in response to the second clock signal; a holding section that holds the second node and the fourth node at a high level while a low-level active scan signal and a high-level active scan signal can be output; and a stabilizer part applying a high gate voltage to the third node in response to a voltage of the fourth node after the low level active scan signal and the high level active scan signal are output, and changing a voltage of the second node to a second low level.

In an embodiment, the input section may include a first transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal electrically connected to the third node.

In an embodiment, the bootstrap section may include a first capacitor including a first electrode electrically connected to a first output node at which the active low scan signal may be output and a second electrode electrically connected to the first node.

In an embodiment, the stabilizer part may include: a second transistor including a gate electrically connected to the fourth node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the third node; a second capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the second node; a third transistor including a gate electrically connected to the second node, a first terminal electrically connected to the fourth node, and a second terminal receiving the second clock signal; and a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage.

In an embodiment, each of the plurality of stages may receive a fourth clock signal having a high level as an active level and having a phase different from that of the third clock signal. The stabilizer part may include: a second transistor including a gate electrically connected to the fourth node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the third node; a second capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the second node; a third transistor including a gate electrically connected to the second node, a first terminal electrically connected to the fourth node, and a second terminal receiving a fourth clock signal; and a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage.

In an embodiment, the holding part may include: a fourth transistor including a gate electrically connected to the third node, a first terminal electrically connected to the second node, and a second terminal receiving the first clock signal; and a sixth transistor including a gate electrically connected to the third node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the fourth node.

In an embodiment, the stress relaxation portion may include a seventh transistor including a gate receiving the low gate voltage, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node.

In an embodiment, the first output buffer may include: an eighth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the first output node at which an active-low scan signal can be output, and a second terminal receiving the second clock signal; and a ninth transistor including a gate electrically connected to the second node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the first output node.

In an embodiment, the second output buffer may include: a tenth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the second output node at which an active-high scan signal can be output, and a second terminal receiving the third clock signal; and an eleventh transistor including a gate electrically connected to the second node, a first terminal receiving a low gate voltage, and a second terminal electrically connected to the second output node.

According to an embodiment, a scan driver including a plurality of stages may be provided. Each of the plurality of stages may include: a first transistor including a gate receiving a first clock signal, a first terminal receiving an input signal, and a second terminal electrically connected to a third node; a second transistor including a gate electrically connected to the fourth node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the third node; a third transistor including a gate electrically connected to the second node, a second terminal, and a first terminal electrically connected to the fourth node; a fourth transistor including a gate electrically connected to the third node, a first terminal electrically connected to the second node, and a second terminal receiving the first clock signal; a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage; a sixth transistor including a gate electrically connected to the third node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the fourth node; a seventh transistor including a gate receiving a low gate voltage, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node; a first capacitor including a first electrode electrically connected to the first output node and a second electrode electrically connected to the first node; a second capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the second node; an eighth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the first output node, and a second terminal receiving the second clock signal; a ninth transistor including a gate electrically connected to the second node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the first output node; a tenth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the second output node, and a second terminal receiving the third clock signal; and an eleventh transistor including a gate electrically connected to the second node, a first terminal receiving a low gate voltage, and a second terminal electrically connected to the second output node.

In an embodiment, the first clock signal and the second clock signal may have a low level as an active level and may have different phases. The third clock signal may have a high level as an active level.

In an embodiment, the second terminal of the third transistor may receive the second clock signal, or may receive a fourth clock signal having a high level as an active level and having a phase different from that of the third clock signal.

According to an embodiment, there may be provided a display device, which may include: a display panel including a plurality of pixels; a data driver supplying data signals to the plurality of pixels; a scan driver supplying an active low scan signal and an active high scan signal to the plurality of pixels; and a controller controlling the data driver and the scan driver. The scan driver may include a plurality of stages receiving first and second clock signals having a first low level as an active level and a third clock signal having a high level as an active level. Each of the plurality of stages may include a logic circuit changing a voltage of the first node to a first low level based on the input signal and the first clock signal, and changing the voltage of the first node to a second low level based on the second clock signal. The voltage level of the second low level may be lower than the voltage level of the first low level. Each of the plurality of stages may include: a first output buffer outputting a second clock signal as an input signal for a next stage among the plurality of stages in response to a voltage of the first node; and a second output buffer outputting the third clock signal as a corresponding one of the active-high scan signals in response to the voltage of the first node.

In an embodiment, the second clock signal output by the first output buffer may be provided as a corresponding one of the active-low scan signals to a corresponding pixel row among the plurality of pixels. The plurality of stages may sequentially supply the active low scan signal and the active high scan signal to the plurality of pixels.

In an embodiment, the scan driver may further include a plurality of P-type stages, the plurality of P-type stages may sequentially supply the active-low scan signal to the plurality of pixels, and the plurality of stages may sequentially supply the active-high scan signal to the plurality of pixels.

As described above, in the scan driver and the display device according to the embodiment, each stage may include a first output buffer that may output an active low scan signal and a second output buffer that may output an active high scan signal. Accordingly, the size and power consumption of the scan driver according to the embodiment may be reduced as compared to a conventional scan driver including separate stages that output the active low scan signal and the active high scan signal, respectively.

Drawings

The illustrative, non-limiting embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

Fig. 1 is a schematic circuit diagram showing stages included in a scan driver according to an embodiment.

Fig. 2 is a schematic timing diagram for describing an example of the operation of the stage of fig. 1.

Fig. 3 to 9 are schematic circuit diagrams for describing an example of the operation of the stage of fig. 1.

Fig. 10 is a schematic circuit diagram showing stages included in the scan driver according to the embodiment.

Fig. 11 is a schematic block diagram illustrating a display device including a scan driver according to an embodiment.

Fig. 12 is a schematic circuit diagram showing an example of a pixel included in a display device according to an embodiment.

Fig. 13 is a schematic block diagram illustrating a scan driver included in the display apparatus of fig. 11 according to an embodiment.

Fig. 14 is a schematic timing diagram for describing an example of the operation of the scan driver according to the embodiment.

Fig. 15 is a schematic block diagram illustrating a display device including a scan driver according to an embodiment.

Fig. 16 is a schematic block diagram illustrating a scan driver included in the display device of fig. 15 according to an embodiment.

Fig. 17 is a schematic circuit diagram showing a P-type stage included in the scan driver of fig. 16.

Fig. 18 is a schematic timing diagram for describing an example of the operation of the scan driver according to the embodiment.

Fig. 19 is a schematic block diagram illustrating an electronic apparatus including a display apparatus according to an embodiment.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

The terms "a," "an," and "the" can refer to one element or to more than one element. Likewise, particular numbers of elements may be described or illustrated, while the actual number of elements may vary.

The terms "stacked" or "stacked" mean that the first object may be above or below or to the side of the second object, and vice versa. Additionally, the term "stacked" may include layered stacking, facing, or variations thereof, extending, covering, or partially covering throughout, or any other suitable term as will be appreciated and understood by one of ordinary skill in the art. The term "facing" and variations thereof means that a first element can be directly or indirectly opposite a second element.

For the purposes of its meaning and explanation, the phrase "at least one of … …" is intended to include the meaning of "at least one selected from the group consisting of … …". For example, "at least one of a and B" may be understood to mean "A, B or a and B". The terms "and" or "may be used in a combined or separated sense and may be understood to be equivalent to" and/or ".

The terms "comprising," "including," and variations thereof, and/or "having" and variations thereof, as used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. It will be understood that when a feature or component is referred to as being "on … …", "over … …", "under … …", etc., relative to another feature or component, it can be directly or indirectly on the other feature or component. That is, for example, intermediate features or components may be present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to fig. 1, each stage 100 included in the scan driver according to the embodiment may receive a scan start signal FLM or a previous active low scan signal PRE _ PSS output from a previous stage as an input signal SIN, may receive first and second clock signals CLK1 and CLK2 having a first low level L (see fig. 2) as an active level, and may receive a third clock signal CLK3 having a high level H (see fig. 2) as an active level. In an embodiment, among a plurality of stages included in the scan driver, odd-numbered stages may receive the first and second P-type clock signals PCLK1 and PCLK2 for the PMOS transistors as the first and second clock signals CLK1 and CLK2, and the first and second P-type clock signals PCLK1 and PCLK2 for the PMOS transistors may have different phases (e.g., opposite phases) and may have the first low level L as an active level. The even-numbered stages may receive the second and first P-type clock signals PCLK2 and PCLK1 as the first and second clock signals CLK1 and CLK2, respectively. Further, the odd-numbered stages may receive the second N-type clock signal NCLK2 of the first and second N-type clock signals NCLK1 and NCLK2 for the NMOS transistors as the third clock signal CLK3, and the first and second N-type clock signals NCLK1 and NCLK2 for the NMOS transistors may have different phases (e.g., opposite phases) and may have a high level H as an active level. Even-numbered stages may receive the first N-type clock signal NCLK1 of the first and second N-type clock signals NCLK1 and NCLK2 as the third clock signal CLK 3.

Each stage 100 included in the scan driver according to the embodiment may include a logic circuit 110, and the logic circuit 110 may change a voltage V _ NQ (see fig. 2) of the first node NQ to a first low level L based on the input signal SIN and the first clock signal CLK1, and may change the voltage V _ NQ of the first node NQ to a second low level 2L (see fig. 2) based on the second clock signal CLK 2. The voltage level of the second low level 2L may be lower than that of the first low level L. Each stage 100 may include a first output buffer 120 and a second output buffer 130, the first output buffer 120 may output the second clock signal CLK2 as the active low scan signal PSS in response to the voltage V _ NQ of the first node NQ, and the second output buffer 130 may output the third clock signal CLK3 as the active high scan signal NSS in response to the voltage V _ NQ of the first node NQ.

As shown in fig. 1, the logic circuit 110 may include an input section 140, a stress relaxation section 150, a bootstrap section 160, a holding section 170, and a stabilizer section 180.

The input part 140 may transmit the input signal SIN to the third node NQ' in response to the first clock signal CLK 1. In an embodiment, the stress relaxation part 150 may be disposed at the node Q, the node Q may be divided into a first node NQ and a third node NQ 'by the stress relaxation part 150, and the input part 140 may be electrically connected (or coupled) to the third node NQ'. In an embodiment, the input section 140 may include a first transistor T1, the first transistor T1 including a gate receiving the first clock signal CLK1, a first terminal receiving the input signal SIN, and a second terminal electrically connected to the third node NQ'.

The stress relaxation section 150 may be disposed between the first node NQ and the third node NQ ', and may transmit the input signal SIN from the third node NQ' to the first node NQ. The voltage V _ NQ of the first node NQ may be changed to the first low level L by the input signal SIN transmitted to the first node NQ. In an embodiment, the stress relaxation part 150 may include a seventh transistor T7, the seventh transistor T7 including a gate receiving the low gate voltage VGL, a first terminal electrically connected to the third node NQ', and a second terminal electrically connected to the first node NQ.

The bootstrap section 160 may change the voltage V _ NQ of the first node NQ from the first low level L to the second low level 2L lower than the first low level L by bootstrapping the first node NQ in response to the second clock signal CLK 2. In an embodiment, the voltage level difference between the first low level L and the second low level 2L may correspond to, but is not limited to, the voltage level difference between the high level H and the first low level L. Further, in an embodiment, the bootstrap section 160 may include a first capacitor C1, the first capacitor C1 including a first electrode electrically connected to a first output node NO _ PSS at which the low-level active scan signal PSS may be output, and a second electrode electrically connected to a first node NQ.

The holding part 170 may hold the second node NQB and the fourth node NQB' at the high level H, while the active low scan signal PSS and the active high scan signal NSS may be output. Here, the second capacitor C2 may be disposed at the node QB, and thus the node QB may be divided into the second node NQB and the fourth node NQB'. The holder 170 may be electrically connected to the second node NQB and the fourth node NQB'. In an embodiment, the holding part 170 may include a fourth transistor T4 and a sixth transistor T6, the fourth transistor T4 includes a gate electrically connected to the third node NQ ', a first terminal electrically connected to the second node NQB, and a second terminal receiving the first clock signal CLK1, and the sixth transistor T6 includes a gate electrically connected to the third node NQ ', a first terminal receiving the high gate voltage VGH, and a second terminal electrically connected to the fourth node NQB '. As shown in fig. 1, the fourth transistor T4 may be implemented with, but is not limited to, two transistors connected in series.

After the active low scan signal PSS and the active high scan signal NSS may be output, the stabilizer section 180 may apply (or periodically apply) the high gate voltage VGH to the third node NQ ' in response to the voltage V _ NQB ' (see fig. 2) of the fourth node NQB ', and may change (or periodically change) the voltage V _ NQB (see fig. 2) of the second node NQB to the second low level 2L. For example, the stabilizer part 180 may periodically apply the high gate voltage VGH to the third node NQ ', and the high gate voltage VGH applied to the third node NQ' may be transferred to the first node NQ by the seventh transistor T7, and thus the high gate voltage VGH may also be periodically applied to the first node NQ. In another example, the stabilizer part 180 may periodically apply the high gate voltage VGH to the first node NQ. Further, the stabilizer part 180 may periodically change the voltage V _ NQB of the second node NQB to the second low level 2L, and thus the active low scan signal PSS and the active high scan signal NSS may be stabilized to the high level H and the low level (or the first low level L) based on the voltage V _ NQB of the second node NQB having the second low level 2L, respectively. In an embodiment, the stabilizer part 180 may include a second transistor T2, a second capacitor C2, a third transistor T3, and a fifth transistor T5, the second transistor T2 including a gate electrically connected to the fourth node NQB ', a first terminal receiving a high gate voltage VGH, and a second terminal electrically connected to the third node NQ', a second capacitor C2 including a first electrode electrically connected to the fourth node NQB 'and a second electrode electrically connected to the second node NQB, a third transistor T3 including a gate electrically connected to the second node NQB, a first terminal electrically connected to the fourth node NQB', and a second terminal receiving the second clock signal CLK2, and a fifth transistor T5 including a gate receiving the first clock signal CLK1, a first terminal electrically connected to the second node NQB, and a second terminal receiving a low gate voltage VGL. As shown in fig. 1, the third transistor T3 may be implemented with, but is not limited to, two transistors connected in series.

The first output buffer 120 may be controlled by the voltage V _ NQ of the first node NQ and/or the voltage V _ NQB of the second node NQB, and may output an active low scan signal PSS for PMOS transistors included in the pixel. The low-level active scanning signal PSS may have a low level (or a first low level L) as an active level. In an embodiment, the first output buffer 120 may include an eighth transistor T8 and a ninth transistor T9, the eighth transistor T8 includes a gate electrically connected to the first node NQ, a first terminal electrically connected to the first output node NO _ PSS at which the low-level active scan signal PSS may be output, and a second terminal receiving the second clock signal CLK2, and the ninth transistor T9 includes a gate electrically connected to the second node NQB, a first terminal receiving the high gate voltage VGH, and a second terminal electrically connected to the first output node NO _ PSS.

Similar to the first output buffer 120, the second output buffer 130 may be controlled by the voltage V _ NQ of the first node NQ and/or the voltage V _ NQB of the second node NQB. In addition, the second output buffer 130 may output an active high scan signal NSS for NMOS transistors included in the pixels. The active high scan signal NSS may have a high level H as an active level. In an embodiment, the second output buffer 130 may include a tenth transistor T10 and an eleventh transistor T11, the tenth transistor T10 including a gate electrically connected to the first node NQ, a first terminal electrically connected to the second output node NO _ NSS at which the active-high scan signal NSS may be output, and a second terminal receiving the third clock signal CLK3, the eleventh transistor T11 including a gate electrically connected to the second node NQB, a first terminal receiving the low gate voltage VGL, and a second terminal electrically connected to the second output node NO _ NSS.

As shown in fig. 1, the first to eleventh transistors T1 to T11 included in each stage 100 may be the same type of transistor, for example, MOS transistors T1 to T11. Therefore, in the scan driver according to the embodiment, the stage 100 including only the PMOS transistors T1 to T11 may generate not only the active low scan signal PSS for the PMOS transistors of the pixels but also the active high scan signal NSS for the NMOS transistors of the pixels.

As described above, in the scan driver according to the embodiment, each stage 100 may include the logic circuit 110, the first output buffer 120, and the second output buffer 130, the logic circuit 110 may control the voltage V _ NQ of the first node NQ and the voltage V _ NQB of the second node NQB, the first output buffer 120 may output the active low scan signal PSS based on the voltage V _ NQ of the first node NQ and the voltage V _ NQB of the second node NQB, and the second output buffer 130 may output the active high scan signal NSS based on the voltage V _ NQ of the first node NQ and the voltage V _ NQB of the second node NQB. Accordingly, since the low level active scan signal PSS and the high level active scan signal NSS may be output by a single stage 100, the size and power consumption of the scan driver according to the embodiment may be reduced as compared to the conventional scan driver including separate stages that output the low level active scan signal PSS and the high level active scan signal NSS, respectively.

Hereinafter, an example of the operation of the stage 100 will be described below with reference to fig. 1 to 9.

Fig. 2 is a schematic timing diagram for describing an example of the operation of the stage of fig. 1, and fig. 3 to 9 are schematic circuit diagrams for describing an example of the operation of the stage of fig. 1.

Referring to fig. 1 and 2, each stage 100 may receive an input signal SIN and first to third clock signals CLK1, CLK2, and CLK 3. The input signal SIN may be a scan start signal FLM with respect to a first stage among a plurality of stages included in the scan driver, and may be a previous active low scan signal PRE _ PSS with respect to the remaining plurality of stages. Further, the first clock signal CLK1 and the second clock signal CLK2 may have different phases (e.g., opposite phases) and may have the first low level L as an active level. The third clock signal CLK3 may have a high level H as an active level. In an embodiment, as shown in fig. 2, the active period (or ON period) may be shorter than the inactive period (or OFF period) with respect to each of the first to third clock signals CLK1, CK2, and CLK 3. For example, the duty ratio of each of the first to third clock signals CLK1, CLK2, and CLK3 may be, but is not limited to, about 40%. In another example, an active period of each of the first to third clock signals CLK1, CLK2, and CLK3 may be longer than or equal to an inactive period.

In a period from the first time point TP1 to the second time point TP2, the input signal SIN having the first low level L may be applied, and the first clock signal CLK1 having the first low level L may be applied. As shown in fig. 3, the first transistor T1 may be turned on in response to the first clock signal CLK1 having the first low level L, and the seventh transistor T7 may be turned on in response to the low gate voltage VGL having the first low level L. The input signal SIN may be transferred to the third node NQ ' by the turned-on first transistor T1, and thus the voltage V _ NQ ' of the third node NQ ' may be changed from the high level H to the first low level L. In addition, the input signal SIN at the third node NQ' may be transferred to the first node NQ by the turned-on seventh transistor T7, and thus the voltage V _ NQ of the first node NQ may be changed from the high level H to the first low level L.

The first clock signal CLK1 may change from the first low level L to the high level H at the second time point TP2, and the first clock signal CLK1 having the high level H may be applied in a period from the second time point TP2 to the third time point TP 3. As shown in fig. 4, the fourth and sixth transistors T4 and T6 may be turned on in response to the voltage V _ NQ 'of the third node NQ' having the first low level L. The first clock signal CLK1 having a high level H may be transmitted to the second node NQB by the turned-on fourth transistor T4, and the voltage V _ NQB of the second node NQB may change from the first low level L to the high level H. In addition, the turned-on sixth transistor T6 may apply a high gate voltage VGH to the fourth node NQB' or the first electrode of the second capacitor C2, and the turned-on fourth transistor T4 may apply the first clock signal CLK1 having a high level H to the second node NQB or the second electrode of the second capacitor C2. Accordingly, the second capacitor C2 may be initialized or discharged.

The third clock signal CLK3 may change from the first low level L to the high level H at the third time point TP3, and the third clock signal CLK3 having the high level H may be applied in a period from the third time point TP3 to the fourth time point TP 4. As shown in fig. 5, the tenth transistor T10 may be turned on in response to the voltage V _ NQ having the first low level L of the first node NQ, and the third clock signal CLK3 having the high level H may be output at the second output node NO _ NSS as the active high scan signal NSS having the high level H by the turned on tenth transistor T10.

The second clock signal CLK2 may change from the high level H to the first low level L at the fourth time point TP4, and the second clock signal CLK2 having the first low level L may be applied in a period from the fourth time point TP4 to the fifth time point TP 5. As shown in fig. 6, the eighth transistor T8 may be turned on in response to the voltage V _ NQ of the first node NQ, and the second clock signal CLK2 having the first low level L may be output at the first output node NO _ PSS as the active low scan signal PSS having the first low level L by the turned-on eighth transistor T8. If the second clock signal CLK2 having the first low level L is applied to the first output node NO _ PSS through the turned-on eighth transistor T8, the voltage of the first output node NO _ PSS or the voltage of the first electrode of the first capacitor C1 may be changed from the high level H to the first low level L. If the voltage of the first electrode of the first capacitor C1 is changed from the high level H to the first low level L, the voltage of the second electrode of the first capacitor C1 or the voltage V _ NQ of the first node NQ may be changed from the first low level L to the second low level 2L lower than the first low level L. In an embodiment, the voltage level difference between the first low level L and the second low level 2L may correspond to, but is not limited to, the voltage level difference between the high level H and the first low level L. Here, an operation of the voltage V _ NQ of the first node NQ changing from the first low level L to the second low level 2L may be referred to as a bootstrap operation, and the first capacitor C1 may be referred to as a bootstrap capacitor.

In a case where the stage 100 may not include the seventh transistor T7, or in a case where the first node NQ and the third node NQ 'may be the same node, if the voltage V _ NQ of the first node NQ is changed from the first low level L to the second low level 2L, the voltage V _ NQ of the first node NQ having a high absolute value may be applied to the transistors T1, T2, T4, and T6 electrically connected (e.g., directly electrically connected) to the third node NQ'. Specifically, since a voltage having a high level H may be applied to first terminals of the transistors T1, T2, T4, and T6, and a voltage having a second low level 2L may be applied to second terminals or gates of the transistors T1, T2, T4, and T6, high voltage stress may be applied to the transistors T1, T2, T4, and T6. However, in the stage 100 of the scan driver according to the embodiment, although the voltage V _ NQ of the first node NQ may have the second low level 2L, the low gate voltage VGL having the first low level L higher than the second low level 2L may be applied to the gate of the seventh transistor T7, and thus the voltage V _ NQ of the first node NQ may not be transmitted to the third node NQ'. Accordingly, voltage stress applied to the transistors T1, T2, T4, and T6 electrically connected (e.g., directly electrically connected) to the third node NQ' may be reduced. Therefore, the seventh transistor T7 may be referred to as a stress relaxation (or release) transistor.

Further, while the active low scan signal PSS and the active high scan signal NSS may be output, the voltage V _ NQB of the second node NQB and the voltage V _ NQB 'of the fourth node NQB' may be held or maintained at the high level H by the fourth transistor T4 and the sixth transistor T6 having gates receiving the voltage V _ NQ 'of the third node NQ'. Accordingly, while the active low scan signal PSS and the active high scan signal NSS may be output, the ninth transistor T9 and the eleventh transistor T11 may not be turned on based on the voltage V _ NQB of the second node NQB having the high level H.

The third clock signal CLK3 may change from the high level H to the first low level L at the fifth time point TP5, and the third clock signal CLK3 having the first low level L may be applied in a period from the fifth time point TP5 to the sixth time point TP 6. As shown in fig. 7, the turned-ON state of the tenth transistor T10 may be maintained in response to the voltage V _ NQ of the first node NQ having the second low level 2L, and the active high scan signal NSS at the second output node NO _ NSS may be changed from the high level H, which may be an active level (or ON level), to the first low level L, which may be an inactive level (or OFF level), through the turned-ON tenth transistor T10. Although the third clock signal CLK3 applied to the second terminal of the tenth transistor T10 may have the first low level L, in order to maintain the turned-on state of the tenth transistor T10, a voltage having a voltage level lower than the first low level L should be applied to the gate of the tenth transistor T10. In the stage 100 according to the embodiment, since the third clock signal CLK3 may be changed to the first low level L in a case where the voltage V _ NQ of the first node NQ applied to the gate of the tenth transistor T10 may have the second low level 2L lower than the first low level L, the turned-on state of the tenth transistor T10 may be maintained, and the active-high scan signal NSS may be changed to the first low level L which may be an inactive level (or OFF level).

In an embodiment, in order to change the third clock signal CLK3 to the first low level L while the voltage V _ NQ of the first node NQ may have the second low level 2L, a rising edge of the third clock signal CLK3 (e.g., the third time point TP3) may lag a falling edge of the first clock signal CLK1 (e.g., the first time point TP1), and a falling edge of the third clock signal CLK3 (e.g., the fifth time point TP5) may lead a rising edge of the second clock signal CLK2 (e.g., the sixth time point TP 6). Further, as shown in fig. 2, the effective period AP1 of the third clock signal CLK3 from the rising edge of the third clock signal CLK3 (e.g., the third time point TP3) to the falling edge of the third clock signal CLK3 (e.g., the fifth time point TP5) may be different from the effective period AP2 of the second clock signal CLK2 from the falling edge of the second clock signal CLK2 (e.g., the fourth time point TP4) to the rising edge of the second clock signal CLK2 (e.g., the sixth time point TP6), and the effective period AP1 of the third clock signal CLK3 may overlap (e.g., partially overlap) with the effective period AP2 of the second clock signal CLK 2. For example, a falling edge of the third clock signal CLK3 (e.g., the fifth time point TP5) may lag behind a falling edge of the second clock signal CLK2 (e.g., the fourth time point TP4) and may lead a rising edge of the second clock signal CLK2 (e.g., the sixth time point TP 6). Accordingly, the active high scan signal NSS having the high level H may be output at a rising edge (e.g., the third time point TP3) of the third clock signal CLK3, and the active high scan signal NSS may change to the first low level L, which may be an inactive level (or OFF level), at a falling edge (e.g., the fifth time point TP5) of the third clock signal CLK 3.

If the second clock signal CLK2 changes to the high level H at the sixth time point TP6, the active low scan signal PSS at the first output node NO _ PSS may change to the high level H which may be a non-active level (or OFF level). If the voltage of the first output node NO _ PSS or the voltage of the first electrode of the first capacitor C1 is changed from the first low level L to the high level H, the voltage of the second electrode of the first capacitor C1 or the voltage V _ NQ of the first node NQ may be changed from the second low level 2L to the first low level L.

The first clock signal CLK1 may change from the high level H to the first low level L at the seventh time point TP7, and the first clock signal CLK1 having the first low level L may be applied in a period from the seventh time point TP7 to the eighth time point TP 8. As shown in fig. 8, the first and fifth transistors T1 and T5 may be turned on in response to the first clock signal CLK1 having the first low level L, and the seventh transistor T7 may be turned on in response to the low gate voltage VGL having the first low level L. The voltage V _ NQ 'of the third node NQ' may be changed from the first low level L to the high level H by the turned-on first transistor T1, and the voltage V _ NQ of the first node NQ may be changed from the first low level L to the high level H by the turned-on seventh transistor T7. In addition, the voltage V _ NQB of the second node NQB may be changed from the high level H to the first low level L by the turned-on fifth transistor T5. The third and ninth transistors T3 and T9 may be turned on in response to the voltage V _ NQB of the second node NQB having the first low level L. The second clock signal CLK2 having the high level H may be transmitted to the fourth node NQB' by the turned-on third transistor T3. Accordingly, the first electrode of the second capacitor C2 may have a voltage having a high level H, and the second electrode of the second capacitor C2 may have a voltage having a first low level L. In addition, the active low level scan signal PSS at the first output node NO _ PSS may be stabilized to the high level H which may be an inactive level (or OFF level).

The second clock signal CLK2 may change from the high level H to the first low level L at the ninth time point TP9, and the second clock signal CLK2 having the first low level L may be applied in a period from the ninth time point TP9 to the tenth time point TP 10. As shown in fig. 9, the second clock signal CLK2 having the first low level L may be applied to the fourth node NQB ' through the turned-on third transistor T3, and the voltage V _ NQB ' of the fourth node NQB ' or the voltage of the first electrode of the second capacitor C2 may be changed from the high level H to the first low level L. If the voltage of the first electrode of the second capacitor C2 is changed from the high level H to the first low level L, the voltage of the second electrode of the second capacitor C2 or the voltage V _ NQB of the second node NQB may be changed from the first low level L to the second low level 2L. Here, an operation of the voltage V _ NQB of the second node NQB changing from the first low level L to the second low level 2L may be referred to as a bootstrap operation, and the second capacitor C2 may also be referred to as a bootstrap capacitor. If the voltage V _ NQB of the second node NQB may have the second low level 2L, the ninth transistor T9 and the eleventh transistor T11 may be fully turned on, and the active low scan signal PSS at the first output node NO _ PSS and the active high scan signal NSS at the second output node NO _ NSS may be stabilized to the high level H and the first low level L, which may be an inactive level (or OFF level), respectively, by the turned-on ninth transistor T9 and the eleventh transistor T11. In addition, the second transistor T2 may be turned on in response to the voltage V _ NQB 'of the fourth node NQB' having the first low level L, and the seventh transistor T7 may be turned on in response to the low gate voltage VGL having the first low level L. The high gate voltage VGH may be applied to the third node NQ ' by the turned-on second transistor T2, and the voltage V _ NQ ' of the third node NQ ' may be stabilized to a high level H. In addition, the voltage V _ NQ of the first node NQ may be stabilized to the high level H by the turned-on seventh transistor T7. As described above, the second transistor T2 may periodically apply the high gate voltage VGH to the third node NQ ' in response to the voltage V _ NQB ' of the fourth node NQB ' (or whenever the second clock signal CLK2 may have the first low level L), and the fifth transistor T5, the second capacitor C2, and the third transistor T3 may periodically change the voltage V _ NQB of the second node NQB (or whenever the second clock signal CLK2 may have the first low level L) to the second low level 2L. Accordingly, after the active low scan signal PSS and the active high scan signal NSS having an active level (or ON level) may be output, the active low scan signal PSS and the active high scan signal NSS may be stabilized to a high level H and a first low level L, which may be an inactive level (or OFF level), respectively.

As described above, in the scan driver according to the embodiment, each stage 100 may output not only the active low scan signal PSS having the first low level L as an active level but also the active high scan signal NSS having the high level H as an active level. Accordingly, the size and power consumption of the scan driver according to the embodiment may be reduced.

Referring to fig. 10, each stage 200 included in the scan driver according to the embodiment may include a logic circuit 210, a first output buffer 120 that may output an active low scan signal PSS, and a second output buffer 130 that may output an active high scan signal NSS. In an embodiment, the logic circuit 210 may include an input section 140, a stress relaxation section 150, a bootstrap section 160, a holding section 170, and a stabilizer section 280. Stage 200 of fig. 10 may have a similar construction and similar operation as stage 100 of fig. 1, except that stabilizer section 280 of logic circuit 210 may receive fourth clock signal CLK4 instead of second clock signal CLK 2.

The stage 200 may receive the first and second clock signals CLK1 and CLK2 having the first low level L as an active level and the third clock signal CLK3 having the high level H as an active level, and may also receive the fourth clock signal CLK4 having the high level H as an active level and having a phase different from that of the third clock signal CLK 3. In an embodiment, the first and second clock signals CLK1 and CLK2 may be first and second P-type clock signals PCLK1 and PCLK2 for PMOS transistors, the first and second P-type clock signals PCLK1 and PCLK2 for PMOS transistors have different phases (e.g., opposite phases) and may have a first low level L as an active level, the third and fourth clock signals CLK3 and CLK4 may be second and first N-type clock signals NCLK2 and NCLK1 for NMOS transistors, the second and first N-type clock signals NCLK2 and NCLK1 for NMOS transistors may have different phases (e.g., opposite phases) and may have a high level H as an active level. Further, in an embodiment, each of the first through fourth clock signals CLK1, CLK2, CLK3, and CLK4 may have a duty cycle less than or equal to about 50%. For example, the duty ratio of each of the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 may be, but is not limited to, about 40%. The inactive period of the fourth clock signal CLK4, which may be an N-type clock signal, or the low level period of the fourth clock signal CLK4 may be longer than the active period of the second clock signal CLK2, which may be a P-type clock signal, or the low level period of the second clock signal CLK 2.

As shown in fig. 10, the stabilizer part 280 of the logic circuit 210 may include a second transistor T2, a second capacitor C2, a third transistor T3', and a fifth transistor T5, the second transistor T2 including a gate electrically connected to the fourth node NQB', a first terminal receiving a high gate voltage VGH, and a second terminal electrically connected to the third node NQ ', the second capacitor C2 including a first electrode electrically connected to the fourth node NQB' and a second electrode electrically connected to the second node NQB, the third transistor T3 'including a gate electrically connected to the second node NQB, a first terminal electrically connected to the fourth node NQB' and a second terminal receiving a fourth clock signal CLK4, the fifth transistor T5 including a gate receiving the first clock signal CLK1, a first terminal electrically connected to the second node NQB, and a second terminal receiving a low gate voltage VGL. During the low level period of the fourth clock signal CLK4, the stabilizer section 280 including the second transistor T2, the second capacitor C2, the third transistor T3', and the fifth transistor T5 may change the voltage V _ NQB of the second node NQB to a second low level 2L lower than the first low level L. If the voltage V _ NQB of the second node NQB is changed to the second low level 2L, the active low scan signal PSS and the active high scan signal NSS may be stabilized to the high level H and the first low level L, which may be inactive levels, by the ninth transistor T9 and the eleventh transistor T11, respectively. The low level period of the fourth clock signal CLK4 may be longer than the low level period of the second clock signal CLK2, and thus the active low scan signal PSS and the active high scan signal NSS may be further stabilized in the stage 200 of fig. 10 as compared to the stage 100 of fig. 1.

Fig. 11 is a schematic block diagram showing a display device including a scan driver according to an embodiment, fig. 12 is a schematic circuit diagram showing an example of a pixel included in the display device according to the embodiment, fig. 13 is a schematic block diagram showing the scan driver included in the display device of fig. 11 according to the embodiment, and fig. 14 is a schematic timing chart for describing an example of an operation of the scan driver according to the embodiment.

Referring to fig. 11, the display device 300 according to the embodiment may include a display panel 310, a data driver 320, a scan driver 330, and a controller 350, the display panel 310 may include pixels PX, the data driver 320 may supply a data signal DS to the pixels PX, the scan driver 330 may supply low-level active scan signals PSS1, PSS2 …, and high-level active scan signals NSS1, NSS2 … to the pixels PX, and the controller 350 may control the data driver 320 and the scan driver 330. In an embodiment, the display device 300 may further include an emission driver 340 that may provide the emission signal SEM to the pixels PX.

The display panel 310 may include data signal lines, low-level active scan signal lines, high-level active scan signal lines, emission signal lines, and pixels PX electrically connected thereto. In an embodiment, each pixel PX may include at least one capacitor, at least two transistors, and an Organic Light Emitting Diode (OLED), and the display panel 310 may be an OLED display panel. Further, in an embodiment, each pixel PX may include a different type of transistor suitable for low frequency driving capable of reducing power consumption. For example, each pixel PX may include at least one Low Temperature Polysilicon (LTPS) PMOS transistor and at least one oxide NMOS transistor.

For example, as shown in fig. 12, each pixel PX may include a driving transistor PXT1, a switching transistor PXT2, a compensation transistor PXT3, a storage capacitor CST, a first initialization transistor PXT4, a first emission transistor PXT5, a second emission transistor PXT6, a second initialization transistor (or bypass transistor) PXT7, and an organic light emitting diode EL, the driving transistor PXT1 may generate a driving current, the switching transistor PXT2 may transmit a data signal DS from the data driver 320 to a first terminal of the driving transistor PXT1 in response to a low-level active scan signal PSS from the scan driver 330, the compensation transistor PXT3 may diode-connect the driving transistor PXT1 in response to a high-level active scan signal NSS from the scan driver 330, the storage capacitor CST may store the data signal DS transmitted through the switching transistor PXT2 and the diode-connected driving transistor PXT1, the first initialization transistor PXT4 may supply the initialization voltage VINIT to the storage capacitor CST and the gate of the driving transistor PXT1 in response to the initialization signal SI from the scan driver 330 (or the high-level active scan signal PRE _ NSS for the pixels PX in the previous pixel row), the first emission transistor PXT5 may connect a line of the high power supply voltage ELVDD to a first terminal of the driving transistor PXT1 in response to the emission signal SEM from the emission driver 340, the second emission transistor PXT6 may connect a second terminal of the driving transistor PXT1 to the organic light emitting diode EL in response to the emission signal SEM from the emission driver 340, the second initialization transistor (or bypass transistor) PXT7 may supply the initialization voltage ninit to the organic light emitting diode EL in response to the bypass signal SB from the scan driver 330 (or the low-level active scan signal nexits for the pixels PX in another (e.g., NEXT) pixel row, the organic light emitting diode EL emits light based on the driving current from the line of the high power supply voltage ELVDD to the line of the low power supply voltage ELVSS.

At least one of the driving transistor PXT1, the switching transistor PXT2, the compensation transistor PXT3, the first initialization transistor PXT4, the first emission transistor PXT5, the second emission transistor PXT6, and the second initialization transistor PXT7 may be implemented with a PMOS transistor, and at least one of the driving transistor PXT1, the switching transistor PXT2, the compensation transistor PXT3, the first initialization transistor PXT4, the first emission transistor PXT5, the second emission transistor PXT6, and the second initialization transistor PXT7 may be implemented with an NMOS transistor. For example, as shown in fig. 12, the compensation transistor PXT3 and the first initialization transistor PXT4 may be implemented with NMOS transistors, and the other transistors PXT1, PXT2, PXT5, PXT6, and PXT7 may be implemented with PMOS transistors. The high active signals NSS and PRE _ NSS may be applied to the compensation transistor PXT3 and the first initialization transistor PXT 4. Since the transistors PXT3 and PXT4 electrically connected (e.g., directly electrically connected) to the storage capacitor CST may be implemented with NMOS transistors, leakage current from the storage capacitor CST may be reduced, and thus the pixel PX may be suitable for low frequency driving. Although fig. 12 shows an example in which the compensation transistor PXT3 and the first initialization transistor PXT4 may be implemented with NMOS transistors, the configuration of each pixel PX may not be limited to the example of fig. 12. In another example, the display panel 310 may be a Liquid Crystal Display (LCD) panel or the like.

The data driver 320 may generate the data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 350, and may supply the data signal DS to the pixels PX through the data signal lines. In an example, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In an embodiment, the data driver 320 and the controller 350 may be implemented with a single integrated circuit, which may be referred to as a timing controller embedded data driver (TED). In another embodiment, the data driver 320 and the controller 350 may be implemented in separate integrated circuits.

The scan driver 330 may generate the active low scan signals PSS1, PSS2 … and the active high scan signals NSS1, NSS2 … based on scan control signals that may be received from the controller 350, and may supply the active low scan signals PSS1, PSS2 … and the active high scan signals NSS1, NSS2 … to the pixels PX through active low scan signal lines and active high scan signal lines. In an embodiment, the scan control signals may include, but are not limited to, a scan start signal FLM, first and second P-type clock signals PCLK1 and PCLK2, and first and second N-type clock signals NCLK1 and NCLK 2. In an embodiment, the scan driver 330 may be integrated or formed in a peripheral portion of the display panel 310. In another example, scan driver 330 may be implemented with one or more integrated circuits.

As shown in fig. 13, the scan driver 330 may include a plurality of

stages

331, 332, 333, 334 …, and the plurality of

stages

331, 332, 333, 334 … may output active low scan signals PSS1, PSS2 … and active high scan signals NSS1, NSS2 …. In an embodiment, each stage (e.g., 331) may output an active low scan signal (e.g., PSS1) for a P-type transistor (e.g., PMOS transistor) and an active high scan signal (e.g., NSS1) for an N-type transistor (e.g., NMOS transistor), and thus may be referred to as an NP integration stage.

The plurality of

stages

331, 332, 333, 334 … may receive the scan start signal FLM, may receive the first and second P-type clock signals PCLK1 and PCLK2 having a low level as an active level and having different phases (e.g., opposite phases), and may also receive the first and second N-type clock signals NCLK1 and NCLK2 having a high level as an active level and having different phases (e.g., opposite phases). A first stage 331 of the plurality of

stages

331, 332, 333, 334 … may receive the scan start signal FLM as an input signal SIN, and the remaining plurality of

stages

332, 333, 334 … may receive the active low scan signals PSS1, PSS2, PSS3, PSS4 … from the previous stage as the input signal SIN. In an embodiment, the odd-numbered

stages

331, 333 … may receive the first P-type clock signal PCLK1, the second P-type clock signal PCLK2, and the second N-type clock signal NCLK2 as the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3, respectively. The even-numbered

stages

332, 334 … may receive the second P-type clock signal PCLK2, the first P-type clock signal PCLK1, and the first N-type clock signal NCLK1 as the first, second, and third clock signals CLK1, CLK2, and CLK3, respectively.

According to an embodiment, each of the plurality of

stages

331, 332, 333, 334 … may have a configuration similar to that of stage 100 of fig. 1, stage 200 of fig. 10, and so on. For example, each of the plurality of

stages

331, 332, 333, 334 … may include a

logic circuit

110 or 210, a first output buffer 120, and a second output buffer 130, the

logic circuit

110 or 210 may change a voltage V _ NQ of a first node NQ to a first low level L based on an input signal SIN and a first clock signal CLK1, and may change the voltage V _ NQ of the first node NQ to a second low level 2L lower than the first low level L based on a second clock signal CLK2, the first output buffer 120 may output a second clock signal CLK2 as a corresponding one of an input signal SIN (i.e., a carry signal) and/or a low-level valid scan signal 1, PSS2, PSS3, PSS4 … for another (e.g., a next) stage in response to the voltage V _ NQ of the first node NQ, and the second output buffer 130 may output a third clock signal nsclk 26 as a high-level valid scan signal PSS3 s1 s 3668 in response to the voltage V _ NQ of the first node NQ, A corresponding one of NSS2, NSS3, NSS4 ….

As shown in fig. 13 and 14, the first stage 331 may output the first active-high scan signal NSS1 to the first pixel row in synchronization with the second N-type clock signal NCLK2, and may output the first active-low scan signal PSS1 to the first pixel row in synchronization with the second P-type clock signal PCLK 2. Also, the second stage 332 may output the second active high scan signal NSS2 to the second pixel row in synchronization with the first N-type clock signal NCLK1, and may output the second active low scan signal PSS2 to the second pixel row in synchronization with the first P-type clock signal PCLK 1. Further, the third stage 333 may output the third active high scan signal NSS3 to the third pixel row in synchronization with the second N-type clock signal NCLK2, and may output the third active low scan signal PSS3 to the third pixel row in synchronization with the second P-type clock signal PCLK 2. Further, the fourth stage 334 may output the fourth active high scan signal NSS4 to the fourth pixel row in synchronization with the first N-type clock signal NCLK1, and may output the fourth active low scan signal PSS4 to the fourth pixel row in synchronization with the first P-type clock signal PCLK 1. In this manner, the plurality of

stages

331, 332, 333, 334 … may sequentially output the low-level effective scan signals PSS1, PSS2, PSS3, PSS4 … to the pixels PX on a pixel row basis, and may sequentially output the high-level effective scan signals NSS1, NSS2, NSS3, NSS4 … to the pixels PX on a pixel row basis.

The emission driver 340 may generate an emission signal SEM based on the emission control signal EMCTRL received from the controller 350, and may provide the emission signal SEM to the pixels PX through the emission signal line. In an embodiment, the emission signal SEM may be sequentially supplied to the pixels PX on a pixel row basis. In another example, the emission signal SEM may be a global signal that may be provided to the pixels PX substantially simultaneously. In an embodiment, the emission driver 340 may be integrated or formed in a peripheral portion of the display panel 310. In another example, the transmit driver 340 may be implemented with one or more integrated circuits.

The controller (e.g., a Timing Controller (TCON))350 may receive input image data IDAT and a control signal CTRL from an external host (e.g., a Graphics Processing Unit (GPU) or a graphics card). In an embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, and the like. The controller 350 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and an emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 350 may control the operation of the data driver 320 by supplying the output image data ODAT and the data control signal DCTRL to the data driver 320, may control the operation of the scan driver 330 by supplying the scan control signal to the scan driver 330, and may control the operation of the emission driver 340 by supplying the emission control signal EMCTRL to the emission driver 340.

As described above, in the display device 300 according to the embodiment, each stage (e.g., 331) of the scan driver 330 may output an active low scan signal (e.g., PSS1) and an active high scan signal (e.g., NSS 1). Accordingly, the size and power consumption of the scan driver 330 of the display apparatus 300 according to the embodiment may be reduced as compared to a conventional scan driver including separate stages that output an active low scan signal and an active high scan signal, respectively.

Fig. 15 is a schematic block diagram illustrating a display device including a scan driver according to an embodiment, fig. 16 is a schematic block diagram illustrating a scan driver included in the display device of fig. 15 according to the embodiment, fig. 17 is a schematic circuit diagram illustrating a P-type stage included in the scan driver of fig. 16, and fig. 18 is a schematic timing diagram for describing an example of an operation of the scan driver according to the embodiment.

Referring to fig. 15, a display apparatus 400 according to an embodiment may include a display panel 410, a data driver 420, a scan driver 430, and a controller 450. In an embodiment, the display apparatus 400 may further include an emission driver 440 that may provide the emission signal SEM to the pixels PX. The display device 400 of fig. 15 may have a similar configuration and a similar operation to the display device 300 of fig. 11 except that the scan driver 430 may include not only a plurality of

stages

431, 432 … (or a plurality of NP integrated stages), but also a plurality of P-

type stages

461, 462 …. Unlike the plurality of

stages

331, 332 … that supply the low-level effective scan signals PSS1, PSS2 … and the high-level effective scan signals NSS1, NSS2 … to the pixels PX shown in fig. 11, the plurality of

stages

431, 432 … may sequentially supply only the high-level effective scan signals NSS1, NSS2 … to the pixels PX on a pixel row basis. The plurality of P-

type stages

461, 462 … may sequentially supply the low-level effective scanning signals PSS1, PSS2 … to the pixels PX on a pixel row basis.

According to an embodiment, each of the plurality of

stages

431, 432 … may have a configuration similar to that of stage 100 of fig. 1, stage 200 of fig. 10, and so on. As shown in fig. 16, the plurality of

stages

431, 432, 433, 434 … may receive a first scan start signal FLM1, first and second P-type clock signals PCLK1 and PCLK2, and first and second N-type clock signals NCLK1 and NCLK2, and may sequentially supply high-level active scan signals NSS1, NSS2, NSS3, NSS4 … to the pixels PX on a pixel row basis. The low-level active scan signal generated by each of the plurality of

stages

431, 432, 433, 434 … may not be supplied to the pixels PX, and may be used as an input signal or carry signal CR1, CR2, CR3, CR4 … for another (e.g., next) stage.

As shown in fig. 16, the plurality of P-

type stages

461, 462, 463, 464 … may receive the second scan start signal FLM2 and the third and fourth P-type clock signals PCLK3 and PCLK 4. In an embodiment, each of the plurality of P-

type stages

461, 462, 463, 464 … may be implemented as a P-type stage PSTAGE shown in fig. 17. For example, as shown in fig. 17, each P-type stage PSTAGE may include first to seventh transistors M1 to M7 and first and second capacitors PC1 and PC 2. In each of the P-type stages PSTAGE, the first transistor M1 may transmit the second scan start signal FLM2 or the previous active low scan signal PRE _ PSS to the first node N1 in response to the third P-type clock signal PCLK3 (or the fourth P-type clock signal PCLK4), the second transistor M2 may transmit the high gate voltage VGH to the third node N3 in response to the voltage of the second node N2, the third transistor M3 may transmit the voltage of the third node N3 to the first node N1 in response to the fourth P-type clock signal PCLK4 (or the third P-type clock signal PCLK3), the fourth transistor M4 may transmit the third P-type clock signal PCLK3 (or the fourth P-type clock signal PCLK4) to the second node N2 in response to the voltage of the first node N1, the fifth transistor M5 may transmit the gate voltage PCLK 24 or the fourth P-type clock signal PCLK 4624 to the second node N2 in response to the third P type clock signal PCLK 3984 (or the fourth PCLK3), the sixth transistor M6 may output the high gate voltage VGH as the active low scan signal PSS to the output node NO in response to the voltage of the second node N2, and the seventh transistor M7 may output the fourth P-type clock signal PCLK4 (or the third P-type clock signal PCLK3) as the active low scan signal PSS to the output node NO in response to the voltage of the first node N1. In addition, the first capacitor PC1 may be electrically connected between a line of the high gate voltage VGH and the second node N2, and the second capacitor PC2 may be electrically connected between the first node N1 and the output node NO. As shown in fig. 17, all of the first to seventh transistors M1 to M7 of each P-type stage PSTAGE may be PMOS transistors. However, the configuration of each of the plurality of P-

type stages

461, 462, 463, 464 … of the scan driver 430 may not be limited to the configuration of fig. 17.

As shown in fig. 16 and 18, the first P-type stage 461 may output the first active low scan signal PSS1 to the first pixel row in synchronization with the fourth P-type clock signal PCLK4, and the first stage 431 may output the first active high scan signal NSS1 to the first pixel row in synchronization with the second N-type clock signal NCLK 2. In addition, the second P-type stage 462 may output the second active low scan signal PSS2 to the second pixel row in synchronization with the third P-type clock signal PCLK3, and the second stage 432 may output the second active high scan signal NSS2 to the second pixel row in synchronization with the first N-type clock signal NCLK 1. Further, the third P-type stage 463 may output the third active low scan signal PSS3 to the third pixel row in synchronization with the fourth P-type clock signal PCLK4, and the third stage 433 may output the third active high scan signal NSS3 to the third pixel row in synchronization with the second N-type clock signal NCLK 2. Further, the fourth P-type stage 464 may output the fourth active low scan signal PSS4 to the fourth pixel row in synchronization with the third P-type clock signal PCLK3, and the fourth stage 434 may output the fourth active high scan signal NSS4 to the fourth pixel row in synchronization with the first N-type clock signal NCLK 1. In this manner, the plurality of P-

type stages

461, 462, 463, 464 … may sequentially supply the low-level effective scan signals PSS1, PSS2, PSS3, PSS4 … to the pixels PX on a pixel row basis, and the plurality of

stages

431, 432, 433, 434 … may sequentially supply the high-level effective scan signals NSS1, NSS2, NSS3, NSS4 … to the pixels PX on a pixel row basis. As shown in fig. 18, the active period of the third P-type clock signal PCLK3 may be substantially the same as (or substantially completely overlap with) the active period of the first N-type clock signal NCLK1, and the active period of the fourth P-type clock signal PCLK4 may be substantially the same as (or substantially completely overlap with) the active period of the second N-type clock signal NCLK 2. The active period of each active-low scan signal (e.g., PSS1) may be substantially the same as (or substantially completely overlap with) the active period of the corresponding active-high scan signal (e.g., NSS 1).

Referring to fig. 19, an electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input/output (I/O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include ports for communicating with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, other electronic devices, and the like.

Processor 1110 may perform various computing functions or tasks. The processor 1110 may be an Application Processor (AP), a microprocessor, a Central Processing Unit (CPU), or the like. The processor 1110 may be electrically connected to the other components via an address bus, a control bus, a data bus, etc. Further, in an embodiment, the processor 1110 may also be electrically connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 1120 may store data for operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an Erasable Programmable Read Only Memory (EPROM) device, an Electrically Erasable Programmable Read Only Memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a Resistive Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a polymer random access memory (ponam) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, etc., and/or at least one volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

The storage device 1130 may be a Solid State Drive (SSD) device, a Hard Disk Drive (HDD) device, a CD-ROM device, or the like. I/O devices 1140 may be input devices such as a keyboard, keypad, mouse, touch screen, etc., and output devices such as a printer, speakers, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. Display device 1160 may be electrically connected to the other components through a bus or other communication link.

In the display device 1160, each stage of the scan driver may include a first output buffer that may output an active low scan signal and a second output buffer that may output an active high scan signal. Accordingly, the size and power consumption of the scan driver of the display device 1160 according to the embodiment may be reduced as compared to the conventional scan driver including separate stages that output the active low and active high scan signals, respectively.

The concepts of the present disclosure can be applied to any display device 1160 and any electronic device 1100 that includes the display device 1160. For example, the concepts may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, Televisions (TVs), digital TVs, 3D TVs, Personal Computers (PCs), home appliances, laptop computers, Personal Digital Assistants (PDAs), Portable Multimedia Players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this disclosure. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the claims and any equivalents thereof.

Claims

1. A scan driver, the scan driver comprising:

a plurality of stages receiving first and second clock signals having a first low level as an active level and a third clock signal having a high level as the active level, each of the plurality of stages including: a logic circuit changing a voltage of a first node to the first low level based on an input signal and the first clock signal, and changing the voltage of the first node to a second low level based on the second clock signal, the second low level having a voltage level lower than that of the first low level; a first output buffer outputting the second clock signal as an active low scan signal in response to the voltage of the first node; and a second output buffer outputting the third clock signal as an active high scan signal in response to the voltage of the first node.

2. The scan driver of claim 1, wherein an active period of the third clock signal from a rising edge of the third clock signal to a falling edge of the third clock signal overlaps with an active period of the second clock signal from a falling edge of the second clock signal to a rising edge of the second clock signal.

3. The scan driver of claim 2, wherein the active period of the third clock signal partially overlaps the active period of the second clock signal.

4. The scan driver of claim 1,

the rising edge of the third clock signal lags the falling edge of the first clock signal, and

a falling edge of the third clock signal lags a falling edge of the second clock signal and leads a rising edge of the second clock signal.

5. The scan driver of claim 1, wherein the logic circuit comprises:

an input part transmitting the input signal to a third node in response to the first clock signal;

a stress relaxation section provided between the first node and the third node, the stress relaxation section transmitting the input signal from the third node to the first node so that the voltage of the first node changes to the first low level;

a bootstrap section that changes the voltage of the first node to the second low level by bootstrapping the first node in response to the second clock signal;

a holding section that holds the second node and the fourth node at the high level while the low-level active scan signal and the high-level active scan signal are output; and

a stabilizer part applying a high gate voltage to the third node in response to the voltage of the fourth node after the active low level scan signal and the active high level scan signal are output, and changing the voltage of the second node to the second low level.

6. The scan driver of claim 5, wherein the input section comprises:

a first transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal electrically connected to the third node.

7. The scan driver of claim 5, wherein the bootstrap section comprises:

a first capacitor including a first electrode electrically connected to a first output node at which the active low scan signal is output and a second electrode electrically connected to the first node.

8. The scan driver of claim 5, wherein the stabilizer part comprises:

a second transistor including a gate electrically connected to the fourth node, a first terminal receiving the high gate voltage, and a second terminal electrically connected to the third node;

a second capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the second node;

a third transistor including a gate electrically connected to the second node, a first terminal electrically connected to the fourth node, and a second terminal receiving the second clock signal; and

a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage.

9. The scan driver of claim 5,

each of the plurality of stages receives a fourth clock signal having the high level as the active level and having a phase different from that of the third clock signal, and

the stabilizer section includes: a second transistor including a gate electrically connected to the fourth node, a first terminal receiving the high gate voltage, and a second terminal electrically connected to the third node; a second capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the second node; a third transistor including a gate electrically connected to the second node, a first terminal electrically connected to the fourth node, and a second terminal receiving the fourth clock signal; and a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage.

10. The scan driver of claim 5, wherein the holding part comprises:

a fourth transistor including a gate electrically connected to the third node, a first terminal electrically connected to the second node, and a second terminal receiving the first clock signal; and

a sixth transistor including a gate electrically connected to the third node, a first terminal receiving the high gate voltage, and a second terminal electrically connected to the fourth node.

11. The scan driver of claim 5, wherein the stress relaxation portion comprises:

a seventh transistor comprising a gate that receives a low gate voltage, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node.

12. The scan driver of claim 1, wherein the first output buffer comprises:

an eighth transistor including a gate electrically connected to the first node, a first terminal electrically connected to a first output node at which the active-low scan signal is output, and a second terminal receiving the second clock signal; and

a ninth transistor including a gate electrically connected to the second node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the first output node.

13. The scan driver of claim 1, wherein the second output buffer comprises:

a tenth transistor including a gate electrically connected to the first node, a first terminal electrically connected to a second output node at which the active-high scan signal is output, and a second terminal receiving the third clock signal; and

an eleventh transistor including a gate electrically connected to the second node, a first terminal receiving a low gate voltage, and a second terminal electrically connected to the second output node.

14. A scan driver comprising a plurality of stages, each of the plurality of stages comprising:

a first transistor including a gate receiving a first clock signal, a first terminal receiving an input signal, and a second terminal electrically connected to a third node;

a second transistor including a gate electrically connected to a fourth node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the third node;

a third transistor including a gate electrically connected to a second node, a second terminal, and a first terminal electrically connected to the fourth node;

a fourth transistor including a gate electrically connected to the third node, a first terminal electrically connected to the second node, and a second terminal receiving the first clock signal;

a fifth transistor including a gate receiving the first clock signal, a first terminal electrically connected to the second node, and a second terminal receiving a low gate voltage;

a sixth transistor including a gate electrically connected to the third node, a first terminal receiving the high gate voltage, and a second terminal electrically connected to the fourth node;

a seventh transistor including a gate receiving the low gate voltage, a first terminal electrically connected to the third node, and a second terminal electrically connected to the first node;

a first capacitor including a first electrode electrically connected to a first output node and a second electrode electrically connected to the first node;

an eighth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the first output node, and a second terminal receiving a second clock signal;

a ninth transistor including a gate electrically connected to the second node, a first terminal receiving the high gate voltage, and a second terminal electrically connected to the first output node;

a tenth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the second output node, and a second terminal receiving a third clock signal; and

an eleventh transistor including a gate electrically connected to the second node, a first terminal receiving the low gate voltage, and a second terminal electrically connected to the second output node.

15. The scan driver of claim 14,

the first clock signal and the second clock signal have a low level as an active level and have different phases, and

the third clock signal has a high level as the active level.

16. The scan driver of claim 15, wherein an active period of the third clock signal from a rising edge of the third clock signal to a falling edge of the third clock signal overlaps with an active period of the second clock signal from a falling edge of the second clock signal to a rising edge of the second clock signal.

17. The scan driver of claim 16, wherein the active period of the third clock signal partially overlaps the active period of the second clock signal.

18. The scan driver of claim 15,

19. The scan driver of claim 14, wherein the second terminal of the third transistor receives the second clock signal or a fourth clock signal having a high level as an active level and having a phase different from that of the third clock signal.

20. A display device, the display device comprising:

a display panel including a plurality of pixels;

a data driver supplying data signals to the plurality of pixels;

a scan driver supplying an active low scan signal and an active high scan signal to the plurality of pixels; and

a controller controlling the data driver and the scan driver,

wherein the scan driver includes a plurality of stages receiving first and second clock signals having a first low level as an active level and a third clock signal having a high level as the active level, each of the plurality of stages including: a logic circuit changing a voltage of a first node to the first low level based on an input signal and the first clock signal, and changing the voltage of the first node to a second low level based on the second clock signal, the second low level having a voltage level lower than that of the first low level; a first output buffer outputting the second clock signal as the input signal for a next stage of the plurality of stages in response to the voltage of the first node; and a second output buffer outputting the third clock signal as a corresponding active-high scan signal among the active-high scan signals in response to the voltage of the first node.

21. The display device according to claim 20,

the second clock signal output by the first output buffer is supplied as a corresponding one of the active-low-level scan signals to a corresponding pixel row among the plurality of pixels, and

the plurality of stages sequentially supply the active-low scan signal and the active-high scan signal to the plurality of pixels.

22. The display device according to claim 20,

the scan driver further includes a plurality of P-type stages sequentially supplying the active-low scan signal to the plurality of pixels, and

the plurality of stages sequentially supply the high-level active scan signal to the plurality of pixels.