CN112445525A - Data processing method, related device and computer readable medium - Google Patents
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Abstract
The embodiment of the invention discloses a data processing method, related equipment and a computer readable medium, wherein the computing equipment in the related equipment comprises the following steps: the system comprises a processor, a memory and a bus, wherein the processor is connected with the memory through the bus, the memory is used for storing instructions, and the processor is used for calling the instructions stored in the memory and executing a specific data processing method so as to improve the data processing performance and efficiency.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data processing method, a related device, and a computer-readable medium.
Background
In the field of chip technology, a Central Processing Unit (CPU) has great programming flexibility and complex logic processing capability. A Graphics Processing Unit (GPU) is mainly responsible for operations. In practical applications, data processing is often completed by combining a CPU and a GPU, where the CPU is responsible for logic control during processing and the GPU is responsible for actual data operations.
For an Artificial Intelligence (AI) chip, flexibility of a CPU cannot be achieved in terms of logic control. Moreover, since the AI chip frequently interacts with the CPU to degrade the performance of the AI chip, the AI chip cannot adopt the CPU to implement logic control as the GPU does in view of the performance problem of the AI chip. Currently, an AI chip usually employs a register to configure instructions to implement data processing. However, in practice, it is found that a large number of scalar instructions are generated and stored in the register configuration instruction, which wastes chip resources and affects chip performance.
Disclosure of Invention
The embodiment of the invention provides a data processing method which can realize splicing and operation of data blocks to be spliced by combining dynamic control and static operation and improve the data processing efficiency.
In a first aspect, an embodiment of the present invention provides a data processing method, where the method includes: the computing device may obtain a dynamic control instruction, the dynamic control instruction carrying a size H x W of the data block to be pieced together; and selecting a template data block for the data block to be spliced according to the dynamic control instruction, wherein the template data block is used for realizing splicing of the data block to be spliced. The computing device can obtain the static operation instruction associated with the template data block, and execute the operation indicated by the static operation instruction on the template data block to obtain the operation result of the data block to be pieced together.
By implementing the embodiment of the invention, the splicing and the operation of the data blocks to be spliced can be comprehensively realized by combining the dynamic control instruction and the static operation instruction, so that the method is suitable for the operation on the corresponding core in the computing equipment, thereby improving the data processing efficiency, saving the computing resources and avoiding the problem of core resource waste.
With reference to the first aspect, in some possible embodiments, the template data block includes n sub-data blocks. The computing device may sequentially perform the operation indicated by the static operation instruction on n sub-data blocks in the template data block to obtain n sub-block results; and further, address offset can be carried out on the n sub-block results so as to realize storage of the n sub-block results. The n sub-block results form the operation data corresponding to the template data block.
With reference to the first aspect, in some possible embodiments, the computing device may determine an address offset of the template data block with respect to the data block to be pieced, where the address offset is used to indicate a splicing position where the template data block is located with respect to the data block to be pieced. Further, the operation indicated by the static operation instruction is performed on the template data block according to the address offset.
In some possible embodiments, in combination with the first aspect, the computing device may store context information associated with the dynamic control instruction, the context information including a size of the template data block and a size of the data block to be pieced together.
With reference to the first aspect, in some possible embodiments, the computing device may select, according to the dynamic control instruction, a template data chunk for a data chunk to be pieced together from a static data chunk library, where the static data chunk library includes at least one preset sample data chunk, and the template data chunk is a data chunk in the at least one sample data chunk.
In a second aspect, an embodiment of the present invention provides a computing device, which includes means for performing the method of the first aspect.
In a third aspect, an embodiment of the present invention provides another computing device, including a processor, a memory, and a bus, where the processor and the memory are connected through the bus, the memory is used to store an instruction, and the processor is used to call the instruction stored in the memory, so as to execute the method of the first aspect.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program is stored, the computer program comprising program instructions, which, when executed by a processor, cause the processor to perform the method of the first aspect.
By implementing the embodiment of the invention, the splicing and the operation of the data blocks to be spliced can be realized by combining the dynamic control and the static operation, thereby improving the performance and the efficiency of data processing.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a data processing method according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a computing device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The application provides a data processing method combining dynamic control and static operation and related equipment applicable to the method for adapting to the operation of data blocks with different scales. Fig. 1 is a schematic flow chart of a data processing method according to an embodiment of the present invention. The data processing method shown in fig. 1 may specifically include the following implementation steps:
step S101, the computing device obtains a dynamic control instruction, where the dynamic control instruction carries a size H × W of the data block to be pieced together.
In the initial operation stage, the computing device may initialize relevant information of the data to be processed, where the relevant information includes, but is not limited to, an input address and an output address of the data to be processed, and parameters of a relevant operator involved in processing the data to be processed, such as a convolution kernel parameter that needs to be used by a convolution operator, and the like, and the invention is not limited thereto. The data to be processed is data to be processed set by the system in a user-defined manner, and in practical application, the data to be processed may also be data blocks to be processed, such as data blocks to be pieced together and the like described below.
Alternatively, information of the data blocks to be pieced together (specifically, the data blocks to be processed) may be stored in corresponding registers. For example, the height H and the width W to which the size H × W of the data block to be pieced relates may be stored in a height register and a width register, respectively. During initialization, the computing device needs to initialize the corresponding height register and width register in advance to clear the information stored in each register.
In order to avoid the problems of chip resource waste, chip performance influence and the like caused by a large number of scalar instructions generated in the conventional data processing scheme, the method adopts two types of instructions, namely a dynamic control instruction and a static operation instruction to perform operation processing on data blocks with different scales in batches. The following description of the present application takes the data block to be pieced together with size H × W as an example.
And S102, selecting a template data block for the data block to be spliced by the computing equipment according to the dynamic control instruction, wherein the template data block is used for realizing splicing of the data block to be spliced.
In the actual operation process, after the computing device obtains the dynamic control instruction, the computing device may obtain the relevant information of the data block to be pieced, such as the size H × W of the data block to be pieced, the input address of the data block to be pieced, and the like, according to the dynamic control instruction. And then splitting the data blocks to be spliced to select proper template data blocks for splicing the data blocks to be spliced, wherein the number of the template data blocks is not limited and can be one or more.
In practical applications, the computing device may select a template data block for the data block to be pieced from the static data block library according to the size H × W of the data block to be pieced. Specifically, the computing device may select a template data chunk for the data chunk to be pieced from a static data chunk library along a height direction and a width direction of the data chunk to be pieced, where the static data chunk library includes one or more preset sample data chunks, and the template data chunk is a data chunk in the sample data chunks. The specific form of the static database is not limited, and for example, it may be embodied in the form of a table or in the form of text txt.
Step S103, the computing equipment acquires a static operation instruction associated with the template data block, and executes the operation indicated by the static operation instruction on the template data block to obtain an operation result of the data block to be spliced.
According to the method and the device, the dynamic control instruction and the static operation instruction are combined and interacted with each other to realize the operation of the data block to be spliced, so that in the static operation process, the computing device needs to transmit the relevant parameters related to the dynamic control instruction to the static operation instruction to realize the static operation of the corresponding data block. For example, after selecting a template data block for the data block to be pieced together according to the dynamic control instruction, the computing device may obtain a static operation instruction associated with the template data block, where the static operation instruction is used to instruct a corresponding operation, such as a multiplication operation, a convolution operation, and the like, to be performed on the template data block to obtain an operation result of the template data block. After the operation of the template data block is completed, the process returns to step S102 to select a next template data block for the data block to be pieced together along the height and width directions of the data block to be pieced together, and the static operation of the next template data block is realized with reference to step S103 until the static operation of all the template data blocks constituting the data block to be pieced together is completed, so as to obtain the operation result of the data block to be pieced together.
The following description of the related contents is made by taking a template data block as an example. In the static operation process, after the computing equipment selects the template data block for the data block to be spliced according to the dynamic control instruction, the parameters of the template data block can be sent to the corresponding static operation instruction. And the computing equipment executes the operation indicated by the static operation instruction on the template data block according to the static operation instruction so as to obtain an operation result corresponding to the template data block. Specifically, after obtaining the template data block, the computing device may prepare a running environment for the template data block, for example, determine an address offset of the template data block with respect to the data block to be spliced, where the address offset is used to indicate a splicing position where the template data block is located with respect to the data block to be spliced, further call the template data block according to the address offset, and perform an operation indicated by the static operation instruction on the template data block to obtain an operation result of the template data block.
The parameters of the template data block include, but are not limited to, specific values of the template data block, a size of the template data block, an input address of the template data block, an output address of the template data block corresponding to the operation result, or other parameters set by a user.
Alternatively, after receiving the parameters of the template data block, the computing device may store the parameters in a corresponding register for backup. After the computing device selects one template data block for each data block to be pieced, the computing device may correspondingly update registers related to the data block to be pieced, for example, the height H of the data block to be pieced stored in the corresponding update height register and the width W of the data block to be pieced stored in the width register.
Optionally, the computing device may initialize relevant information related to the static operation instruction before performing the operation indicated by the static operation instruction, where the relevant information includes, but is not limited to, an input address and an output address of the data block, and the like.
Taking the operation indicated by the static operation instruction as the convolution operation as an example, after the computing device obtains the template data block, the computing device can obtain the pre-stored weight data block, and perform the convolution operation on the weight data block and the template data block according to the static operation instruction. In this example, taking the example that the size (i.e. the scale size) of the template data block is larger than the size of the weight data block, in practical application, the computing device may perform sliding convolution on the template data block by using the weight data block to implement convolution operation of the template data block. For example, in the sliding convolution process, the computing device divides the template data block into n sub-data blocks, and then may sequentially perform convolution operation on the n sub-databases using the weight data block, so as to obtain n sub-block results, that is, operation results corresponding to the template data block. Specifically, when the computing device detects that the processing of the entire template data block is not currently completed (in this example, the convolution operation of n sub-data blocks is completed), the computing device may load the sub-data block that needs to be currently processed, so as to perform the convolution operation on the sub-data block by using the weight data block, and obtain the corresponding sub-block result. Accordingly, after the computing device has completed processing the entire template data block, the process may be ended or the loop may be skipped to select the next template data block, which is not limited in the present application. After obtaining the n sub-block results, the computing device may perform address offset on the n sub-block results, and determine a respective storage address or offset address of each sub-block result, so as to implement storage of the n sub-block results.
In an alternative embodiment, the computing device may employ an on-chip storage area as a storage medium, and the computing device may store the relevant parameters related to the dynamic control instructions and/or the static operation instructions on the storage medium. For example, in the above of the present application, the computing device may store information (e.g., size, input address, etc.) of the weight data block or the template data block related to the static operation instruction in the storage medium, so as to be called when the static operation instruction is executed. Optionally, before executing/calling the static operation instruction, the computing device further needs to store context information related to the dynamic control instruction, where the context information may include, but is not limited to, a size of the data block to be pieced, an input address of the data block to be pieced, a size of the template data block, an input address and an output address of the template data block, and the like.
The computing device related to the present invention includes, but is not limited to, a chip (e.g., an AI chip), a smart phone (e.g., an Android phone, an IOS phone, etc.), a personal computer, a tablet computer, a palm computer, a Mobile Internet device (MID, Mobile Internet Devices), or a wearable smart device, and the embodiments of the present invention are not limited thereto.
By implementing the embodiment of the invention, dynamic control and static operation can be integrated in the same chip (computing device) to realize the operation processing of the data block with variable size. Compared with the prior art, the problems of chip resource waste, influence on chip performance and the like caused by the fact that a large number of scalar instructions are used for completing data processing can be solved, and therefore data processing efficiency and performance can be improved.
Fig. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention. The data processing apparatus 200 shown in fig. 2 may include an acquisition module 202, a selection module 204, and an operation module 206. Wherein the content of the first and second substances,
the obtaining module 202 is configured to obtain a dynamic control instruction, where the dynamic control instruction carries a size H × W of a data block to be spliced;
the selecting module 204 is configured to select a template data block for the data block to be spliced according to the dynamic control instruction, where the template data block is used to splice the data blocks to be spliced;
the obtaining module 202 is further configured to obtain a static operation instruction associated with the template data block;
the operation module 206 is configured to perform the operation indicated by the static operation instruction on the template data block to obtain an operation result of the data block to be pieced together.
In some possible embodiments, the template data block comprises n sub-data blocks. The operation module 206 is specifically configured to sequentially perform operations indicated by the static operation instruction on n sub-data blocks in the template data block to obtain n sub-block results; and performing address offset on the n sub-block results to realize storage of the n sub-block results.
In some possible embodiments, the operation module 206 is specifically configured to determine an address offset of the template data block with respect to the data block to be spliced, where the address offset is used to indicate a splicing position of the template data block with respect to the data block to be spliced; and executing the operation indicated by the static operation instruction on the template data block according to the address offset.
In some possible embodiments, the data processing apparatus 200 further comprises a saving module 208. The saving module 208 is configured to save context information associated with the dynamic control instruction, where the context information includes a size of the template data block and a size of the data block to be spliced.
In some possible embodiments, the selecting module 204 is specifically configured to select, according to the dynamic control instruction, a template data chunk for a data chunk to be pieced together from a static data chunk library, where the static data chunk library includes at least one preset sample data chunk, and the template data chunk is a data chunk in the at least one sample data chunk.
Optionally, the computing device 200 further comprises a storage module (not shown) storing program code for implementing the relevant operations of the computing device 200. In practical applications, the modules or units involved in the computing device in the embodiments of the present invention may be specifically implemented by software programs or hardware. When implemented by a software program, each module or unit related to the computing device is a software module or a software unit, and when implemented by hardware, each module or unit related to the computing device may be implemented by an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD), where the PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof, and the present invention is not limited thereto.
It should be noted that fig. 2 is only one possible implementation manner of the embodiment of the present application, and in practical applications, more or less components may be included in the computing device, which is not limited herein. For the content that is not shown or described in the embodiment of the present invention, reference may be made to the relevant explanation in the foregoing method embodiment, which is not described herein again.
Fig. 3 is a schematic structural diagram of a computing device according to an embodiment of the present invention. The computing device 300 shown in fig. 3 includes one or more processors 301, a communication interface 302, and a memory 303, and the processors 301, the communication interface 302, and the memory 303 may be connected by a bus, and may also implement communication by other means such as wireless transmission. The embodiment of the present invention is exemplified by being connected through a bus 304, wherein the memory 303 is used for storing instructions, and the processor 301 is used for executing the instructions stored by the memory 303. The memory 303 stores program code, and the processor 301 may call the program code stored in the memory 303 to perform the following operations:
acquiring a dynamic control instruction, wherein the dynamic control instruction carries the size H x W of a data block to be spliced;
selecting a template data block for the data block to be spliced according to the dynamic control instruction, wherein the template data block is used for realizing splicing of the data block to be spliced;
and acquiring a static operation instruction associated with the template data block, and executing the operation indicated by the static operation instruction on the template data block to obtain an operation result of the data block to be spliced.
For the content that is not shown or not described in the embodiment of the present invention, reference may be made to the related explanation in the embodiment described in fig. 1 or fig. 2, which is not described herein again.
It should be understood that, in the embodiment of the present invention, the Processor 301 may be a Central Processing Unit (CPU), and the Processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The communication interface 302 may be a wired interface (e.g., an ethernet interface) or a wireless interface (e.g., a cellular network interface or using a wireless local area network interface) for communicating with other modules or equipment devices. For example, in the embodiment of the present application, the communication interface 302 may be specifically used to obtain a dynamic control instruction or a static operation instruction.
It should be noted that fig. 3 is only one possible implementation manner of the embodiment of the present invention, and in practical applications, the computing device may further include more or less components, which is not limited herein. For the content that is not shown or described in the embodiment of the present invention, reference may be made to the relevant explanation in the foregoing method embodiment, which is not described herein again.
Embodiments of the present invention also provide a computer-readable storage medium, which stores instructions that, when executed on a processor, implement the method flow shown in fig. 1.
Embodiments of the present invention further provide a computer program product, where when the computer program product runs on a processor, the method flow shown in the embodiment of fig. 1 is implemented.
The computer readable storage medium may be an internal storage unit of the computing device according to any of the foregoing embodiments, for example, a hard disk or a memory of the computing device. The computer readable storage medium may also be an external storage device of the computing device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), etc. provided on the computing device. Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the client. The computer-readable storage medium is used for storing the computer program and other programs and data required by the computing device. The computer readable storage medium may also be used to temporarily store data that has been output or is to be output.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the terminal device and the unit described above may refer to corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed terminal device and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A method of data processing, the method comprising:
acquiring a dynamic control instruction, wherein the dynamic control instruction carries the size H x W of a data block to be spliced;
selecting a template data block for the data block to be spliced according to the dynamic control instruction, wherein the template data block is used for realizing splicing of the data block to be spliced;
and acquiring a static operation instruction associated with the template data block, and executing the operation indicated by the static operation instruction on the template data block to obtain an operation result of the data block to be spliced.
2. The method of claim 1, wherein the template data block comprises n sub-data blocks, and wherein performing the operation indicated by the static operation instruction on the template data block to obtain an operation result comprises:
sequentially executing the operation indicated by the static operation instruction on n sub-data blocks in the template data block to obtain n sub-block results;
and performing address offset on the n sub-block results to realize the storage of the n sub-block results.
3. The method of claim 1, wherein performing the operation indicated by the static operation instruction on the template data block comprises:
determining an address offset of the template data block for the data block to be spliced, wherein the address offset is used for indicating a splicing position of the template data block relative to the data block to be spliced;
and executing the operation indicated by the static operation instruction on the template data block according to the address offset.
4. The method of claim 1, wherein prior to obtaining the static operation instruction associated with the template data block, the method further comprises:
and saving context information associated with the dynamic control instruction, wherein the context information comprises the size of the template data block and the size of the data block to be spliced.
5. The method according to any one of claims 1 to 4, wherein the selecting a template data block for the data block to be spliced according to the dynamic control instruction comprises:
and selecting a template data block for the data block to be spliced from a static data block library according to the dynamic control instruction, wherein the static data block library comprises at least one preset sample data block, and the template data block is a data block in the at least one sample data block.
6. A data processing device is characterized by comprising an acquisition module, a selection module and an operation module, wherein,
the acquisition module is used for acquiring a dynamic control instruction, and the dynamic control instruction carries the size H x W of a data block to be spliced;
the selection module is used for selecting a template data block for the data block to be spliced according to the dynamic control instruction, and the template data block is used for realizing splicing of the data block to be spliced;
the obtaining module is further configured to obtain a static operation instruction associated with the template data block;
the operation module is used for executing the operation indicated by the static operation instruction on the template data block so as to obtain an operation result of the data block to be spliced.
7. The apparatus of claim 6, wherein the template data block comprises n sub-data blocks,
the operation module is specifically configured to sequentially perform operations indicated by the static operation instruction on n sub-data blocks in the template data block to obtain n sub-block results; and performing address offset on the n sub-block results to realize the storage of the n sub-block results.
8. The apparatus of claim 6,
the operation module is specifically configured to determine an address offset of the template data block with respect to the data block to be spliced, where the address offset is used to indicate a splicing position of the template data block with respect to the data block to be spliced; and executing the operation indicated by the static operation instruction on the template data block according to the address offset.
9. The apparatus of claim 6, further comprising a save module,
the storage module is configured to store context information associated with the dynamic control instruction, where the context information includes a size of the template data block and a size of the data block to be spliced.
10. The apparatus according to any one of claims 6-9,
the selecting module is specifically configured to select, according to the dynamic control instruction, a template data block for the data block to be spliced from a static data block library, where the static data block library includes at least one preset sample data block, and the template data block is a data block in the at least one sample data block.
11. A computing device comprising a processor, a memory, and a bus, the processor and the memory being connected by the bus, the memory for storing instructions, the processor for invoking the instructions stored in the memory for performing the method of any of claims 1-5 above.
12. A computer-readable storage medium, characterized in that the computer storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method according to any of claims 1-5.
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| CN201910830238.XA CN112445525A (en) | 2019-09-02 | 2019-09-02 | Data processing method, related device and computer readable medium |
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