CN112445520B

CN112445520B - Branch prediction optimization method for conditional branch instructions in loop

Info

Publication number: CN112445520B
Application number: CN201910794939.2A
Authority: CN
Inventors: 钱宏; 朱琪; 王飞; 吴伟; 肖谦; 管茂林; 沈莉; 周文浩
Original assignee: Wuxi Jiangnan Computing Technology Institute
Current assignee: Wuxi Jiangnan Computing Technology Institute
Priority date: 2019-08-27
Filing date: 2019-08-27
Publication date: 2022-11-15
Anticipated expiration: 2039-08-27
Also published as: CN112445520A

Abstract

The invention discloses a branch prediction optimization method for a conditional branch instruction in a loop, which comprises the following steps: s11, judging whether the number of instruction strips in a cycle can meet the condition that at least N instructions are advanced before the conditional branch instruction with the conditional branch flag bit of the operation instruction with the conditional branch flag bit; s12, if the condition is met, the compiler directly generates the assembly code, and if the condition is not met, the compiler calculates the number of times of loop expansion according to the loop body code quantity and the condition N, and performs loop expansion to generate the assembly code; s13, the operation instruction with the conditional tag changes the branch flag bit of the conditional branch instruction in advance; s14, judging the conditional branch instruction according to the corresponding conditional flag bit, if so, indicating, by the processor, skipping to fetch the instruction according to the conditional branch flag, otherwise, sequentially fetching the instruction; s15, whether the jump is predicted or not, the condition marking bit is used and then is invalidated, and the branch instruction condition marking bit is clear 0. The invention can avoid the performance loss caused by the last transfer of the cycle.

Description

Branch prediction optimization method for conditional branch instructions in loops

Technical Field

The invention relates to a branch prediction optimization method for a conditional branch instruction in a loop, and belongs to the technical field of computers.

Background

Performance of the processor is often limited by the branch instruction because many cycles are lost by the need to drain the pipeline of invalid instructions following the branch instruction when the branch occurs to fetch the instruction from a new target address. Branch prediction is an effective method to overcome this loss, and the success rate of branch prediction is critical to improving the performance of the processor.

Branch prediction mechanisms can be divided into static branch prediction and dynamic branch prediction. Static branch prediction is irrelevant to the execution result of the branch, does not need history, is simple to realize, and can be divided into compiler prediction and hardware fixed prediction. Dynamic branch prediction is divided into primary branch prediction, secondary adaptive branch prediction and hybrid prediction, and the accuracy is much higher than that of static branch prediction.

For a loop executing n times, the existing branch prediction technology can successfully predict the jump direction of the previous n-1 loops, but cannot predict the last branch when the nth loop ends, that is, the branch prediction always fails when the loop ends and jumps out of the loop, which causes a certain loss to the performance of program operation.

Disclosure of Invention

The invention aims to provide a branch prediction optimization method for a conditional branch instruction in a loop, which achieves the purpose of avoiding the performance loss caused by the failure of the branch prediction and can avoid the performance loss caused by the last branch of the loop.

In order to achieve the purpose, the invention adopts the technical scheme that: a method of branch prediction optimization for an in-loop conditional branch instruction, comprising the steps of:

s11, a compiler processes a for loop in a user program, and judges whether the number of instruction in a loop can meet the condition that at least N instructions are advanced before a conditional branch instruction with a conditional branch flag bit of an operation instruction with a conditional branch flag bit;

s12, the compiler generates an operation instruction with a conditional branch flag bit and a conditional branch instruction with a conditional branch flag bit, if the number of instruction in a cycle is satisfied, whether the instruction can satisfy the condition that the operation instruction with the conditional branch flag bit is advanced by at least N, the compiler directly generates an assembly code, and if the instruction cannot satisfy the condition, the compiler calculates the number of times of loop expansion according to the code amount of a loop body and the condition N, and performs loop expansion to generate the assembly code;

s13, in the program running stage, the operation instruction with the conditional branch instruction changes the branch flag bit of the conditional branch instruction in advance, namely the operation instruction with the conditional branch instruction is valid when the conditional branch flag bit is set, and a corresponding conditional branch flag is set according to the operation result;

s14, judging the conditional branch instruction according to the corresponding conditional flag bit, if so, indicating, by the processor, skipping to fetch the instruction according to the conditional branch flag, otherwise, sequentially fetching the instruction;

s15, whether the jump is predicted or not, the condition marking bit is used and then is invalidated, and the branch instruction condition marking bit is clear 0.

The further improved scheme in the technical scheme is as follows:

1. in the above scheme, N is determined by hardware, and N is an integer.

Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:

the invention relates to a branch prediction optimization method for a conditional branch instruction in a loop, which combines an operation instruction with a conditional tag provided by a processor and the conditional branch instruction with a conditional branch flag bit, so that the branch direction can be correctly predicted when the loop is jumped out of the loop after the loop is ended, thereby achieving the purpose of avoiding the performance loss caused by the branch prediction failure and avoiding the performance loss caused by the last branch of the loop.

Drawings

FIG. 1 is a flow diagram of a method for branch prediction optimization for an in-loop conditional branch instruction according to the present invention.

Detailed Description

The embodiment is as follows: a method of branch prediction optimization for an in-loop conditional branch instruction, comprising the steps of:

s12, the compiler generates an operation instruction with a condition mark and a conditional branch instruction with a condition branch zone bit, if the number of instructions in a loop is satisfied, the compiler directly generates an assembly code if the number of the instructions in the loop can satisfy the condition that the operation instruction with the condition mark is at least N ahead of the conditional branch instruction with the condition branch zone bit, and if the number of the instructions in the loop is not satisfied, the compiler calculates the number of times of loop expansion according to the code amount of the loop body and the condition N, performs loop expansion and generates the assembly code;

s14, judging the conditional branch instruction according to the corresponding conditional flag bit, if so, indicating skip instruction fetching by the processor according to the conditional branch flag, otherwise, sequentially fetching the instruction;

The N is determined by hardware and is an integer, the jump direction of the conditional branch is calculated by using an operation instruction with a conditional tag, in order to ensure that the branch prediction is successful, the position of the instruction is ahead of the conditional branch instruction, and how many instructions ahead are related to the pipeline stage number of the processor.

The examples are further explained below:

the compiler processes for loop in the program, the generated assembly code uses processor provided operation instruction with conditional branch flag bit and conditional branch instruction with conditional branch flag bit, during the program running, the operation instruction with conditional branch flag bit is changed in advance, the processor fetches instruction according to the branch flag bit of the conditional branch instruction.

It should be noted that, in order for the branch flag bit to function correctly, the conditional tagged instruction needs to be advanced by at least N before the conditional branch instruction, which leaves a cycle for the processor to handle the branch flag and fetch, and the specific value of N depends on the hardware implementation. The compiler needs to consider the condition when generating the assembly code, and for the condition that the condition cannot be met because the number of instructions in one loop is small, the compiler adopts a loop expansion strategy to enable the instruction generation to meet the condition.

The invention provides a branch prediction optimization method aiming at a conditional branch instruction in a loop, which comprises the following specific processes:

and S11, processing a for loop in the user program by the compiler.

Specifically, the compiler processes the for loop in the user program and judges whether the number of instructions in one loop can meet the condition that the operation instruction with the conditional flag is advanced by at least N before the conditional branch instruction.

And S12, the compiler generates an operation instruction with a conditional tag and a conditional branch instruction with a conditional branch flag bit.

Specifically, for the case where the above condition can be satisfied, the compiler directly generates assembly code; and for the condition that the condition is not met, the compiler adopts a loop expansion strategy, calculates the times of loop expansion according to the loop body code quantity and the condition N, and generates the assembly code.

And S13, in the program running stage, the operation instruction with the condition mark changes the branch flag bit of the conditional branch instruction in advance.

Specifically, the operation instruction with conditional tag is valid in the condition tag bit, and the corresponding conditional branch tag is set according to the operation result.

And S14, the processor indicates to fetch the instruction according to the condition transfer mark.

Specifically, the conditional branch instruction is judged according to the corresponding conditional flag bit, if yes, the instruction fetching is skipped, otherwise, the instruction fetching is performed sequentially.

And step S15, marking the bit clear 0 by the branch instruction condition.

Specifically, the conditional flag bit is invalidated after use, regardless of whether a jump or no jump is predicted.

When the branch prediction optimization method for the conditional branch instruction in the loop is adopted, the operation instruction with the conditional label provided by the processor and the conditional branch instruction with the conditional branch flag bit are combined, so that the branch direction can be correctly predicted when the loop is jumped out of the loop after the loop is ended, the purpose of avoiding the performance loss caused by the branch prediction failure is achieved, and the performance loss caused by the last branch of the loop can be avoided.

To facilitate a better understanding of the invention, the terms used herein will be briefly explained as follows:

processor pipeline: the method is a technology for decomposing an instruction into multiple steps and overlapping the operations of the steps of different instructions so as to realize parallel processing of a plurality of instructions and accelerate the program running process.

A conditional branch instruction: and taking the state of the flag bit or the logic operation result of the flag bit as a basis, if the branch condition is met, switching to the instruction execution indicated by the target address, and otherwise, continuing to execute the next instruction.

And (3) branch prediction: an advanced data processing method for solving the problem of pipeline failure caused by processing branch instructions, a processor predicts the proceeding direction of program branches and can accelerate the operation speed;

a compiler: a program that translates one language (typically a high level language) into another language (typically a low level language).

The above embodiments are only for illustrating the technical idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention, and not to limit the protection scope of the present invention by this means. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method of branch prediction optimization for an in-loop conditional branch instruction, comprising: the method comprises the following steps:

s11, a compiler processes a for loop in a user program, and judges whether the number of instructions in a loop can meet the requirement that whether an operation instruction with a conditional branch flag bit can be preceded by at least N instructions in advance so as to meet the condition that branch prediction prompts success;

s12, on the basis of the judgment result of the S11, the compiler generates an operation instruction with a condition mark and a conditional branch instruction with a condition branch flag bit, if the number of instruction strips in a cycle can meet the condition that the operation instruction with the condition mark is at least N strips ahead of the conditional branch instruction with the condition branch flag bit, the compiler directly generates an assembly code, and if the number of instruction strips in the cycle can not meet the condition, the compiler calculates the number of times of cycle expansion according to the code amount of a cycle body and the condition N strips, and performs cycle expansion to generate the assembly code;

2. The method of claim 1 for branch prediction optimization for an in-loop conditional branch instruction, wherein: the N is determined by hardware and is an integer.