CN112433504A

CN112433504A - Combined type BACnet controller

Info

Publication number: CN112433504A
Application number: CN202110033914.8A
Authority: CN
Inventors: 张青; 周建东; 董世运; 蒋伟; 马俊杰
Original assignee: Suzhou Hexinzhiyuan Energy Saving Technology Co ltd
Current assignee: Suzhou Hexinzhiyuan Energy Saving Technology Co ltd
Priority date: 2021-01-12
Filing date: 2021-01-12
Publication date: 2021-03-02

Abstract

The invention discloses a composite BACnet controller, which is characterized in that a host and a plurality of slave machines are arranged on an internal bus, and the plurality of slave machines are hung on the internal bus in a serial bus installation mode; the host comprises a single chip microcomputer, a nonvolatile memory and a host power supply conversion circuit, wherein the single chip microcomputer is connected with an interface for realizing BACnet communication and a host 485 interface for connecting the internal bus; the slave comprises a microprocessor, the microprocessor is connected with an analog input channel, a switching value input channel, an analog output channel, a switching value output channel, a slave 485 interface used for connecting the internal bus, and a slave power supply conversion circuit. The controller can realize the technical effect of logic centralized control point dispersion.

Description

Combined type BACnet controller

Technical Field

The invention belongs to the field of building automatic control systems, and particularly relates to a BACnet controller.

Background

The building automatic control system is an important component of an intelligent building and is also a whole set of automatic control system formed by combining an advanced computer technology and a network communication technology.

In the building automatic control field, a DDC controller based on a BACnet communication protocol is dominant. Such a controller has the following features: A. BACnet MSTP is used as a main communication port; B. support various services and objects of BACnet; C. downloading and uploading a logic file through a BACnet file service; D. running the programmable logic file; E. the device comprises an analog quantity input, a switching quantity input, an analog quantity output and a switching quantity output (also a relay output); F. the number of input and output points is limited, and 1-2 controllers generally control one unit electromechanical device; G. the controllers can transmit data through network variables, but the internal resources of the chip and the MSTP bus time are consumed more.

The DDC controller based on the BACnet communication protocol in the building automatic control system is more suitable for controlling electromechanical equipment with less points, such as a fresh air handling unit, an air conditioning unit, water supply and drainage, a sump and the like. However, the control of a large-scale unit such as a freezing station is difficult to deal with because of a plurality of control points, control logic needs to be written in a centralized manner but the space distribution of equipment is not centralized (generally, a refrigerator is underground and a cooling tower is on the top of a building), a plurality of DDC controllers do not know which is the core, a main logic program runs in which controller, and a large number of network variables need to be transmitted back and forth, which brings great difficulty to programming and debugging, and is difficult to deal with various fault-tolerant problems and faces a large number of hidden program defects.

The other scheme is to use PLC control. The PLC is a combination of a main module and a plurality of IO extension modules, only the main module can be programmed, and troubles of programming and network variables can be avoided. However, PLC has 2 drawbacks: 1. the slave machine carried by each host machine is expanded by a parallel bus and cannot be dispersedly installed, so that one additional slave machine is required to be additionally arranged for controlling the cooling tower; 2. the building automatic control system is not provided with a BACnet data interface, does not support a BACnet standard protocol, and means that a technical system is not unified with the whole building automatic control system, is not fused, and is troublesome in debugging and maintenance.

Disclosure of Invention

In order to solve the problems in the prior art, the invention aims to provide a composite BACnet controller which can realize the technical effect of logic centralized control point dispersion.

In order to achieve the technical purpose and achieve the technical effect, the invention is realized by the following technical scheme:

a compound BACnet controller is provided with a host and a plurality of slaves on an internal bus, and the slaves are hung on the internal bus in a serial bus installation mode; the host comprises a single chip microcomputer, the single chip microcomputer (101) is connected with an interface for realizing BACnet communication and a host 485 interface for connecting the internal bus, and further comprises a nonvolatile memory and a host power supply conversion circuit, wherein the nonvolatile memory and the host power supply conversion circuit are respectively connected with the single chip microcomputer, the interface for realizing BACnet communication and the host 485 interface; the slave comprises a microprocessor, the microprocessor is connected with an analog input channel, a switching value input channel, an analog output channel, a switching value output channel and a slave 485 interface used for connecting the internal bus, and the slave also comprises a slave power supply conversion circuit, and the slave power supply conversion circuit is respectively connected with the microprocessor, the analog input channel, the switching value input channel, the analog output channel, the switching value output channel and the slave 485 interface.

Further, the interface for realizing BACnet communication includes one or both of an ethernet interface for realizing BACnet IP communication and an RS485 interface for realizing BACnet MSTP communication.

The analog output channel comprises an analog-to-digital conversion chip, the microprocessor controls the output of the analog-to-digital conversion chip through 12C or SPI serial communication, the analog-to-digital conversion chip is connected with a signal amplifier, and a voltage signal output by the analog-to-digital conversion chip is converted into a 4-20mA current or a 0-10V voltage signal through the signal amplifier.

The switching value output channel comprises a latch, and the latch is connected with a plurality of relays.

In the actual operation process, due to external electromagnetic interference or internal data disorder and the like, abnormal reset may occur in both the master and the slave. In the absence of a reliable design, the two abnormal resets can cause the output signal to be out of control, and further damage the stable operation of the controlled equipment.

In most building control systems, the system is in a stable state under the condition that the output of the relay and the output of the analog quantity are kept unchanged, so the reliability design principle provided by the invention is as follows: a, setting a certain time window, wherein in the window, the operation result of a logic program is possibly unreasonable, but the actual output of a controller is kept unchanged before resetting; and B, after the time window is passed, the logic program is operated and restored to a reasonable state, and the controller executes the operation result.

Combining the design of the BACnet controller, when the host is reset, the host sets a reset time window, and the task of the host is to recover data from the nonvolatile memory device A in the reset time window; B. the logic program enters a recovery running state; C. the slave still keeps reading the physical channel; D. reading necessary data from an external device; E. stopping sending data and commands to the external device; F. the sending of commands to the slave is stopped. The reset window period ends and all data returns to normal E, F.

The length of the reset time window is generally fixed time which can be set manually, and can also be judged by program logic, and a user can judge whether to enter a stable operation period by programming according to collected information.

The slave is abnormally reset, the output of analog quantity and switching value signals is automatically latched and unchanged before the program is restored to be normal, and the host command is restored to be executed after the normal operation is carried out. The latch time of the slave is much shorter than that of the master.

The invention has the following beneficial effects:

1. the invention is constructed by hanging a host and a plurality of slave machines on an internal bus, and the slave machines are installed by a serial bus and can be installed dispersedly, thereby realizing the requirements of 'logic concentration and control point dispersion' of the refrigeration station.

2. The host of the invention is the core of the whole BACnet controller, and has the upper layer functions of the general BACnet controller:

A. support BACnet communication protocol, MSTP and IP, have one of them at least;

B. the logic file can be downloaded and uploaded through the file service in the BACnet protocol;

C. executing a logical operation function;

D. storing a configuration file of a slave machine physical channel;

E. and converting the original information of the input channel read from the slave into physical data which can be understood by a user according to the configuration information, and converting the physical data of the output channel into original information which can be executed by the slave.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings. The detailed description of the present invention is given in detail by the following examples and the accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings;

FIG. 1 is a system architecture diagram of the present invention.

FIG. 2 is a system framework diagram of the host of the present invention.

Fig. 3 is a system framework diagram of the slave of the present invention.

Fig. 4 is a schematic diagram of a switching value output channel system of the slave of the invention.

FIG. 5 is a schematic diagram of the analog output channel system of the slave of the present invention.

Fig. 6 shows a communication relationship between a master and a slave according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 1, a composite BACnet controller is provided with a master 1 and a plurality of slaves 2 on an internal bus 3, and the slaves 2 are hung on the internal bus 3 by a serial bus installation method.

As shown in fig. 2, the host 1 includes a single chip microcomputer 101, the single chip microcomputer 101 is connected to the ethernet interface (102) for implementing BACnet IP communication, an RS485 interface 103 for implementing BACnet MSTP communication, and a host 485 interface 104 for connecting the internal bus, and further includes a nonvolatile memory 105 and a host power conversion circuit 106, and the nonvolatile memory 105 and the host power conversion circuit 106 are respectively connected to the single chip microcomputer 101, the ethernet interface 102, the RS485 interface 103, and the host 485 interface 104.

As shown in fig. 3, the slave 2 includes a microprocessor 201, the microprocessor 201 is connected to an analog input channel 204, a switching input channel 205, an analog output channel 206, a switching output channel 207, a slave 485 interface 202 for connecting the internal bus, and a slave power conversion circuit 203, the slave power conversion circuit 203 is connected to the microprocessor 201, the analog input channel 204, the switching input channel 205, the analog output channel 206, the switching output channel 207, and the slave 485 interface 202, respectively.

The host needs to adopt a high-performance chip, has strong operational capability and larger storage space, and preferably, the single chip microcomputer 101 adopts a 32-bit ARM chip.

Preferably, the microprocessor 201 is an 8-bit MCU chip.

As shown in fig. 5, the analog output channel 206 includes an analog-to-digital conversion chip 2061, the microprocessor 201 controls the output of the analog-to-digital conversion chip 2061 through 12C or SPI serial communication, the analog-to-digital conversion chip 2061 is connected to a signal amplifier 2062, and a voltage signal output by the analog-to-digital conversion chip 2061 is converted into a 4-20mA current or a 0-10V voltage signal through the signal amplifier 2062. When the microprocessor 201 is abnormally reset, the output of the digital-to-analog conversion chip is kept unchanged, and the latch function is automatically realized.

As shown in fig. 6, the switching value output channel 207 includes a latch 2071, and a plurality of relays 2072 are connected to the latch 2071. The latch signal is normally turned off, and only when the program in the microprocessor 201 judges that the latch is in a normal state, the output control signal is given first, and then the latch is in a through state, so that the relay is correctly controlled, and the fluctuation of the microprocessor 201 under the abnormal reset condition is avoided.

In this embodiment, a communication bus protocol between the master and the slave, a physical layer of which adopts a commonly used 485 polling architecture, the master sends commands of analog output and switching output, and the slave responds to input port information. If a certain address has no response, it indicates that the module corresponding to the address is empty, and the corresponding variable displays an "unbown" value, as shown in fig. 6.

In this embodiment, the physical channel of the slave is mapped to the BACnet IO object of the host. And setting a frame with the largest possible size, and automatically numbering the IO channels of the slave machines. The addresses of the slaves start from 0, and the section corresponding to each slave is assumed to have a maximum number of AI (analog input) N1, a maximum number of BI (switching value input) N2, a maximum number of AO (analog output) N3, and a maximum number of BO (switching value output) N4 for each IO. See table below:

the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A combined type BACnet controller is characterized in that: a host (1) and a plurality of slave machines (2) are arranged on one internal bus (3), and the plurality of slave machines (2) are hung on the internal bus (3) in a serial bus installation mode;

the host (1) comprises a single chip microcomputer (101), the single chip microcomputer (101) is connected with an interface for realizing BACnet communication and a host 485 interface (104) for connecting the internal bus, and further comprises a nonvolatile memory (105) and a host power conversion circuit (106), and the nonvolatile memory (105) and the host power conversion circuit (106) are respectively connected with the single chip microcomputer (101), the interface for realizing BACnet communication and the host 485 interface (104);

the slave (2) comprises a microprocessor (201), the microprocessor (201) is connected with an analog input channel (204), a switching value input channel (205), an analog output channel (206), a switching value output channel (2057), a slave 485 interface (202) used for being connected with the internal bus, and the slave power supply conversion circuit (203), wherein the slave power supply conversion circuit (203) is respectively connected with the microprocessor (201), the analog input channel (204), the switching value input channel (205), the analog output channel (206), the switching value output channel (2057) and the slave 485 interface (202).

2. The composite BACnet controller of claim 1, wherein: the interface for realizing BACnet communication comprises one or two of an Ethernet interface (102) for realizing BACnet IP communication or an RS485 interface (103) for realizing BACnet MSTP communication.

3. The composite BACnet controller of claim 1, wherein: the analog quantity output channel (206) comprises an analog-to-digital conversion chip (2061), the microprocessor (201) controls the output of the analog-to-digital conversion chip (2061) through 12C or SPI serial communication, the analog-to-digital conversion chip (2061) is connected with a signal amplifier (2062), and a voltage signal output by the analog-to-digital conversion chip (2061) is converted into a 4-20mA current or 0-10V voltage signal through the signal amplifier (2062).

4. The composite BACnet controller of claim 1, wherein: the switching value output channel (207) comprises a latch (2071), and a plurality of relays (2072) are connected to the latch (2071).

5. The composite BACnet controller of any one of claims 1-4, wherein: the single chip microcomputer (101) is a 32-bit ARM chip.

6. The composite BACnet controller of any one of claims 1-4, wherein: the microprocessor (201) is an 8-bit MCU chip.