CN112422856A - Energy harvesting image sensor system - Google Patents

Abstract

The present invention relates to a sensor system. The sensor system includes a pixel array, a DC/DC converter, and a photodiode stack. The pixel array is configured to operate in an image capture mode or an energy harvesting mode. The DC/DC converter is configured to convert energy captured by the pixel array when in an energy harvesting mode. The photodiode stack is positioned adjacent to the pixel array and is configured to provide power to the DC/DC converter.

Description

Energy harvesting image sensor system

Cross Reference to Related Applications

This application claims the benefit of U.S. provisional application serial No. 62/889,487 filed on 8/20/2019, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present invention generally relates to a system and method for harvesting energy via an image sensor system.

Background

In an energy harvesting system with an image sensor, the power supply rail of the self-powered image sensor must be charged to the required operating voltage before it can begin capturing images. It is desirable to use a DC-DC converter to generate the supply rail from the incident light. However, operating a DC-DC converter also requires a stable supply rail. Small rechargeable batteries, capacitors or other charge storage devices are often used to cold start the system.

Disclosure of Invention

The sensor system includes a pixel array, a DC/DC converter, and a photodiode stack. The pixel array is configured to operate in an image capture mode or an energy harvesting mode. The DC/DC converter is configured to convert energy captured by the pixel array when in an energy harvesting mode. The photodiode stack is positioned adjacent to the pixel array and is configured to provide power to the DC/DC converter.

The sensor system includes a pixel array and a photodiode stack. The pixel array is configured to operate in an image capture mode or an energy harvesting mode. The photodiode stack is monolithically integrated with the pixel array and is positioned adjacent to the pixel array. The photodiode stack is configured to provide a voltage to power a DC/DC converter configured to convert energy captured by the pixel array when in an energy harvesting mode.

The sensor system includes an image area including a pixel array configured to operate in an image capture mode or an energy harvesting mode, and one or more auxiliary photodiodes configured to provide a voltage to power a DC/DC converter configured to convert energy captured by the pixel array when in the energy harvesting mode.

Drawings

FIG. 1 is a block diagram of a battery-powered sensor node.

FIG. 2 is a block diagram of an energy harvesting sensor node.

FIG. 3 is a block diagram of an exemplary energy harvesting image sensor node.

Fig. 4 is a block diagram of an energy harvesting system powered by an image sensor pixel.

Fig. 5 is a block diagram of an output voltage regulator using a Switched Capacitor (SC) boost converter with ping-pong hysteretic control.

Fig. 6 is a graphical illustration of control signals for ping-pong hysteresis control of the SC boost converter shown in fig. 5.

Fig. 7 is a block diagram of a non-overlapping clock phase generator.

Fig. 8 is a graphical illustration of control and intermediate signals of the non-overlapping clock phase generator of fig. 7.

Fig. 9 is a block diagram of a clock generator using a staggered oscillator with power gating buffers.

FIG. 10 is a block diagram of a buffered high-speed ring oscillator.

Fig. 11 is a block diagram of a buffered high-speed current starved type ring oscillator.

Fig. 12A is a block diagram of a first exemplary non-overlapping two-phase clock generator with frequency-independent delay.

Fig. 12B is a block diagram of a second exemplary non-overlapping two-phase clock generator with frequency-independent delay.

FIG. 13 is a block diagram of a two-phase clock generator with staggered ring oscillators.

Figure 14 is a block diagram of an interleaved current starved type ring oscillator with power gated buffers.

Figure 15 is a block diagram of an interleaved current starved-type ring oscillator with power-gated buffers and non-gated buffers.

FIG. 16 is a block diagram of a plurality of non-overlapping clock phase generators based on a state machine.

FIG. 17 is a block diagram of an energy collection system.

Fig. 18 is a block diagram of a maximum output power tracking regulator that controls the switching frequency or duty cycle.

Fig. 19 is a block diagram of an alternative embodiment of a maximum input power tracking regulator that controls the switching frequency or duty cycle.

Fig. 20 is a system model diagram of a switching frequency regulator.

Fig. 21 is a block diagram of a regulator with a switched capacitor converter, a maximum output power tracking regulator, and a ping-pong hysteretic controller.

FIG. 22 is a graphical representation of the output voltage versus time of a regulator with a switched capacitor converter and ping-pong hysteresis control.

FIG. 23A is a schematic diagram of a hysteresis controller.

FIG. 23B is a graphical representation of output voltage and control signal versus time.

Fig. 24A is a schematic diagram of a ping-pong hysteresis controller.

FIG. 24B is a graphical representation of output voltage and control signal versus time.

FIG. 25 is a flow chart of a hill climbing algorithm to minimize output capacitor charging time.

Fig. 26 is a graphical representation of charging time and switching frequency versus time.

FIG. 27 is a block diagram of an asynchronous maximum output power tracking circuit.

Fig. 28 is a graphical representation of measured peak efficiency and tracking efficiency versus time for a system using maximum power point tracking.

FIG. 29 is a perspective view of an image sensor having a peripheral diode configured to capture light adjacent to an image field of view.

Fig. 30 is a block diagram of an auxiliary energy harvesting diode configured to power up a system via a DC-DC converter with a Low Frequency (LF) oscillator.

Fig. 31 is a block diagram of an image sensor in an energy harvesting mode using a DC-DC converter with a High Frequency (HF) oscillator.

Fig. 32 is a schematic diagram of a diode stack arranged adjacent to an image sensor.

Figure 33 is a cross-sectional view of an embodiment of two semiconductor structures configured to capture light.

Fig. 34 is a cross-sectional view of an alternative embodiment of two semiconductor structures configured to capture light.

Fig. 35 is a schematic diagram of an image sensor node with peripheral diodes capturing adjacent light for a cold start sequence from a powered energy collector.

FIG. 36 is a schematic diagram of a comparator with a built-in reference threshold for Power On Reset (POR).

FIG. 37 is a schematic diagram of a hysteretic comparator in which the reference voltage is generated by an isolated photodiode.

FIG. 38 is a graphical representation of measured voltage and logic levels versus time for a cold start image sensor using peripheral diodes.

FIG. 39 is a graphical representation of a typical image sensor application based on image capture rate versus time.

Detailed Description

As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.

The term "substantially" may be used herein to describe disclosed or claimed embodiments. The term "substantially" may modify a value or a relative property disclosed or claimed in the present disclosure. In this case, "substantially" may mean that the value or relative property which it modifies is within ± 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5% or 10% of the value or relative property in question.

Using distributed sensor nodes employing energy harvesting techniques may improve battery life and form factor. Using the sensors themselves as energy harvesting elements is an attractive option to further reduce the cost and footprint of such nodes. CMOS image sensors are one example of a pixel array that can be reconfigured to collect incident light. Several applications, including warehouse inventory tracking and structural failure detection, may capture images at a slow rate, such as once every 2-5 minutes, and are therefore compatible with ultra-low energy collection power levels. However, a key challenge of such circuit configurations is to ensure robust cold start and efficient operation over a wide range of light intensities.

Harvesting energy from an imager pixel array energy is generated with the pixel array when not being used to capture an image. However, the pixel array needs to be modified to multiplex (multiplex) between the energy harvesting mode and the image capture mode. These modifications result in low fill factors and large pixel pitches (i.e., reduced image resolution). In addition, system modifications require a battery or off-chip inductor to start (i.e., cold start). Furthermore, prior art designs employ maximum input power point tracking (MPPT) for power saving operation at varying light intensities. However, this does not necessarily result in maximum power delivery to the load.

Other related work in this area has explored more general energy harvesters with power management capabilities. A dedicated charge pump is used to enable cold start, but this entails a large area overhead. This design employs off-chip solar cells, which adds additional cost and floor space to the sensor node.

Fig. 1 is a block diagram of a battery-powered sensor node 100. The sensor node 100 comprises at least a sensor 102, such as an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof. The output of the sensor 102 may then be converted from an analog signal to a digital signal via an analog-to-digital converter (ADC) 104, and the digital signal may then be processed by a Central Processing Unit (CPU) 106. The sensor nodes also include a communication node 108. The communication node 108 may be a wireless node configured to communicate via a wireless protocol, such as cellular, 802.11 (Wi-Fi), 802.15, optical (e.g., via optical fiber), infrared (e.g., IrDA), or acoustic (e.g., ultrasonic). Here, the sensor node 100 is powered by a battery 110 or alternatively connected to the grid, e.g. via an AC/DC converter.

Fig. 2 is a block diagram of an energy harvesting sensor node 200. The sensor node 200 comprises at least one sensor 202, such as an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof. The output of the sensor 202 may then be converted from an analog signal to a digital signal via an analog-to-digital converter (ADC) 204, and the digital signal may then be processed by a Central Processing Unit (CPU) 106. The sensor nodes also include a communication node 208. The communication node 208 may be a wireless node configured to communicate via a wireless protocol, such as cellular, 802.11 (Wi-Fi), 802.15, optical (e.g., via optical fiber), infrared (e.g., IrDA), or acoustic (e.g., ultrasonic). Here, the sensor node 200 is powered by a sensor 202, which sensor 202 includes an energy harvesting system, or alternatively may be selectively configured as an energy harvesting system.

Fig. 3 is a block diagram of an exemplary energy harvesting sensor node 300. The sensor node 300 includes an Integrated Circuit (IC) 302, the integrated circuit 302 including a pixel array 304 and a DC/DC converter 306. The integrated circuit 302 is shown configured to operate the pixel array 304 as a voltage source to power a DC/DC converter that generates at least one voltage level, or in an imaging mode, where digital signals of a captured image are sent to an image readout circuit 308 that can be used to produce a remote image 310.

For example, consider a fully integrated energy collector IC that uses conventional 4-T image sensor pixels with a constant fill factor or pixel pitch arranged as a QVGA (320 x 240) pixel array. Referring back to figure 3 of the drawings,the image sensor is configured to be in an imaging mode (I)_M) Or an energy harvesting mode (EH). The design includes a DC/DC converter 306, such as a switched capacitor (S)_C) A boost converter for boosting the pixel array voltage (V)_IN) To generate two output voltages (A) for standard imager readout_VDDAnd D_VDD). In this prototype the read-out circuit is not included monolithically, but since the pixel structure is not changed, the integration should be relatively simple.

Next, we will describe the IC chip architecture and its key building blocks, followed by circuit details, and finally end up with measurements from prototypes fabricated in sub-500 nm CMOS Image Sensor (CIS) processes, however, the concepts disclosed in this application are not limited to these technologies.

Fig. 4 is a block diagram of an energy harvesting image sensor system 400. Sensor system 400 includes an image area 402 having an image/pixel array 404 and auxiliary photodiodes. Array 404 is coupled with DC/DC converter 406 and voltage regulator 408, with the regulated output fed back to DC/DC converter 406 via MPPT controller 401 and oscillator 412. The QVGA pixel array is forward biased when configured in an Energy Harvesting (EH) mode. When illuminated, the pixel array 404 collects energy and generates a V between 0.25-0.4V depending on the light intensity_IN. The voltage (V)_IN) Is boosted to digital (D)_VDD) And simulation (A)_VDD) Supplying, using a hysteresis control circuit, said number (D)_VDD) And simulation (A)_VDD) The supply was regulated to 0.6V and 1.8V. SC converters operate using non-overlapping clocks from oscillators. The oscillator frequency is set by the MPPT algorithm to maximize the power delivered to the load under different light and load conditions. An auxiliary photodiode adjacent to the pixel array captures edge light at the periphery of the imager pixel array to enable cold start.

The QVGA pixel array is comprised of conventional 4-T pixels. As shown in fig. 33 and 34, each pixel is embedded in a shared P-well and deep N-well. During Imaging (IM) mode, the P-well-N diffusion (PD 1) junction is reverse biased, while the P-well-deep N-well (PD 2) junction is shorted. The junction depth of the PD1 is constant and therefore has a negligible effect on image quality.

During the EH mode, the NMOS transfer gate and reset transistor of the 4-T pixel bias the N-diffusion to GND. The forward biased PD1 and PD2 junctions collect energy from light at different wavelengths, thereby generating a positive VIN at the P-well node. The entire array may be configured to share a set of reconfiguration switches outside the array to multiplex it between IM and EH modes. This approach is independent of pixel pitch and does not sacrifice fill factor. Thus, this work achieves a high reporting pixel fill factor (60.4%) and a small pitch (e.g., 5 μm) for EH pixels.

Each unit photodiode in the auxiliary array may have a structure similar to that in the pixel array and be placed in its own N-well. The photodiodes may be configured in series, parallel, or a combination thereof. For example, the photodiodes may be arranged in 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15 in series to produce a photodiode string of a desired voltage, which may then be connected in parallel with other photodiode strings to achieve a desired current. The test chip is constructed of nine photodiodes stacked in series (see fig. 32). The stack generates an unregulated secondary power rail (V)_AUX) The supply rail may reach about 1.8V. The size of the diode is gradually increased (4 x to 35 x) to compensate for the reverse photocurrent loss (i.e., I) at the deep nwell-pbase junction_s,leak). This sizing greatly enhances the V_AUXOutput drive capability of the rail.

Fig. 5 is a block diagram of an output voltage regulator 500 using a Switched Capacitor (SC) boost converter with ping-pong hysteretic control. Voltage regulator 500 uses a modified Dickson (Dickson) topology for fully integrated SC boost conversion. This topology enables a step charging of the capacitor, thereby reducing conduction losses across the switch. This topology also ensures that the voltage offset across the top and bottom plate parasitic capacitors is minimized to reduce losses. The SC boost-1 and SC boost-2 converters adopt daisy chainBy generating (unregulated) V in stepwise increments_DIGAnd V_ANAA voltage. These outputs are then adjusted using a hysteresis control to generate D_VDDAnd A_VDD. SC boost-1 at frequency f_HFOperating at non-overlapping clocks (phi 1 and phi 2), frequency f_HFProvided by a high frequency oscillator. When SC boost-2 gets input from SC boost-1, it is at a lower frequency f_DIVOperating on a gated clock. MPPT control regulation f_HFAnd f_DIVTo maximize the output power delivered by each stage. Fig. 6 is a graphical illustration of control signals for the SC boost converter shown in fig. 5.

The test set-up has a boost converter with 10 stages, each stage containing a 200 pF unit flying capacitor (fly capacitor). The converter can be programmed to tap two outputs from any two different stages, which provides the flexibility to change the conversion ratio independently. Referring to fig. 5, after stage 2, V from SC boost converter 1 is nominally tapped_DIGOutputs and taps V from SC boost converter 2 after stage 6_ANAAnd (6) outputting. The clocks of the unused stages are turned off to save energy.

Voltage regulation occurs through ping-pong hysteresis control. The two output capacitors C1 and C2 buffer the boost converter output in opposite phases. While one capacitor delivers energy to the load, the other capacitor buffers the boosted output. The charge enable signal QEN1 charges C1, while the load enable signal LEN2 connects C2 to the load. Likewise, once QEN1 and LEN2 have both been disabled, QEN2 and LEN1 begin to be in phase. The voltage across C1 and C2 is compared with V_refLAnd V_refHMaking the comparison allows independent control of the charge and discharge times.

Dependent on A_VDDAnd D_VDDLoad at, switching frequency f_HFTypically in the range from 0.5 to 10 kHz, and f_DIV/f_HFThe ratio of (a) varies from 0.75 to 1. Clock generators and drivers for SC boost converter switches are often the main source of energy loss in the energy scavenger. This is via an improved interleaved ring oscillator described below (IRO) is solved by design.

The oscillator of the chip operates at 82 Hz (LF for cold start; see below) and 10 kHz (HF). Here, referring to fig. 14 and 15, an ultra-low power Interleaved Ring Oscillator (IRO) generating two non-overlapping clock phases is disclosed. The IRO draws current proportional to its frequency due to the special circuit configuration that minimizes the through current in its pre-stage buffers (which would otherwise result in disproportionate overhead). IRO employs two interleaved ring oscillator chains that operate at the same operating frequency, but are out of phase. Each chain consists of an odd number (e.g., five in this embodiment) of current starved stages to control the oscillation frequency. The current sources in each stage are gated to control the phase of charging and discharging. Stage outputs 1-5 and 1 '-5' control gating control in the other chain. This results in I and I' (1 ≦ I ≦ 5) being out of phase. In order to minimize the through current in the subsequent buffers of the ring oscillator, specific i and i' nodes are used for power gating. Six gated buffer stages are used to recover small transition times and consume mainly dynamic switching currents. A conventional clock driver follows the gated buffer and drives the boost converter switch.

At the lowest operating frequency of 82 Hz, the measured IRO current consumption of the test apparatus was 2.1 nA/kHz with negligible shoot-through current. A current source biasing the ring oscillator sets the oscillator frequency. The non-overlapping delay is proportional to the rise and fall times of the stage nodes, which relaxes the clock driver requirements.

Here, circuit techniques are disclosed for generating ultra-low power clock phases for signal processing and power conversion. The present disclosure describes generating non-overlapping clocks over a very wide frequency range with very low power consumption.

Most signal processing or power conversion ICs use switched capacitor or inductor circuits, however in energy-constrained applications (such as energy harvesting devices, wireless sensor nodes, or implantable devices), an important source of energy consumption is the generation of these non-overlapping clocks. In these and other applications, the clock generator needs to operate over a wide range of frequencies depending on the mode of operation or available power.

A conventional on-chip non-overlapping clock generator consists of blocks in a dashed rectangle followed by a clock driver as indicated in fig. 7 and 8.

Fig. 7 is a block diagram of a non-overlapping clock phase generator 700. Clock generator 700 includes an oscillator 702, a buffer 706, a two-phase non-overlap generator 708, and a clock driver 710. Fig. 8 is a graphical illustration of control and intermediate signals of the non-overlapping clock phase generator of fig. 7.

Fig. 9 is a block diagram of a clock generator 900 with a buffered two-phase interleaved oscillator 902. The buffered two-phase interleaved oscillator 902 includes an interleaved oscillator 904 having a power-gated buffer 906. The buffered two-phase interleaved oscillator 902 provides an input to a clock driver 908.

Figure 10 is a block diagram of a buffered high-speed ring oscillator 1000. Buffered high-speed ring oscillator 1000 includes ring oscillator 1002, buffer 1004, and non-overlap generator 1006. Ring oscillator 1002 is shown as a 5-stage ring oscillator, however the ring oscillator may be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51 stages, etc. Further, buffer 1004 is shown as a single buffer, however this may be implemented as multiple buffers arranged in series or parallel or a combination thereof.

Current starved ring oscillators or relaxation oscillators are often used to generate variable frequency clocks at lower power. When the clock frequency decreases beyond a certain limit, the oscillator outputs (ɸ)_OSC) Rise time (T) of_r) And a fall time (T)_f) And (4) increasing. This results in a higher dc current in the subsequent buffers of the oscillator and any power reduction obtained by lowering the oscillator frequency is lost.

Fig. 11 is a block diagram of a buffered current starved high speed ring oscillator 1100. Buffered high-speed ring oscillator 1100 includes ring oscillator 1102, buffer 1104, and non-overlap generator 1106. The ring oscillator 1102 is shown as a 5-stage ring oscillator, however the ring oscillator may be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51, etc. Further, the buffer 1104 is shown as a single buffer, however this may be implemented as multiple buffers arranged in series or parallel or a combination thereof.

To reduce the number of clock drivers and repeaters in a chip, when the input power is limited, the period of non-overlap (T) is limited_nov) Must be large. The non-overlapping period depends on the delay introduced in the non-overlapping generator. Conventionally, increasing the length of the delay also increases the power consumption of the non-overlapping generator.

To overcome these important problems at lower power supplies, we propose a new type of interleaved oscillator to generate the non-overlapping clocks (ɸ a and ɸ B) without the need for additional non-overlapping generator circuits. The non-overlapping period increases with decreasing frequency, thereby enabling reduced clock drivers in energy-limited applications. To reduce the rise and fall times of the clock, we propose a new type of power-gated buffer to avoid shoot-through currents.

Conventional ring oscillators have an odd number of inverter stages. The oscillator output is buffered before being driven by the clock driver. To reduce the power through the oscillator, the inverters in the oscillator are made weaker (smaller W/L size). This increases the rise and fall times of the ring oscillator output, resulting in large through currents in the buffer.

A current starvation type ring oscillator is used to tune the frequency using a programmable current source in series with an inverter. As shown in fig. 11, the output of the current starved oscillator also has large rise and fall times to realize a low frequency clock. However, at lower frequencies, the through current in the buffers following the current starved ring oscillator dominates the total power consumption.

Fig. 12A is a block diagram of a first exemplary CMOS logic non-overlapping two-phase clock generator 1200 with frequency-independent delay. Fig. 12B is a block diagram of a second exemplary CMOS logic non-overlapping two-phase clock generator 1250 with frequency-independent delay. Here, the delay stage I_A1To I_AN、I_B1To I_BNAnd I₁To I_NAny number of inverters or similar logic structures may be used.

For low power, low frequency applications, it is desirable to have larger non-overlapping phases. This enables the use of a reduced number of buffer stages while tolerating greater clock skew. However, the larger delay comes at the cost of power consumption of these delay stages.

For high frequency clocks generated by current starved ring oscillators, the rise and fall times are small, and therefore, small non-overlapping phases are sufficient to ensure two-phase operation. Smaller non-overlapping phases ensure greater on-times in high frequency applications. This improves the transient stability behavior of the switched capacitor or inductor circuit.

Therefore, it would be desirable to make the delay between non-overlapping clock phases proportional to their frequency.

Fig. 13 is a block diagram of a two-phase clock generator 1300 with a staggered ring oscillator 1302. The interleaved ring oscillator 1302 includes a first current starved ring oscillator 1304 and a second current starved ring oscillator 1306 coupled such that an output of the first current starved ring oscillator 1304 is an input to the second current starved ring oscillator 1306, and the second current starved ring oscillator 1306 is an input to the first current starved ring oscillator 1304. The first current-starved ring oscillator 1304 and the second current-starved ring oscillator 1306 send signals to power gating buffers 1308 and 1310. The output of the first current-starved ring oscillator 1304 is an input to a first power-gated buffer 1308, and the gating control for the first power-gated buffer 1308 is the output of a second current-starved ring oscillator 1306. Similarly, the output of the second current-starved-type ring oscillator 1306 is an input to the second power-gated buffer 1310, and the gating control for the second power-gated buffer 1310 is the output of the first current-starved-type ring oscillator 1304. The time period or clock frequency may be based on a programmable current source in a current starved inverter.

The staggered ring oscillator helps generate a clock phase at half the original phase difference. These intermediate clock phases are used as gating control signals to prevent shoot-through current in the power-gated buffers, as shown in fig. 13.

Conventional buffers or clock drivers help drive non-overlapping clocks once the edges of the clocks are sufficiently sharp after passing through several stages of power gated buffers.

This approach also inherently introduces a delay between clock phases that is also proportional to frequency. Thus, low power, low frequency operation may be implemented using fewer clock repeater stages.

At higher available power, the clock frequency may be increased depending on the mode of operation and the non-overlapping periods are smaller. This feature helps to improve the stabilization of the switched capacitor voltage.

Figure 14 is a block diagram of an interleaved current starved-type ring oscillator with a power-gated buffer system 1400. The interleaved ring oscillator 1402 includes a first current starved ring oscillator 1404 and a second current starved ring oscillator 1406 coupled such that an output of the first stage first current starved ring oscillator 1404 gates the first stage second current starved ring oscillator 1406, and the first stage second current starved ring oscillator 1406 gates the first stage first current starved ring oscillator 1404. Third current starving ring oscillator 1404 and second current starving ring oscillator 1406 send signals to power gating buffers 1408 and 1410. The output of the first current starving type ring oscillator 1404 is an input to a first power gating buffer 1408, and the gating control for the first power gating buffer 1408 is the output of the second current starving type ring oscillator 1406. Similarly, the output of the second current starving-type ring oscillator 1406 is an input to the second power gating buffer 1410, and the gating control for the second power gating buffer 1410 is the output of the first current starving-type ring oscillator 1404.

The ring oscillators 1404, 1406 are shown as 5-stage ring oscillators, however the ring oscillators can be any odd number of stages, such as 5, 7, 9, 11, 21, 31, 41, 51, etc. Further, buffers 1108, 1410 are shown as double buffers, however this may be implemented as multiple buffers arranged in series or parallel or a combination thereof.

In addition, the first ringEach internal stage of the ring oscillator 1404 is staggered and used to gate internal stages of the second ring oscillator 1406, and each internal stage of the second ring oscillator 1406 is staggered and used to gate internal stages of the first ring oscillator 1404. E.g. to the first ring oscillator I_A1Of the first inverter stage of (a)₁Is used to gate the second ring oscillator I_B1To the second ring oscillator I, and to the second inverter stage of_B1Output B of the first inverter stage₁Is used to gate the first ring oscillator I_A1The first inverter stage of (1). This continues with each stage of each ring oscillator.

The power consumed by the interleaved ring oscillator and the power-gated buffer is linearly proportional to the clock frequency, which indicates that there is no shoot-through current even at very low clock frequencies. Furthermore, the power of the non-overlapping clock phase generator is linearly proportional to the supply voltage.

Fig. 14 shows two interleaved current starved ring oscillators, each having 5 stages. The current source in each stage helps to control the frequency.

Each current starved inverter in ring oscillator-A is gated by the switching output (B1-B5) of the corresponding inverter in oscillator-B, respectively. Likewise, the inverters in oscillator-B are gated by the switch outputs (A1-A5) from oscillator-A, respectively.

These interleaved ring oscillators produce clock phases that are 18 out of phase with each other and produce outputs that are 180 degrees out of phase. The outputs from these oscillators have the same frequency.

Taking outputs from nodes a5 and B5, we get non-overlapping clocks that are opposite in phase. However, at low clock frequencies, the rise and fall times are very large transition times.

These large transition times will result in large through currents in the subsequent buffers. We solve this problem using a power gated buffer. The power gating signal for the buffer is selected to be one of the appropriate oscillator phases a1-a5 and B1-B5 that have been generated. This is shown in fig. 14, where a first power-gated buffer B_A1From a first ring oscillator I_A2And the first power gating buffer B_B1By a second ring oscillator I_B2The output of the second inverter stage of (1) is gated. In this example, a second power gating buffer is used, where the second power gating buffer B_A2From a first ring oscillator I_A3And a second power gating buffer B_B2By a second ring oscillator I_B3The output of the third inverter stage of (1) is gated.

As an example, if a5 rises, the output of the first inverter after it will transition from high → low. Thus, to avoid through current in the inverter, it is gated by clock phase B2. This results in an output with a lower transition time without any through current loss.

Generating sharper clock phases in this manner results in clocks having non-overlapping periods proportional to the slow rise and fall times of the staggered ring oscillator. At lower supply voltage levels and lower clock frequencies, we obtain larger non-overlapping periods. On the other hand, at faster clock frequencies, the non-overlapping period decreases.

Figure 15 is a block diagram of an interleaved current starved-type ring oscillator with a power-gated buffer and a non-gated buffer system 1500.

Figure 15 is a block diagram of an interleaved current starved-type ring oscillator with a power-gated buffer system 1500. The interleaved ring oscillator 1502 includes a first current-starved ring oscillator 1504 and a second current-starved ring oscillator 1506 coupled such that the output of the first stage first current-starved ring oscillator 1504 gates the first stage second current-starved ring oscillator 1506 and the first stage second current-starved ring oscillator 1506 gates the first stage first current-starved ring oscillator 1504. The third current-starving ring oscillator 1504 and the second current-starving ring oscillator 1506 send signals to power- gating buffers 1508 and 1510. The output of the first current-starving type ring oscillator 1504 is an input to a first power-gated buffer 1508, and the gating control for the first power-gated buffer 1508 is the output of a second current-starving type ring oscillator 1506. Similarly, the output of the second current starved ring oscillator 1506 is an input to the second power gated buffer 1510, and the gating control for the second power gated buffer 1510 is the output of the first current starved ring oscillator 1504.

Conventional clock driver buffers increase the drive strength of these non-overlapping clocks. A simple state machine can generate any number of non-overlapping clock phases using a multiplexer to pass one of the two clocks, as shown in fig. 16.

Fig. 16 is a block diagram of a plurality of non-overlapping clock phase generators 1600 based on a state machine. The clock generator includes a state machine 1602 and a multiplexer. In this exemplary block diagram, there are three multiplexers (first multiplexer 1604, second multiplexer 1606, and third multiplexer 1608) for generating the three-phase clock. However, more or fewer multiplexers may be used to generate the desired number of phases. For example, if only two phases are needed, then only the first 1604, second 1606 multiplexers would be needed, and the third 1608 might be removed. If more phases are required, additional multiplexers may be added.

Energy collectors have transducers that convert physical energy, such as vibration, light, or temperature differences, into electrical energy. This electrical energy is often generated at a voltage different from the voltage required to charge a battery or capacitor. Switching voltage converters are commonly used to step up/down voltages.

In energy-limited applications, tracking the maximum output power at different inputs is challenging. The present disclosure outlines an analog maximum output power tracking scheme that uses a hill-climbing (also known as perturbation and observation) algorithm to adjust the switching frequency of a voltage regulator at very low energies. The proposed method adjusts the switching frequency to change the input and output impedance of the voltage regulator. This impedance matching helps deliver maximum power output from the collector.

Energy harvesting systems typically utilize hysteretic control to regulate the output voltage due to its simplicity and low power implementation. The present disclosure describes an improved modified hysteretic control with higher efficiency that also provides a control signal for tracking the output power.

Typical energy collection systems have transducers that convert, for example, light, pressure, or thermal energy into electrical energy. Electric energy from the transducer at a voltage V_INThe following are produced. This requires that the voltage is raised/lowered before it can be delivered to the load R_LOADOr stored in a capacitor C_LOADIn (1).

Fig. 17 is a block diagram of an energy collection system 1700. The energy harvesting system 1700 includes a clock generator 1702, a transducer 1704, a switching voltage converter 1706, a voltage regulator 1708, and a load having a resistance R_LOADAnd/or a capacitance C_LOADThe load of (2). The transducer 1704 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

Switching voltage converter at voltage V_OUTThe regulated output power is delivered. The converter requires a clock to periodically open and close its switches. The power delivered from the source to the load is regulated by varying the switching frequency or duty cycle. The feedback loop senses the output power and modulates the switching frequency or duty cycle as shown in fig. 18.

Fig. 18 is a block diagram of an energy harvesting system 1800 with a switching frequency regulator. The energy harvesting system 1800 includes a clock generator 1802, a transducer 1804, a switching voltage converter 1806, a voltage regulator 1808, having a load resistance R_LOADAnd/or load capacitance C_LOADAnd a maximum output power tracking module 1810. The transducer 1804 comprises an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

Sensing the output power requires sensing the output voltage and current and obtaining the product to adjust the switching frequency. This is extremely challenging in energy-limited applications, such as harvesting energy from environmental sources.

FIG. 19 shows aA method of maximizing power in an energy harvesting system. Fig. 19 is a block diagram of an energy harvesting system 1900 having a switching frequency regulator. The energy harvesting system 1900 includes a clock generator 1902, a transducer 1904, a switching voltage converter 1906, a voltage regulator 1908, having a load resistance R_LOADAnd/or load capacitance C_LOADAnd a maximum output power tracking module 1910. The transducer 1904 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

Each source has well-defined characteristics in its operating region, where its power can be maximized. For example, a thermoelectric generator (TEG) delivers maximum power when the voltage across it is half that under no-load conditions. Likewise, a photovoltaic cell or solar cell delivers maximum power when the voltage across the photovoltaic cell or solar cell is about 0.8 times the voltage under no-load conditions.

A simple and relatively low power implementation of measuring the source voltage under no load conditions results in the feedback control system shown in fig. 19. Regulating the voltage (V) delivered by the source by controlling the switching frequency or duty cycle_IN) Maximum power extraction from the source is enabled. The functionality of this system can be better described from the overall system model shown in fig. 20. Fig. 20 is a schematic diagram of a system model 2000 of a switching frequency regulator. The transducer source 2002 can be modeled as a davinin (Thevenin) voltage source Vs with an equivalent impedance Rs. The switching voltage converter 2004 is modeled as having a ratio of 1: N and a switching frequency f_CLKA voltage converter with an inversely proportional equivalent output impedance. And the load 2006 is modeled as a load resistance R_LOADAnd a load capacitor C_LOAD。

Controlling the frequency or duty cycle of the clock, looking at the converter (R)_IN) Is modulated so that V_INBecomes V according to energy source_INA part of (a). Under such conditions, R_INBecomes equal to Rs and draws maximum power from the energy source. Therefore, optimizing the clock to have impedance matching in matching network-1 results in matchingSub-optimal operation of network-2. This results in a lower total power output from the voltage converter.

The present disclosure relates to adjusting a clock to maximize total power output from a voltage converter. The main advantage of this solution is that it enables maximum power delivered from the energy harvesting system and is not limited to extracting maximum power from the source. Some novel points include:

some key aspects of the maximum power tracking system include:

the system may measure and maximize output power in energy-limited applications (e.g., energy harvesting), but embodiments are not limited to maximizing power from an energy source.

A method of sensing output power by measuring current from an output voltage regulator while consuming very low energy is achieved.

The current measurement from the voltage regulator does not require a series resistor or replica generation. The current output from the voltage regulator is measured by measuring the charging time of an intermediate capacitor in the voltage regulator.

The charge time of the intermediate capacitor is measured by converting a small bias current to a corresponding voltage and comparing the charge times at different clocks using a voltage regulator.

A novel multiplexed ping-pong hysteretic output voltage regulator scheme is disclosed that improves efficiency but maintains the simplicity of conventional hysteretic control.

Fig. 21 is a block diagram of a system 2100 having a regulator with a switched capacitor converter and ping-pong hysteresis control. The energy harvesting system 2100 includes a clock generator 2102, a transducer 2104, a switched voltage converter 2106, such as a switched capacitor converter, a ping-pong hysteretic control voltage regulator 2108, having a load resistance R_LOADAnd/or load capacitance C_LOADAnd a maximum output power tracking module 2110. The transducer 2104 includes an imaging sensor, a microphone, a humidity sensor, a pressure sensor, an infrared sensor, a magnetic sensor, a temperature sensor, or a combination thereof.

In one embodiment, the system 2100 is a fully integrated switched capacitor converter with hysteretic control. We regulate the output power by changing the switching frequency of the switched capacitor converter 2106. The output voltage is regulated using a novel ping-pong hysteresis controller 2108, which can improve the efficiency of the voltage regulator. The techniques described herein are not limited to the type of voltage regulator. The feedback control variable is also not limited to the switching frequency and may include a duty cycle or any other variable by which the voltage regulator impedance may be controlled. The output power is a product of the output voltage and the current, and the output power may be expressed as equation 1.

Pout = Vout * Iout （1）

The ability to sense the output voltage and output current to determine the product is challenging for low energy systems. The output voltage is regulated within the hysteresis band as shown in fig. 22. Fig. 22 is a graphical representation 2200 of the output voltage 2202 versus time 2204 of a regulator with a switched capacitor converter and ping-pong hysteresis control. In this graphical representation 2200, the output voltage waveform 2206 swings back and forth between a high output voltage at time 2208 and a low output voltage at time 2210 with a period between times 2208 and 2212.

V_OUT（=V_OUT,_HIGH–V_OUT,_LOW) The ripple voltage on is designed to be small, where the output voltage remains substantially constant and therefore the output power is proportional to the output current. To maximize the output power, the output current from the converter needs to be maximized.

To sense the output current, the current is measured by measuring the voltage across a series resistor or using a replica current mirror. However, these require additional circuitry and consume power to sense the current.

Here, charging the output capacitor in the hysteretic controller using time is used as an estimate of the output current, as illustrated in fig. 23A. FIG. 23A is a schematic 2300 of a hysteresis controller using a Schmitt trigger 2302. Fig. 23B is a graphical representation 2350 of output voltage 2352 and control signals 2354, 2356 with respect to time 2358. The higher the charging current, the shorter the charging time.

When QEN (charge-enable) is high, the output current from the converter charges the output capacitor Co. When QEN is low, the Co discharges to deliver power to the load. When delivering power to the load, energy from the disconnected converter is not utilized, resulting in inefficient operation.

To correct this problem, a ping-pong hysteresis control technique is disclosed in fig. 24A. Fig. 24A is a schematic diagram of ping-pong hysteresis controller 2400, which includes combinational logic 2402 that generates control signals. FIG. 24B is a graphical representation 2450 of the output voltage 2452 and control signals 2454, 2456, 2458, and 2460 versus time 2462. Two capacitors are used to store the output from the converter before it is delivered to the load. When the first capacitor C_O1Second capacitor C when charging from the converter_O2Discharge to deliver power to the load. Each node is connected with V_OUT,HIGHOr V_OUT,LOWThe comparison gives independent control of the charging time.

This ping-pong operation of the two capacitors delivers output power during load delivery without wasting converter energy, making it more efficient than conventional hysteretic control. In other embodiments, 3 or more capacitors may be used, with charge being provided to each capacitor in a round robin fashion.

To measure the output current from the converter, the charge time in one or both capacitors may be observed. The switching frequency of the clock is adjusted using a hill climbing or perturbation and observation algorithm such that the charging time of the output capacitor is minimized. The algorithm is explained with the flow chart in fig. 25.

Fig. 25 is a flow chart of a hill climbing algorithm 2500 that minimizes the output capacitor charging time. Here, the controller starts operation at step 2502. At step 2504, the controller initializes the minimum charge time to an initial value, such as a maximum value based on the capacitor value and the output load condition. At step 2506, control decreases the switching frequency (f)_CLK) The amount of reduction may be a fixed amount or a variable amount. At the step 2508 of the process,the controller monitors the charging time.

At step 2510, the controller compares the charge time to a minimum charge time. If the charging time is less than the minimum charging time, the controller sets the minimum charging time to the current charging time in step 2512 and branches back to step 2506. If the charge time is greater than or equal to the minimum charge time, control branches to step 2514. At step 2514, control increases the switching frequency (f)_CLK) And proceeds to step 2516 where the controller monitors the charge time.

At step 2518, control compares the charge time to a minimum charge time. If the charging time is less than the minimum charging time, the controller sets the minimum charging time to the current charging time in step 2520 and branches back to step 2514. If the charge time is greater than or equal to the minimum charge time, control branches to step 2522. At step 2522, the controller switches the frequency (f)_CLK) Decreases to the previous value and exits the loop at step 2524.

Fig. 26 is a graphical representation 2600 of charging time 2602 and switching frequency 2604 versus time 2606. The change in switching frequency over time is shown in fig. 26 as an example case. The algorithm reduces the switching frequency from f1 to f2 and the observed charge time increases. Therefore, the frequency update direction is reversed, and we continuously increase the switching frequencies f2 to f5, and observe that the charging time is continuously decreased. This indicates that we are operating our complete system to deliver more output power from the converter. If we increase the switching frequency further to f6, the charging time increases and we stop the hill climbing algorithm. The second to last switching frequency value (in this case f 5) is chosen as the optimum value.

The charging time is detected by converting it to a proportional voltage so that it can be compared using a conventional voltage comparator. As shown in FIG. 27, the bias current I is small_BIASFor charging the capacitor (C) during the charging time_XOr C_Y) And (6) charging.

Fig. 27 is a block diagram of an asynchronous maximum output power tracking circuit 2700. Asynchronous maximum output power tracking circuit 2700 includes capacitor group 2702, schmitt trigger comparator 2704, hill climbing logic 2706 that can be used to control the charging and resetting of the capacitors in capacitor group 2702. The hill climbing logic 2706 feeds an up/down counter 2708, which then has a bias control 2710 to set the frequency of at least one oscillator 2712.

Initially, C_XCharged to supply V_AUXAnd C is_YThe charging time corresponding to the current frequency f1 is stored. Frequency decreases from f1 to f2, and I_BIASTo C_XThe charging is performed for an increased charging time. Thus, the voltage comparator determines V_XGreater than V_Y. We retain C_YTo a minimum value of, and reset C_X. The hill climbing logic asserts increment frequency and the up/down counter sets bias control for the new switching frequency f 3. In our example case, I_BIASIs C_XRecharging is performed for a reduced charging time and the voltage comparator determines V_XLess than V_Y。C_YNow reset and the frequency update continues until the charging time starts to increase again.

The circuit proposed here can be designed as an asynchronous circuit, which switches only at the end of one charging cycle. This prevents power loss at each clock.

Maximum Power Point Tracking (MPPT) control adjusts the boost converter clock frequency generated by the IRO. The switching frequency of the boost converter modulates the input and output impedance of the converter. By interfacing with limited source and load impedances, MPPT control can maximize load current delivery at a regulated output voltage. Minimizing QEN1/QEN2 pulse width maximizes load current and, therefore, output power delivered to the load.

In the circuit of fig. 27, the bias current (I) is small_BIAS) Supply capacitor (C)_AOr C_B) And charging, and converting the charging time of QEN1 into a voltage. Comparison V_AAnd V_BIt is helpful to compare the charging times at different frequencies. During power-up, V_AIs initiated byIs converted into V_AUXAnd V is_BIs initialized to GND. The hill climbing logic selects CA or CB to hold the smaller voltage and to override the larger voltage after resetting it. Thus, the switching frequency is gradually decreased or increased until QEN1 the pulse width begins to increase. This is established using an increment or decrement signal to an increment/decrement counter controlling the bias of the HF oscillator, see again fig. 27.

The hill climbing logic is implemented as custom event triggering logic that evaluates the new state only on the falling edge of QEN 1. This slow evaluation enables ultra low power operation and provides sufficient time for updating the HF oscillator frequency. Thus, each QEN1 pulse width corresponds to a different switching frequency.

Fig. 28 is a graphical representation 2800 of measured peak efficiency 2802 and tracking efficiency versus time 2806 for a system using a maximum power point 2804.

Fig. 28 shows the maximum boost converter efficiency and tracking efficiency at various light intensities. Measured at D_VDDLoad of 2-12 M.OMEGA.and A_VDDAt a load of 27-530M omega above (lower load resistance at brighter lighting). By sweeping the switching frequency around the MPPT prediction, the maximum boost converter efficiency is found. MPPT tracking efficiency is the ratio of the efficiency predicted by the MPPT loop to the maximum efficiency found by the sweep. Under indoor lighting conditions of 430 lux, our boost converter operates at maximum efficiency of 52.4%. At a low light of 52 lux, the efficiency of the boost converter at a minimum input power of 79.1 nW is 38.2%. The MPPT output power tracking efficiency exceeds 96%.

For self-powered transducers such as image sensors, the power supply rail must be charged to the required voltage before the image sensor can begin capturing an image. This is achieved by generating these supply rails from incident light using a DC-DC converter. However, a stable supply rail is also required to operate such a DC-DC converter.

The present disclosure addresses cold start of a DC-DC converter using edge incident light near the image sensor. The present disclosure illustrates how to convert very low levels of light to higher voltages and establish a stable power rail, after which a conventional DC-DC converter can hold the power rail and the sensor can then be used to capture an image.

Light from an object passes through a lens or lens system and falls on an image sensor. Some portion of the light passing through the lens or lens system also falls on the peripheral area around the image sensor. This marginal light energy is used to cold start the DC-DC converter to generate the power rails of the imager.

In the present disclosure, the peripheral region is filled with photodiodes arranged in series, parallel, and combinations thereof, which are configured to collect an unregulated voltage Vaux that is high enough to allow operation of the circuit, but which has very limited current drive capability. The auxiliary voltage (Vaux) enables/powers the operation of a Low Frequency (LF) oscillator that drives a DC-DC converter for generating a main supply voltage.

Fig. 29 is a perspective view of an Integrated Circuit (IC) 2902 including an image sensor 2904 and a peripheral region 2906 having diodes. The image sensor is configured to capture light from an object that is focused via the lens 2908 or lens system. The peripheral region 2906 is configured to capture peripheral light 2910 that is incident on the IC 2902 through the lens 2908 and is adjacent to the region of the image sensor 2904.

Fig. 30 is a block diagram of an auxiliary energy collection system 3000, the auxiliary energy collection system 3000 having an auxiliary diode 3008 proximate to an image sensor 3004 and configured to provide power via a DC-DC converter 3006 having an LF oscillator 3002.

FIG. 31 is a block diagram of an auxiliary energy harvesting system 3100 having an image sensor 3104 feeding a voltage regulator 3108 to generate a supply voltage V using a DC-DC converter 3106 clocked by an HF oscillator 3102 in an energy harvesting mode_sup。

The primary input voltage (energy) to the DC-DC converter 3006 is generated by an image sensor 3004 configured as an energy collector. Using LF oscillator 3002, energy from Vaux is used to boost the voltage on Vsup to a sufficient level to allow forAllowing secondary High Frequency (HF) oscillator 3102 to take over. Once in this normal operating configuration, the cold start is complete and energy can be stored or used to drive the load (R)_load) As shown in fig. 31. Conventional operation can generate much more energy from the imager sensors 3004, 3104 because it uses the high frequency oscillator 3102 to drive the DC- DC converters 3006, 3106.

During start-up from a complete power-down, light first falls on the image sensor, while all supply voltage rails are essentially at ground potential. Once these rails reach the threshold voltage level, conventional conversion using an HF oscillator can begin, as shown in fig. 31.

Fig. 32 is a schematic diagram of an imaging system 3200 including an integrated circuit 3200, the integrated circuit 3200 having a pixel array 3204 and a diode stack 3206 arranged adjacent to the pixel array 3204. The diode stack has: first diode D₁Wherein the anode is a P-well (PW) and the cathode is a deep N-well (DNW); a second diode D2, wherein the anode is a P-well (PW) and the cathode is a deep N-well (DNW), and the second diode D2 is in series with D1; and forming a series of diodes in series through the Nth diode D_nWherein the anode is a P-well (PW) and the cathode is a deep N-well (DNW). By D₁Is a current of₁And by D₂Is a current of₂Which is equal to pass through I₁And a current through substrate diode D_R1Leakage current I of_R1. Furthermore, by D_nHas a current of I_nWhich is equal to pass I₂Current (I) of₁ + I_R1) And a through-substrate diode D_R2Leakage current I of_R2。

FIG. 32 illustrates one embodiment of an arrangement of auxiliary photodiode stacks around a test IC based Energy Harvesting (EH) image sensor. The test IC is configured with nine photodiodes stacked to form a series connection. In other embodiments, the auxiliary diode arrangement may not be around the entire circumferential portion of the pixel array, but may be on one side of the pixel array, or on multiple sides of the pixel array. Furthermore, the test chip monolithically combines the pixel array and the auxiliary diode, however in other embodiments the auxiliary diode may be on a separate chip such that the two chips are combined in a multi-chip module (MCM).

FIG. 33 is two monolithic semiconductor structures S configured to capture light₀And S₁ Cross-sectional view 3300 of an embodiment of (a). First structure S₀J1 between N region and P Well (PW) with three junctions₁J2 between PW and deep N-well (DNW)₁And J3 between the P Substrate (PSUB) and the DNW₁. These three junctions form three diodes D₀₁、D₀₂、D₀₃. The structure includes an interconnect such that D₀₃And D₀₂In parallel, and D₀₁Is reverse biased.

FIG. 34 is two semiconductor structures S configured to capture light₀And S ₁3400, cross-sectional view of an alternative embodiment. Similar to fig. 33, the structure has a first structure S₀The first structure S₀J1 between N region and P Well (PW) with three junctions₁J2 between PW and deep N-well (DNW)₁And J3 between the P Substrate (PSUB) and the DNW₁. These three junctions form three diodes D₀₁、D₀₂、D₀₃. The structure includes an interconnect such that D₀₃Is forward biased, and D₀₂And D₀₁Is reverse biased.

In the test chip, each photodiode in the stack is located in a dedicated, separate deep N-well, as shown in cross-section for the structures in fig. 33 and 34. To account for reverse saturation leakage current at each deep nwell-pbase junction (I2, I3), the lower photodiodes in the stack are made larger. As we rise in the stack, the size of the photodiode gradually decreases, as shown schematically in fig. 32. The lowest photodiode is larger because it must carry a larger (I1 + I2+ I3) current than the photodiode above it, which carries the (I1 + I2) current. The pyramid structure of the entire nine photodiode stack is shown in the schematic diagram of fig. 32, and greatly improves the current driving capability of the generated Vaux supply range.

The diode is approximately geometrically rounded to the nearest integer. Each photodiode in the stack is composed of a set of unit cells. This allows for a high degree of layout flexibility of the stack in the peripheral region while maintaining the geometric progression ratio.

Fig. 35 is a schematic diagram of an image sensor node 3500 having a peripheral diode 3502 and an image sensor 3504. Peripheral diode 3502 is configured to collect energy from light at the periphery of image sensor 3504. Image sensor 3504 is configured to collect energy and capture images. System 3500 uses a Low Frequency (LF) oscillator 3506 connected to DC-DC converter 3508 during cold start. Once a sufficient voltage is generated on Win and DVDD and AVDD have reached their specified levels, the DC-DC converter switches to a High Frequency (HF) oscillator and its output is connected to the load.

The power sequence from cold start to normal operation must follow a definite order to prevent any unwanted leakage through the chip and to ensure proper function. The following describes a sequence of steps for a cold start.

To enable energy autonomous operation, the IC is constructed so that system 3500 begins using V when light is first shined on the chip_AUXA power supply rail. The test apparatus delivers approximately 25 nW at 1.8 volts under dim room lighting conditions (25 lux). The four-phase cold start sequence shown in FIG. 35 is described as follows:

first, power gating is performed on the entire chip 3500 up to V_AUXClimb past a certain threshold and assert V_AUXGD （V_AUX__GOOD) A signal.

Second, when V_INExceeding the open circuit voltage (V) of the isolated pixel_OC) At a part of (2), from V_AUXPowered comparator assertion V_INGD（V_{IN_GOOD}). In other words, when V_INAbove a threshold level.

Third, ultra low power, Low Frequency (LF) oscillator 3506 is driven from V_AUXThe rails operate to generate non-overlapping clocks for the SC boost converter.

Fourth step ofSC boost converter will be V_INIs raised to A_VDDAnd D_VDDRail and not deliver power to the load. Once the output rail is within regulation range (e.g., 1%, 2%, 3%, 4%, 5% of the desired output voltage), the COLDST (cold start complete) signal is asserted to begin normal operation with the HF oscillator and the same boost converter. Normally open wake-up comparator A in FIG. 35_ISThere may be built-in weights or offsets to implement the built-in references. When V is_AUXAssertion of V beyond threshold generated by offset (-1.8V)_AUXGD。V_AUXGDThe associated PMOS load device introduces hysteresis.

The more detailed flow follows the following four steps:

step 1: with incident light, Vaux from the photodiode stack ramps up to a higher voltage. When it crosses some minimum threshold, the Vaux Good signal is asserted. This opens the power gating switch and power from the Vaux _ Gated goes to all other parts of the chip. The rest of the chip does not get any power until Vaux _ Good is asserted, and therefore, the only power consuming block in the entire chip is the ultra-low power Vaux comparator.

Step 2: after Vaux _ Good is asserted, the input voltage of Vin from the imager pixel is compared to some reference. Vin _ Good is asserted once Vin reaches a stable voltage above a certain minimum value.

And step 3: the assertion of both Vaux _ Good and Vin _ Good implies that we can run the bias current and LF oscillator starting from the Vaux _ Gated supply with very small current and very low frequency.

And 4, step 4: these low frequency clocks then drive the DC-DC converter to generate the output Vsup voltage. The Vsup reaching the minimum defined value asserts the cold start complete signal. This assertion then enables the conventional efficient conversion mode using the HF oscillator.

Vin is constantly converted to Vsup with much higher efficiency and output load delivery is enabled. The output Vsup is regulated to within a certain voltage band.

An advantage of such a system and method is that it enables a cold start of a self-powered image sensor. This is achieved without using any extra batteries, supercapacitors, inductors or charge pumps in the circuit and therefore has cost and size advantages.

Each photodiode has two vertically stacked PN junctions that collect light: N-diffusion-P-well and P-well-deep N-well. Each photodiode is located in its own deep N-well.

As shown in fig. 32, 33 and 34, there is a reverse photocurrent loss at each deep nwell-pbase junction. In another embodiment, the photodiodes in the stack are sized in an approximately geometric progression to account for reverse current junction leakage between two consecutive photodiodes. This enables higher current delivery from the Vaux supply.

The size ratio of the photodiodes is selected to be <2 to accommodate deep N-well-pbase photocurrent losses while still keeping the area of the auxiliary photodiode stack small enough to fit in the periphery of the pixel array.

Several small cell photodiodes are arranged in parallel to create a larger photodiode. The smaller photodiodes may be arranged in a peripheral ring outside the pixel array shown in fig. 32.

This cold start scheme ensures that under all lighting conditions each supply rail reaches its defined voltage level without any leakage current or loss of function.

When light is first incident on the chip, there is no reference voltage to compare with Vaux, so a new skew comparator with offset that can act as a reference is disclosed in fig. 36.

Also, a part of the open circuit voltage (Voc) of the isolated photodiode is used as a reference for comparison with Vin, as shown in fig. 37.

The cold start sequence starts with Vaux generation, which has the following four steps.

Step 1: vaux is the supply and input to the skew comparator as shown in figure 36. Fig. 36 is a schematic diagram of a comparator 3600 with a built-in reference threshold for power-on reset (POR). When light first falls on the photodiode, Vaux is close to groundAnd I is_L~I _R0. Due to the size setting of the skew, a small Vaux was originally employed. However, when Vaux ramps up beyond a certain voltage level, I is exponential due to the drain current of the transistor when operating in the sub-threshold region versus the gate voltage_L>I_R. Thus, the reference voltage is built into the comparator.

Ultra-low power operation is achieved by a tail current source biased in the deep sub-threshold. Hysteresis in the threshold is introduced by skewing the load of the comparator according to the current Vaux _ Good value. In the test chip, V is used to provide the offset for the step in the comparator_IN1Is set to 3V_AUX/8，V_IN2Is set to 5V_AUXAnd/8, and V_BIASIs set to V_AUX8, such that 0< V_BIAS < V_IN1 < V_IN2 < V_AUX。

Step 2: when Vaux Good is asserted, the power-Gated Vaux Gated supply enables the comparator to check for V from the imager pixel_INWhether the rail is high enough to be loaded. The reference voltage for Vin _ Good generation is implemented using a portion of the open circuit voltage (Voc) of the isolated photodiode, as shown in fig. 37. Voc is the maximum voltage reached by the idler Vin.

FIG. 37 is a schematic 3700 of a hysteretic comparator with reference voltage isolated by photodiode D₁And (4) generating. The first 3702 and second 3704 comparators have a reference voltage input from a voltage divider 3708, the voltage divider 3708 being used for the slave diode D₁The voltage generates a reference voltage. The output of the first comparator 3702 is used to enable the Flip-Flop (Flip-Flop) while the output from the second comparator 3704 is used to drive the active low RESET of the Flip-Flop.

And step 3: after Vaux _ Good and Vin _ Good are asserted, low power current bias generation is performed, followed by non-overlapping clock generation using the LF oscillator.

And 4, step 4: these non-overlapping clocks drive the DC-DC converter to generate a stable Vsup power rail. Once the rail is established, power is delivered to the load at the regulated voltage level using conventional operation of the HF oscillator.

Fig. 38 is a graphical representation 3800 of the measured voltage 3802 and logic level 3804 versus time for a cold-start image sensor using peripheral diodes.

Fig. 38 illustrates a measured cold start sequence waveform. Once V is_AUXClimbing above 1.8V, declaring V_AUXGDAnd when V is_INOver 0.7V_OCWhen, assert V_INGD. Upon assertion of DV_DDGDAnd AV_DDGDThe chip begins normal operation and provides a regulated output voltage.

Program code embodying the algorithms and/or methods described herein may be distributed as program products, individually or collectively, in a variety of different forms. Program code may be distributed using a computer readable storage medium having computer readable program instructions thereon for causing a processor to implement aspects of one or more embodiments. Inherently non-transitory computer readable storage media may include volatile and non-volatile, and removable and non-removable tangible media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data. Computer-readable storage media may also include RAM, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other solid state memory technology, portable compact disc read-only memory (CD-ROM) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be read by a computer. The computer-readable program instructions may be downloaded from a computer-readable storage medium to a computer, another type of programmable data processing apparatus, or another device, or to an external computer or external storage device via a network.

The computer readable program instructions stored in the computer readable medium may be used to direct a computer, other type of programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function, act, and/or operation specified in the flowchart or figures. In some alternative embodiments, the functions, acts and/or operations specified in the flowcharts and figures may be reordered, processed serially and/or processed concurrently in accordance with one or more embodiments. Further, any flow diagrams and/or diagrams may include more or fewer nodes or blocks than those illustrated consistent with one or more embodiments.

While the present invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of the general inventive concept.

Claims (20)

1. A sensor system, comprising:

a pixel array configured to operate in an image capture mode or an energy harvesting mode;

a DC/DC converter configured to convert energy captured by the pixel array when in an energy harvesting mode; and

a photodiode stack positioned adjacent to the pixel array configured to provide power to the DC/DC converter.

2. The sensor system of claim 1, wherein the photodiode stack and pixel array are monolithically integrated.

3. The sensor system of claim 2, wherein the photodiode stack has at least 2 diodes coupled in series.

4. The sensor system of claim 3, wherein the photodiode stack is nine diodes coupled in series.

5. The sensor system of claim 1, wherein the DC/DC converter is a boost converter.

6. The sensor system of claim 1, further comprising a lens configured to focus light onto the pixel array and photodiode stack.

7. The sensor system of claim 1, wherein the photodiode stack surrounds the pixel array.

8. The sensor system of claim 1, further comprising a comparator with a built-in reference generation configured to output a signal indicating that a voltage across a diode in the photodiode stack crosses a threshold.

9. The sensor system of claim 1, wherein the pixel array is a 4-T pixel array.

10. A sensor system, comprising:

a pixel array configured to operate in an image capture mode or an energy harvesting mode; and

a photodiode stack positioned adjacent to and monolithically integrated with the pixel array, the photodiode stack configured to provide a voltage to power a DC/DC converter configured to convert energy captured by the pixel array when in an energy harvesting mode.

11. The sensor system of claim 10, wherein the pixel array is a 4-T pixel array.

12. The sensor system of claim 10, further comprising a comparator with built-in reference generation configured to output a signal indicating that a voltage across a diode in the photodiode stack crosses a threshold.

13. The sensor system of claim 10, wherein each diode of the photodiode stack is formed by a first PN junction between a P-well and a deep N-well and a second junction between a P-well and an N-well, wherein the N-well has a higher doping concentration than the deep N-well.

14. A sensor system, comprising:

an image area comprising an array of pixels configured to operate in an image capture mode or an energy harvesting mode; and

one or more auxiliary photodiodes configured to provide a voltage to power a DC/DC converter configured to convert energy captured by the pixel array when in an energy harvesting mode, wherein the photodiodes are configured to provide a voltage to power the DC/DC converter in response to a cold start.

15. The sensor system of claim 14, wherein the imaging mode is configured to send digital signals of the captured image to an image readout circuit configured to generate a remote image.

16. The sensor system of claim 14, wherein the pixel array is configured to collect energy in response to being illuminated.

17. The sensor system of claim 14, wherein the photodiode stack has at least 2 or more diodes coupled in series.

18. The sensor system of claim 14, wherein the one or more auxiliary photodiodes are integrated around or adjacent to the pixel array.

19. The sensor system of claim 14, further comprising a lens configured to focus light onto the pixel array and photodiode stack.

20. The sensor system of claim 14, wherein the one or more auxiliary photodiodes comprise at least nine photodiodes stacked to form a series connection.

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