CN112422150B

CN112422150B - Base station

Info

Publication number: CN112422150B
Application number: CN202011289100.2A
Authority: CN
Inventors: 杨峰; 任维佳; 杜志贵; 陈险峰
Original assignee: Spacety Co ltd Changsha
Current assignee: Spacety Co ltd Changsha
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2022-04-15
Anticipated expiration: 2038-12-28
Also published as: CN112422151B; CN109698712A; CN109698712B; CN112422150A; CN112422151A

Abstract

A base station for frequency converting signals received by the base station to a plurality of different radio frequency output frequencies to establish multi-channel transmission with a communication satellite, the base station comprising at least an encoding processor. The base station is configured to process its received signals as follows: the encoding processor performs encoding processing on the signal at least in a manner that BCH encoding processing, RS encoding processing, and convolutional encoding processing are collectively processed to acquire an encoded signal.

Description

Base station

The application is 201811629492.5, 28.12.2018, the application type is an invention patent and the application name is a divisional application of a narrow-band satellite communication system.

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to a base station.

Background

The characteristics of large path loss and low receiving power of satellite communication enable the satellite communication to be easily interfered by high-power narrow-band signals, so that the interference level after demodulation is improved, and the performance of a satellite communication system is reduced. A narrowband signal is a signal whose source signal bandwidth is much smaller than the carrier center frequency. In order to improve the satellite communication quality, a series of narrowband interference suppression measures based on, for example, the time domain or the frequency domain are proposed. The basic idea of adopting the method for resisting the narrow-band interference in the frequency domain is as follows: the main information contained in the signal is retained in the phase spectrum of the frequency spectrum, and the amplitude spectrum only represents the power of the signal, so that the signal can be effectively recovered by only retaining most phase information of the signal. When the spectrum width occupied by the high-power narrow-band interference is far smaller than the spectrum bandwidth occupied by the spread spectrum signal, the interference spectrum is set to zero, and then the narrow-band interference suppression can be realized. For example, the suppression of narrowband interference can be realized by using DFT transform, DFT has the advantages of multiple interference suppression, no need of convergence process and simple structure, but the frequency spectrum of interference leaks due to windowing processing, thereby resulting in incomplete interference suppression.

Currently, the following two methods are mainly used for frequency domain filtering: although the method can remove narrow-band interference, the windowing process reduces the frequency spectrum leakage during FFT to avoid interference diffusion to other frequency points, and simultaneously has the defect of causing distortion of input signals and loss of signal-to-noise ratio of output signals. Secondly, in order to reduce the signal-to-noise ratio loss caused by windowing, an interference suppression technology based on the superimposed fast Fourier transform is provided. The basic idea is to copy and shift windowing the input data, obtain two windowed data together with the original windowed data, perform FFT transformation, perform filtering in the frequency domain, perform IFFT after filtering to obtain time domain data without interference, and finally align and combine the two paths of data to obtain the final output. The method has the following defects: firstly, the interference does not always exist, but the interference canceller works all the time, and unnecessary system power consumption is increased; secondly, the length of FFT/IFFT is fixed, and the sensitivity for detecting narrow-band interference is limited; thirdly, the window function is fixed, which is not beneficial to filtering the interference in a large dynamic range; fourthly, a method for delaying data in the existing OFFT interference suppression method generally adds a module of delayed data before windowing, and is used to buffer one path of input data to be output together with another path of original data for windowing, and after frequency domain filtering, the module that also needs to add a delayed data delays the path of data that is not delayed, so that the delayed path of data can be aligned with the path of data that has been delayed before for subsequent merging and output.

Patent document CN105634543A discloses a method and system for anti-narrowband interference, which performs rough estimation on interference strength of input signals and determines a window function; according to the window function, performing the grouped windowing processing on the input signals, and performing N-point FFT (fast Fourier transform) on each group of windowed input signals to obtain frequency domain spectral lines of the windowed input signals; taking the signal output after each N-point FFT as a signal group, dividing the signal group into a plurality of sub-groups with the same point number, and determining an initial embedding value according to the average value of the signal amplitude of each sub-group; filtering interference spectral lines in frequency domain spectral lines by combining a self-adaptive variable threshold algorithm and an initial embedding bit value; performing IFFT transformation on the signals subjected to interference suppression respectively, and outputting time domain signals; and synthesizing and outputting each path of time domain signal to finish the narrow-band interference resistance of the input signal. By applying the narrow-band interference resisting method, interference spectral lines can be effectively filtered, and the reliability of a link is improved. The invention multiplies the time domain of the signal by a window function to carry out windowing processing before carrying out fast Fourier transform processing, the multiplication operation in the time domain is equivalent to convolution processing in the frequency domain, and therefore, the windowing effect is only to reduce side lobes generated by interference sources. The performance that the windowing process can improve depends on the frequency of the interferer. When the interference source is not located at a certain subcarrier frequency, spectrum leakage occurs, and narrowband interference affects all adjacent subcarriers. And it does not consider canceling intercarrier interference.

Disclosure of Invention

The word "module" as used herein describes any type of hardware, software, or combination of hardware and software that is capable of performing the functions associated with the "module".

In view of the deficiencies of the prior art, the present invention provides a narrowband satellite communication system, at least comprising a communication satellite and a base station, wherein the communication satellite is configured to perform at least interference suppression processing on a signal during relay of the signal to realize transmission of the signal among a plurality of base stations, and the base station frequency-converts the signal received by the base station into a plurality of radio frequency output frequencies different from each other to establish multi-channel transmission with the communication satellite, and wherein the communication satellite is configured to: respectively establishing a first complex sinusoidal curve and a second complex sinusoidal curve, and determining frequency components of the signals to separate frequency contents of interference signals; obtaining a first processing signal based on a first-stage multiplication processing of a first complex sinusoidal curve and the signal and introducing inter-carrier interference; eliminating the interference signal according to a subcarrier frequency zero setting mode to obtain a second processing signal; and in the case that the second processed signal is processed by inverse fast Fourier transform, eliminating the intercarrier interference based on a second-stage multiplication process of a second complex sinusoid and the second processed signal.

According to a preferred embodiment, the communications satellite is further configured to: aligning a frequency of the interfering signal with a subcarrier frequency center of the communication channel; acquiring the frequency delta f of a fast Fourier transform filter bank closest to the frequency of the interference signal; and eliminating the interference signal according to a mode of setting the frequency delta f of the fast Fourier transform filter bank corresponding to the subcarrier frequency to zero.

According to a preferred embodiment, the communications satellite is further configured to: configuring a filter bank having a number of different filtering levels, and each filtering level comprising at least a low-pass channel and a high-pass channel, the low-pass channel and the high-pass channel each configuring at least one set of discrete wavelet transformers, wherein: acquiring sub-bands of a plurality of different frequency bands based on a plurality of filtering levels of the filter bank; the signals contained in the sub-bands can be decomposed into a plurality of different time-frequency spaces through discrete wavelet transform processing so as to separate the frequency content of the interference signals.

According to a preferred embodiment, the base station comprises at least a coding processor, a first modulation processor and a filtering processor, and is configured to process its received signal as follows: the coding processor at least carries out coding processing on the signals according to a mode of carrying out common processing on BCH coding processing, RS coding processing and convolutional coding processing so as to obtain coded signals; the first modulation processor performs modulation processing on the coded signal and transmits the modulated signal to the filtering processor at a first carrier frequency, wherein: under the condition that a first path of signal and a second path of signal with a set code element period between the first path of signal and the second path of signal are obtained based on the coded signal, a first modulation signal and a second modulation signal are respectively obtained based on at least the first path of signal and the second path of signal; and acquiring a third modulation signal meeting the first carrier frequency by the first modulation signal and the second modulation signal according to a mode of sequentially executing modulation processing and filtering processing.

According to a preferred embodiment, the encoded signal is obtained as the first path signal and the second path signal by performing serial-to-parallel conversion processing, and the first path signal or the second path signal may be separated from each other by a set symbol period by performing delay processing, where: under the condition that the first path of signal executes the delay processing, the first path of signal acquires the first modulation signal according to a mode of executing first-stage filtering processing and second-stage modulation processing in sequence, and the second path of signal acquires the second modulation signal according to a mode of executing the first-stage filtering processing and the second-stage modulation processing in sequence; and the first modulation signal and the second modulation signal acquire the third modulation signal in a mode of sequentially executing second-stage modulation processing and second-stage filtering processing. The first stage of filtering processing is performed by a raised cosine roll-off filter and the second stage of filtering processing is performed by a band pass filter. After the signal is subjected to the first-stage filtering processing, a periodic continuation phenomenon occurs in a signal frequency spectrum due to a subsequent modulation resampling process, intersymbol interference is generated finally, sidelobe interference exists in a frequency range of the modulated signal, the quality of the modulated signal is reduced, and the error rate is increased. The second stage of filtering processing can reduce the size of a side lobe in a frequency range to a specified decibel range, and can eliminate intersymbol interference. The third modulated signal generated by the modulation has a lower average power ratio peak value than the prior art. And the discontinuity of any phase of the first path of signal and the second path of signal can be effectively and smoothly removed through the first-stage filtering processing.

According to a preferred embodiment, the encoding process comprises at least the following steps: the signals are processed by the BCH coding to generate BCH codes, and the BCH codes and the sent information frames jointly form a plurality of information subframes with set bits according to a mode of supplementing zero codes; and under the condition that the information subframe is subjected to synchronous scrambling processing, RS coding processing and convolutional coding processing in sequence to obtain processed data, the processed data at least forms a complete modulation data frame together with carrier synchronization bits, a guide sequence, a unique code and a frame tail.

According to a preferred embodiment, the base station further comprises a second modulation processor and a frequency conversion module, the filtering processor comprises at least a first filter and a second filter, wherein: the filtering processor performs filtering processing on the received signals according to the mode that the first filter performs the first-stage filtering processing on the first path of signals and the second filter performs the second-stage filtering processing on the third modulation signals; under the condition that the third modulation signal is transmitted to the second modulation processor through the filtering processor, the second modulation processor transmits the signal received by the second modulation processor to the frequency conversion module at a second carrier frequency; and the frequency conversion module converts the received signal into a set radio frequency output frequency.

According to a preferred embodiment, the first filter is a raised cosine roll-off filter and the second filter is a band-pass filter; the first-stage modulation processing is quadrature modulation processing, and the second-stage modulation processing is in-phase modulation processing.

According to a preferred embodiment, the communication satellite further comprises an interference detector configured to calculate an average power of a signal to determine whether an interfering signal is present in a subband, and a demodulator configured to demodulate an output signal of the interference suppressor, wherein: the interference suppressor is further configured to obtain a frequency Δ f of a fast fourier transform filter bank closest to a frequency of the interfering signal, the frequency of the first complex sinusoid being Δ f and the frequency of the second complex sinusoid being- Δ f.

According to a preferred embodiment, said first complex sinusoid is formulated

Defining, said second complex sinusoid being formulated

Defining; the generator polynomial of BCH coding is g (x) x¹⁰+x⁹+x⁸+x⁶+x⁵+x³+ 1; the generator polynomial of RS coding is g (x) x⁸+x⁴+x³+x²+ 1; the generator polynomials of the two output ports of the convolutional coding are g1(x) ═ x respectively⁶+x⁵+x⁴+x³+1 and g2(x) ═ x⁶+x⁴+x³+x¹+ 1; the scrambling code period and polynomial of the synchronous scrambling process are respectively 2¹⁵-1 and 1+ X¹⁴+X¹⁵(ii) a Wherein, F_sRepresenting the sampling frequency, N is the number of fast fourier transform sample points.

The invention has the beneficial technical effects that:

(1) in the iterative process, each narrow-band interference signal is aligned with the center of the subcarrier frequency of a communication channel, so that the generation of the inter-carrier interference is caused. The narrowband interference will no longer be carried by the signal after the narrowband interference is aligned with the subcarrier frequency, and then the intercarrier interference is removed from the signal. Therefore, before decoding, the signal removes all narrow-band interference and any potential side lobes, thereby eliminating spectral leakage.

(2) The invention can eliminate the intersymbol interference through the digital shaping filter, further can meet the Nyquist characteristic without the intersymbol interference, and simultaneously can smooth the waveform, further can accelerate the attenuation speed outside the frequency band of the modulation signal, and improve the frequency spectrum utilization rate. The modulation envelope can be made more rounded by processing through a band pass filter.

Drawings

FIG. 1 is a schematic diagram of the modular connectivity of a preferred narrowband satellite communications system of the present invention;

FIG. 2 is a schematic block diagram of a preferred base station of the present invention;

FIG. 3 is a schematic flow chart of a modulation process of a first preferred modulation processor of the present invention;

FIG. 4 is a schematic diagram of a modular construction of a preferred communication satellite of the present invention;

fig. 5 is a process flow diagram of a preferred interference suppressor of the present invention;

FIG. 6 is a block diagram of the encoding of a preferred RS code of the present invention;

FIG. 7 is a block diagram of the encoding of a preferred convolutional code of the present invention; and

fig. 8 is a process flow diagram of a preferred encoding processor of the present invention.

List of reference numerals

1: communication satellite 2: base station

101: the interference detector 102: the interference suppressor 103: demodulator

104: signal preprocessor

201: the encoding processor 202: the first modulation processor 203: filtering processor

204: the second modulation processor 205: frequency conversion module

102 a: offset logic circuit 102 b: the first multiplication circuit 102 c: windowing circuit

102 d: the first fast fourier transform circuit 102 e: interference suppression circuit

102 f: inverse fast fourier transform circuit 102 g: the correction circuit 102 h: second multiplying circuit

102 i: second fast Fourier transform circuit

2 a: the first base station 2 b: second base station

203 a: first filter 203 b: second filter

202 a: first modulator 202 b: second modulator 202 c: third modulator

Detailed Description

The following detailed description is made with reference to the accompanying drawings.

Example 1

The invention provides a narrow-band satellite communication system, which at least comprises at least one communication satellite 1 and a plurality of base stations 2 which are communicated with each other. For example, as shown in fig. 1, a narrowband satellite communication system includes a communication satellite 1, a first base station 2a, and a second base station 2 b. The first base station 2a may transmit the data signal it receives to the communication satellite 1, which in turn relays it to the second base station 2b via the communication satellite 1. Similarly, the second base station 2b may relay the data signal received by the second base station to the first base station 2a via the communication satellite 1. The first base station 2a and the second base station 2b may individually have their own gateways, and all gateways may be communicatively coupled to each other through a common network.

Preferably, as shown in fig. 2, the base station 2 includes at least a coding processor 201, a first modulation processor 202, a filtering processor 203, a second modulation processor 204 and a frequency conversion module 205. The encoding processor 201 is configured to encode the original data information received by the base station 2 and transmit the encoded digital signal to the first modulation processor 202 according to a set code rate. The first modulation processor 202 is used to modulate the digital signal to transition to a set first carrier frequency. The digital signal modulated by the first modulation processor 202 is transmitted to the filtering processor 203 for filtering. The digital signal filtered by the encoding processor 201 of the filtering processor 203 is transmitted to the second modulation processor 204 to be modulated again so as to be converted to the set second carrier frequency. The digital signal having the second carrier frequency is transmitted to the frequency conversion module 205. The frequency conversion module 205 is configured to convert the digital signal processed by the second modulation processor 204 to a set frequency for transmission so as to upload the digital signal to the communication satellite 1.

Preferably, the encoding processor 201 may be configured to encode the raw data information based on a cyclic coding or a convolutional coding. The first modulation processor 202 and the second modulation processor 204 may modulate the digital signal based on a combination of one or more of digital phase modulation, multilevel digital phase modulation, phase shift keying modulation, quadrature phase keying modulation, offset quadrature phase shift keying modulation. The filtering processor 203 may be a digital shaping filter, and the digital shaping filter may eliminate inter-symbol interference, so as to satisfy the nyquist characteristic without inter-symbol interference, and may also smooth the waveform, so as to accelerate the out-of-band attenuation rate of the modulated signal, and improve the spectrum utilization rate.

Preferably, the frequency conversion module 205 may be a programmable phase-locked loop chip, and may convert the modulation signal to a set radio frequency output frequency range by configuring parameters of a frequency division register of the phase-locked loop chip, and may divide the available frequency spectrum into a plurality of carrier channels at equal frequency intervals by setting a frequency division interval. Dividing the frequency spectrum into multiple channels can improve the utilization rate of the frequency spectrum. For example, if the available frequency band is 100.0000MHz to 100.0100MHz, the frequency band may be divided into 100 channels if the frequency division interval is 100 Hz. The narrowband signal can be obtained through the frequency conversion module. Thereby realizing narrowband multichannel communication between the base station 2 and the communication satellite 1.

Preferably, the base station 2 can send the original data to the first modulation processor 202 for modulation processing at a code rate of 600bps after the encoding processing by the encoding processor. The first modulation processor 202 transmits the carrier frequency of 15KHz to the filtering processor 203 for filtering processing. The second modulation processor 204 re-modulates the 15KHz modulated signal so that it is transmitted to the frequency conversion module 205 at a carrier frequency of 10.685 MHz.

Preferably, as shown in fig. 3, the first modulation processor 202 is further configured to perform modulation processing on the coded signal processed by the coding processor 201 according to the following operation:

s1: the coded signal is processed by serial-to-parallel conversion to generate a first path of signal and a second path of signal, wherein the first path of signal and the second path of signal are separated from each other by a set code element period in a delay processing mode.

Specifically, after the encoded signal is processed by serial-to-parallel conversion to generate a first path of signal and a second path of signal, the code rate of each of the first path of signal and the second path of signal is one half of the code rate of the encoded signal. The first path of signals can be transmitted in a serial transmission mode, and the second path of signals can be transmitted in a parallel transmission mode. The set symbol period may be one-half symbol period. After any one of the first path of signal or the second path of signal is subjected to delay processing of half symbol period, the first path of signal and the second path of signal can be staggered by half symbol period.

S2: under the condition that the first path of signal is delayed for half a symbol period, the first path of signal and the second path of signal are respectively transmitted to the filtering processor 203 for filtering processing in a one-to-one correspondence manner, wherein the filtering processor 203 at least comprises a first filter 203a and a second filter 203b, and the first path of signal and the second path of signal are transmitted to the first filter 203a for filtering processing in a one-to-one correspondence manner. The first stage filtering process may be performed by the first filter 203 a.

Specifically, the first filter 203a is a digital shaping filter. The digital shaping filter can be a raised cosine roll-off filter, and the shaping waveform of the coded signal can be changed by controlling the roll-off coefficient, so that the influence caused by sampling timing errors can be reduced. The frequency response h (f) of the raised cosine roll-off filter can be expressed by the following formula:

wherein, the corresponding time domain waveform function is:

wherein the symbol period T_s＝1/2f_N，f_NIs the quintesla frequency. Alpha is a roll-off factor which determines the shape of H (f), alpha is in [0, 1 ]]Taking a value between. When α is large, the time domain waveform attenuates the block and the oscillation fluctuation is small, which is advantageous for reducing the influence of intersymbol interference and timing error, but the occupied band becomes wide, the band use ratio decreases, and the influence of the in-band noise on the signal increases accordingly. When alpha is smaller, the frequency band utilization rate is increased, the influence of in-band noise is weakened, but the waveform oscillation fluctuation is increased, the influence on intersymbol interference and timing error is increased, and finally the error rate is causedAnd (4) improving. Preferably, the roll-off factor α is selected to be 0.5, and the order of the digital shaping filter is set to 32.

S3: the first path of signal and the second path of signal after being filtered by the first filter 203a are respectively transmitted to the first modulation processor 202 for modulation processing.

Specifically, the first modulation processor 202 includes at least a first modulator 202a, a second modulator 202b, and a third modulator 202 c. The first modulator 202a is a quadrature modulator and the second modulator 202b and the third modulator 202c are both in-phase modulators. The first path of signal is transmitted to the first modulator 202a for quadrature modulation processing to obtain a first modulation signal, and the second path of signal is transmitted to the second modulator for in-phase modulation processing to obtain a second modulation signal. The first modulation signal and the second modulation signal are both uniformly transmitted to the third modulator 202c for in-phase modulation processing to obtain a third modulation signal. A first level of modulation processing may be performed by the first modulator 202 a. The second stage modulation process may be performed by second modulating it 202b and the third modulator 202 c.

S4: the third modulated signal is transmitted to the second filter 203b to be filtered to complete the modulation process of the encoded signal.

Specifically, the second filter 203b is a band-pass filter that allows signals within a specific frequency range to pass through, and can attenuate signals outside the specific frequency range to a very low level. The coded signal is based on the modulation resampling process of the modulation module, so that the signal frequency spectrum can generate period prolongation to generate intersymbol interference, and further the error code probability of the modulation module is increased. Preferably, the order of the band pass filter may be set to 64 orders. The modulation envelope can be made more rounded by processing through a band pass filter. The second stage filtering process may be performed by the second filter 203 b.

Example 2

This embodiment is a further improvement of embodiment 1, and repeated contents are not described again.

Referring again to fig. 1, the first base station 2a may transmit the first signal to the communication satellite 1, and then relay the first signal to the second base station 2b through the communication satellite 1. When the second base station 2b transmits the second signal to the communication satellite, the second base station 2b can simultaneously receive the echo of the second signal and the first signal as a combined signal. Likewise, the first base station 2a can simultaneously receive the echo of the first signal and the second signal as a combined signal. The first base station 2a and the second base station 2b may remove interference due to echo by an echo cancellation method, by which demodulation of the first signal and the second signal may be facilitated. The first signal and the second signal are interfered by different environments and different degrees in the transmission process, so that the combined signal received by the base station at least needs to be transmitted, the echo of the transmitted signal and the noise floor. The transmission signal to be transmitted refers to a first signal or a second signal to be transmitted between the first base station and the second base station. The noise floor refers to the sum of all noise sources and unwanted signals in the communication system, i.e. any other signal than the transmitted signal.

Preferably, as shown in fig. 4, the communication satellite 1 comprises at least a signal preprocessor 104. The signal preprocessor 104 includes several filters to perform decomposition of the combined signal, analysis, or suppression of interfering signals. The signal preprocessor 104 is configured to process the combined signal as follows:

s1: the combined signal is subjected to a fast fourier transform process to determine the frequency content of the combined signal. For example, the signal preprocessor 104 may include a fast fourier transformer to which the combined signal is transmitted to enable fast fourier transformation of the combined signal. The fast fourier transformer may add the product of the combined signal samples to a complex sinusoid of frequency to obtain a frequency domain representation of the combined signal, wherein the processing of the fast fourier transformer may be represented as:

x_nare digital samples of the combined signal. N is the total number of samples being processed.

S2: the output signal after the fast Fourier transform processing is decomposed to obtain a plurality of decomposed signals of different time-frequency spaces. In particular, the output signal may be transmitted into a filter bank, which may comprise several different filtering stages. Each filtering level may include a low pass channel and a high pass channel, and both the low pass channel and the high pass channel are configured with a set of discrete wavelet transformers, respectively. The output signal can be divided into a plurality of sub-bands with different frequency bands through different filtering grades, and signals contained in different sub-bands can be decomposed into a plurality of different time-frequency spaces through discrete wavelet transform processing of a discrete wavelet transformer, so that the time-frequency content of the transmitted signal can be separated from the frequency content of the interference signal.

Preferably, referring again to fig. 4, the communication satellite 1 comprises at least an interference detector 101, an interference suppression module 102 and a demodulator 103. The communication satellite 1 may have a signal receiving module, such as an antenna, which in turn is capable of receiving signals transmitted by the base station 2 or other signal terminals. The interference detector 101 is configured to perform interference detection on signals in a plurality of different subbands output by the signal preprocessor 104, so as to determine frequencies corresponding to all interference sources existing in the combined signal. The interference suppression module 102 is configured to perform, for example, filtering processing on the interference source determined by the interference detector, so as to eliminate the interference. The demodulator 103 is used to demodulate the signal for further transmission of the signal. Preferably, the interference detector 101 may calculate the average power of the combined signal and set a standard threshold. When the actual power of the combined signal determined by the interference detector analysis is higher than the set standard threshold, it can be judged that interference exists. The setting of the criterion threshold can be determined in advance by advance simulation of the interfering signal.

Preferably, as shown in fig. 5, the interference suppression module 102 may include an offset logic circuit 102a, a first multiplication circuit 102b, a windowing circuit 102c, a first fast fourier transform circuit 102d, an interference cancellation circuit 102e, an inverse fast fourier transform circuit 102f, and a signal correction circuit 102 g. The offset logic 102a is used to associate the frequency of the interference signal with the communication channelIs aligned, the offset logic is able to determine the difference between the frequency of the interfering signal and the center frequency of the fft filterbank frequency af, and the offset logic may determine one or more of the fft filterbank frequencies that are closest to the frequency of the interfering signal. Preferably, the offset logic circuit is also able to create a first complex sinusoid on the received signals for performing the multiplication of the analog signals with each other in the first multiplication circuit 102 b. The frequency of the first complex sinusoid may be represented by- Δ f, and the first complex sinusoid may be represented by the following equation

(N-0, 1, …, N-1). F_sRepresenting the sampling frequency. N is the number of fast fourier transform sample points. The first multiplier circuit 102b may receive the first complex sinusoid from the offset logic and a combined signal containing sampled samples of the interfering signal. The first multiplication circuit 102b multiplies the first complex sinusoid with the sampled samples to obtain a first processed signal. Meanwhile, the first-stage multiplication processing of the first complex sinusoid and the sample can also introduce the intercarrier interference into the first multiplication circuit 102 b.

Preferably, the windowing circuit 102c is configured to receive the output of the first multiplying circuit 102b and perform windowing thereon. The windowing circuit may window the signal using, for example, a hanning window function, a rectangular window function or a butley window function. The output of the first multiplication circuit 102b can be limited to the main lobe by the windowing process. The first fast fourier transform circuit 102d can receive the output of the windowing circuit 102c and perform fast fourier transform processing thereon to generate a fast fourier transform signal. The interference cancellation circuit 102e can receive the demodulated fast fourier transform signal processed by the first fast fourier transform circuit 102d, and the interference cancellation circuit 102e can remove the subcarrier frequency determined by the offset logic circuit 102a in calculating Δ f from the fast fourier transform signal to obtain a second processed signal. In particular toThe sub-carrier frequency involved in the calculation of Δ f, and the interference cancellation circuit 102e can set the frequency of the fft filter bank corresponding to the sub-carrier frequency to zero. Since the frequency of the interference signal has already been processed by the offset logic circuit 102a to be aligned with the frequency center of the subcarrier, the frequency of the current subcarrier is set to zero by the interference cancellation circuit 102e, so that the interference signal is cancelled. Preferably, the second processed signal can be transmitted to the inverse fast fourier transform circuit 102f and subjected to an inverse fast fourier transform process to produce time-domain sample samples. Preferably, the correction circuit 102g is configured to generate a ramp signal having a frequency equal to Δ f, which may be passed through a second complex sinusoid

(N-0, 1, …, N-1). So that the correction circuit 102g can eliminate the inter-carrier interference. Specifically, the second complex sinusoid generated by the correction circuit 102g and the output signal generated by the inverse fast fourier transform circuit 102f are simultaneously transmitted to the second multiplication circuit 102h for the second-stage multiplication to eliminate the intercarrier interference. Preferably, the output signal of the second multiplying circuit 102h can be transmitted to the second fast fourier transform circuit 102i to be fast fourier transformed again to perform demodulation processing on the signal. The output signal of the second fast fourier transform circuit 102i is finally transmitted to the demodulator 103 for decoding processing. Preferably, the first fast fourier transform circuit 102d and the second fast fourier transform circuit 102i together define a fast fourier transform filter bank.

Preferably, in an iterative process, each narrowband interfering signal is aligned with the center of the subcarrier frequency of the communication channel, which results in the generation of intercarrier interference. The narrowband interference will no longer be carried by the signal after the narrowband interference is aligned with the subcarrier frequency, and then the intercarrier interference is removed from the signal. Therefore, before decoding, the signal removes all narrow-band interference and any potential side lobes, thereby eliminating spectral leakage.

Example 3

This embodiment is a further improvement of the foregoing embodiment, and repeated contents are not described again.

Preferably, as shown in fig. 8, the encoding processor 201 is further configured to perform encoding processing on the signal as follows:

s1: and combining a BCH code generated after the signal is subjected to BCH coding processing and a transmission information frame into an information subframe with set bits, wherein when the bit length of the information subframe does not meet the set bit length, the information subframe is supplemented in a mode of supplementing 0 codes.

Specifically, a signal with a bits is subjected to BCH (b, a) coding to obtain a BCH code output with b bits, and the BCH code with b bits and a transmitted information frame are combined into an information subframe with c bits. For example, b may be set to 31 and c may be set to 223.

Preferably, the generator polynomial of the BCH code may be represented by the formula g (x) ═ x¹⁰+x⁹+x⁸+x⁶+x⁵+x³And + 1.

S2: the information sub-frame is processed by synchronous scrambling. When a continuous long 0 code or a continuous 1 code is transmitted in digital communication, it is interfered by an electromagnetic field existing in a spatial transmission channel, thereby generating an error code. The scrambling code is an n-pseudo random sequence, the occurrence times of 0 codes and 1 codes can be balanced by adding linear feedback of the n-sequence and data, the data can be converted into approximate white noise, and the fading and the error rate of space signals are reduced. Specifically, the scrambling code period of the synchronous scrambling process may be set to 2¹⁵-1, polynomial 1+ X¹⁴+X¹⁵The n-sequence with the start register value of 1001_0101_0000_000 scrambles all the framed data.

S3: and sequentially carrying out RS coding and convolutional coding on the sub-frames subjected to scrambling processing. For example, specific parameters of RS encoding can be configured as follows: the code length n is 255, the supervision end k is 223, and the polynomial g (x) x is generated⁸+x⁴+x³+x²+1. The convolutional code has 1 input port and 2 output ports, and the two output ports respectively correspond to a generator polynomial g1(x) ═ x⁶+x⁵+x⁴+x³+1 and g2(x) ═ x⁶+x⁴+x³+x¹+1。

Preferably, fig. 6 shows a coding block diagram of the RS code, where the polynomial h (x) of the input information is removed g (x) to obtain a remainder r (x), and r (x) is spliced to the tail of h (x) to obtain an output codeword. Specifically, h (x) is directly output through the gate A, h (x) enters the RS check circuit, the output of the check circuit is disconnected at the moment, and after all 223 elements enter the check circuit, data stored in a plurality of registers are RS check bits. At this time, the output of the check circuit is opened, the check bit is output, and r (x) is spliced to the tail of h (x), so that 255-bit RS encoding data is formed.

Preferably, fig. 7 shows an encoding block diagram of a convolutional code, where the code rate is 3/4 bits/symbol, the constraint length is 7 bits, and the concatenation vector G1 is 1111001 and G2 is 1011011. The output is determined by the puncturing scheme, where C1: 101, C2: 110, 1 denotes a symbol that is transmitted and 0 denotes a symbol that is not transmitted. The shift register is used for storing bit information, and the output code stream sequence enters the shift register and is divided into two branches at the same time, and two paths of XOR operation are respectively carried out. The polynomial of the first branch is g1(x), and the polynomial of the second branch is g2 (x). The first branch and the second branch can feed the operation results into the punching unit, wherein the operation results of the two branches alternately enter the punching unit, the punching unit shifts and divides the continuous 6-bit data into a group, and the entering sequence of each group is C₁(1)C₂(1)C₁(2)C₂(2)C₁(3)C₂(3) … are provided. Finally, the puncturing unit performs convolutional coding 3/4 puncturing output on a group of data according to the puncturing scheme, and the sequence of the output is C₁(1)C₂(1)C₂(2)C₁(3)…。

S4: and the data generated after the convolutional coding, the carrier synchronization bit, the pilot sequence, the unique code and the frame tail form a complete modulation data frame. For example, the data generated after convolutional coding can be combined with 320 bit carrier synchronization bits, 160 bit pilot sequence, 64 bit unique code and 64 bit frame tail to form a complete modulated data frame. By organically combining the coding modes, the formed combined coding mode has low error rate, high confidentiality and high spectrum utilization rate.

It should be noted that the above-mentioned embodiments are exemplary, and that those skilled in the art, having benefit of the present disclosure, may devise various arrangements that are within the scope of the present disclosure and that fall within the scope of the invention. It should be understood by those skilled in the art that the present specification and figures are illustrative only and are not limiting upon the claims. The scope of the invention is defined by the claims and their equivalents.

Claims

1. A base station (2), characterized in that the base station (2) frequency-converts its received signals to a number of mutually different radio frequency output frequencies for establishing a multi-channel transmission with a communication satellite (1) with respect to each other, the base station (2) comprising at least a coding processor (201), the base station (2) being configured to process its received signals in the following manner:

the encoding processor (201) performs encoding processing on the signal at least according to a mode of performing common processing on BCH encoding processing, RS encoding processing and convolutional encoding processing to obtain an encoded signal;

the base station (2) further comprises a first modulation processor (202) and a filtering processor (203), the first modulation processor (202) modulating the encoded signal and transmitting to the filtering processor (203) at a first carrier frequency, wherein:

under the condition that a first path of signal and a second path of signal with a set code element period between the first path of signal and the second path of signal are obtained based on the coded signal, a first modulation signal and a second modulation signal are respectively obtained based on at least the first path of signal and the second path of signal;

and acquiring a third modulation signal meeting the first carrier frequency by the first modulation signal and the second modulation signal according to a mode of sequentially executing modulation processing and filtering processing.

2. The base station (2) of claim 1, wherein the encoded signal is obtained as the first signal and the second signal by performing a serial-to-parallel conversion process, and the first signal or the second signal is separated from each other by a set symbol period by performing a delay process, wherein:

under the condition that the first path of signal executes the delay processing, the first path of signal acquires the first modulation signal according to a mode of executing first-stage filtering processing and second-stage modulation processing in sequence, and the second path of signal acquires the second modulation signal according to a mode of executing the first-stage filtering processing and the second-stage modulation processing in sequence;

and the first modulation signal and the second modulation signal acquire the third modulation signal in a mode of sequentially executing second-stage modulation processing and second-stage filtering processing.

3. The base station (2) according to claim 2, wherein the filtering processor (203) comprises at least a first filter (203a) and a second filter (203b), and the filtering processor (203) performs the filtering processing on the received signal in a manner that the first filter (203a) performs the first filtering processing on the first path signal and the second filter (203b) performs the second filtering processing on the third modulation signal.

4. The base station (2) of claim 3, characterized in that the first filter (203a) is a raised cosine roll-off filter, the frequency response H (f) of which can be expressed by the following equation:

wherein, the corresponding time domain waveform function is:

wherein the code elementPeriod T_s＝1/2f_N，f_NAt the quintester frequency, α is a roll-off factor, which determines the shape of H (f), α is at [0, 1]Taking a value between.

5. Base station (2) according to claim 4, characterized in that said coding process comprises at least the following steps:

the signals are processed by the BCH coding to generate BCH codes, and the BCH codes and the sent information frames jointly form a plurality of information subframes with set bits according to a mode of supplementing zero codes;

and under the condition that the information subframe is subjected to synchronous scrambling processing, RS coding processing and convolutional coding processing in sequence to obtain processed data, the processed data at least forms a complete modulation data frame together with carrier synchronization bits, a guide sequence, a unique code and a frame tail.

6. The base station (2) of claim 5, wherein the base station (2) further comprises a second modulation processor (204) and a frequency conversion module (205), wherein:

in case the third modulated signal is transmitted to the second modulation processor (204) via the filtering processor (203), the second modulation processor (204) transmits its received signal to the frequency conversion module (205) at a second carrier frequency;

the frequency conversion module (205) converts the frequency of the received signal to a set radio frequency output frequency.

7. The base station (2) of claim 6, characterized in that the first modulation processor (202) comprises at least a first modulator (202a), a second modulator (202b) and a third modulator (202c), the first modulator (202a) being a quadrature modulator, the second modulator (202b) and the third modulator (202c) each being an in-phase modulator, the first level of modulation processing being performed by the first modulator (202a), the second level of modulation processing being performed by the second modulator (202b) and the third modulator (202 c);

the first-stage modulation processing is quadrature modulation processing, and the second-stage modulation processing is in-phase modulation processing.

8. The base station (2) according to claim 7, characterized in that the second filter (203b) is a 64 th order bandpass filter.

9. The base station (2) of claim 8,

the generator polynomial of BCH coding is g (x) x¹⁰+x⁹+x⁸+x⁶+x⁵+x³+1；

The generator polynomial of RS coding is g (x) x⁸+x⁴+x³+x²+1；

The generator polynomials of the two output ports of the convolutional coding are g1(x) ═ x respectively⁶+x⁵+x⁴+x³+1 and g2(x) ═ x⁶+x⁴+x³+x¹+1；

The scrambling code period and polynomial of the synchronous scrambling processing are respectively 2¹⁵-1 and 1+ X¹⁴+X¹⁵。