CN112420826A - Vertical pHEMT transistor structure and switch chip - Google Patents
Vertical pHEMT transistor structure and switch chip Download PDFInfo
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Abstract
The invention discloses a vertical pHEMT transistor structure and a switch chip. The transistor includes: the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the metalized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are all of a columnar structure, the axial direction of the metalized through hole is the same as the normal direction of the substrate, a source electrode, a grid electrode and a drain electrode are respectively arranged on the side wall of the barrier layer, the source electrode, the grid electrode and the drain electrode are horizontally or vertically arranged, and when the metalized through hole is vertically arranged, the grid electrode surrounds the columnar. The switch chip is formed by connecting a plurality of vertical pHEMT transistors in series or in parallel in the vertical direction. The transistor and the switch chip have the characteristics of high isolation, large power capacity, small volume, good integration, low power consumption, high efficiency and good broadband characteristics.
Description
Technical Field
The invention relates to the field of semiconductor chips, in particular to a vertical pHEMT transistor structure and a switch chip formed by a vertical pHEMT transistor stacking structure.
Background
Microwave switches are widely used in modern communication systems such as transceiver modules. The existing microwave switch has two technologies: one is a mechanical switch, and the on-off of a mechanical arm is controlled by an electric control to control the switch of a microwave channel; the other is a chip switch, and the on-off of a transistor in the chip is controlled by electric control to control the switch of a microwave channel.
The advantages of mechanical switches over chip switches: the isolation is high and can reach more than 60dB, and the chip switch can only reach about 20 dB. Therefore, the mechanical switch is widely applied to the fields of instruments and meters and the like which need high isolation, high sensitivity, precision measurement and the like.
The advantages of chip switches over mechanical switches: the volume is small, the integration is easy, and the switching speed is high. The chip switches have a transistor with the size of about 100 microns, so that a plurality of switches can be cascaded on a chip conveniently and can be integrated with other control circuits and microwave circuits. This is not done with mechanical switches. And because the chip switch is used for electrically controlling the on-off of the chip transistor to realize the microwave switch function, the speed is far higher than that of a mechanical switch. Mechanical switch switching requires about 100 milliseconds, while chip switches can achieve switching speeds within 10 ms. Therefore, the chip switch is widely applied to modern communication systems with high requirements on volume and integration, such as a multi-channel transceiver chip/module, 5G, Wifi and the like.
The on-chip switches may be implemented on a variety of types of chips, with different substrates, typically of the type GaAs, GaN, InP, bulk silicon CMOS-RF, SOI-RF, etc. The chip switch with the novel structure also comprises a Micro Electro Mechanical System (MEMS) chip switch.
Besides the MEMS chip switch, several other microwave switches have the same structure, and typically compound semiconductor switches such as GaAs, GaN, etc. are chip switches of pHEMT transistor type. The basic structure of this switch is a pHEMT transistor, which mainly includes a substrate and structures of gate, drain, source, etc., a typical GaAs pHEMT structure is shown in fig. 1, and a silicon-based compound semiconductor transistor is similar to this.
Referring to fig. 1, the undoped InGaAs layer forms a heterojunction with the AlGaAs layer at the interface, creating a two-dimensional electron gas. The gate controls the barrier height, and when the gate reaches a certain bias voltage, the two-dimensional electron gas tunnel passes through the barrier to form current between the source and the drain. To prevent current leakage into the GaAs substrate, an undoped GaAs/AlGaAs superlattice buffer layer is added.
The principle of the switching chip based on the pHEMT structure transistor is as follows: when no control voltage is applied to the gate, the barrier of the gate prevents the two-dimensional electron gas current of the source from flowing to the drain, and the switch is in an off state. When the control voltage is applied to the gate, the potential barrier of the gate is lowered, the two-dimensional electron gas current of the source is not blocked to flow to the drain any more, and the switch is in an open state. The capability of the grid control potential barrier for obstructing the flow of the two-dimensional electron gas is weaker than that of a mechanical arm of the mechanical switch, so that the isolation degree of the chip switch is far lower than that of the mechanical switch, and the application of the chip switch is seriously influenced.
The pHEMT transistor is a planar microwave structure manufactured on a chip, so the pHEMT transistor is a planar structure, mainly for facilitating the manufacturing process of a semiconductor chip, and the structural characteristics of the prior art are as follows: the gate is formed as a plurality of fingers inserted between the source and drain. A typical GaAs pHEMT transistor layout design is shown in fig. 2. A fully functional multi-tube stacked single pole double throw switch chip based on pHEMT architecture transistors is generally shown in fig. 3.
The structure described in fig. 3 employs a series-parallel combination of multiple tube stacks in order to improve overall isolation. However, in practical application, the isolation does not increase when the stack is stacked to a certain number, and can only be increased from 10dB to 20 dB. Moreover, the stacking causes an increase in power consumption of the switch and a decrease in efficiency. Therefore, in practical engineering applications, less than 10 transistors are stacked in the serial or parallel direction.
With the development of novel communication technologies such as 5G, Wifi6, CV2X and NBIoT, the requirement on the isolation of the chip switch is higher and higher, and the current chip switch technology has the following defects and needs to be solved urgently:
(1) the principle of a single microwave switch based on a pHEMT structure transistor is that a grid potential barrier controls the on-off of current between a source electrode and a drain electrode, and the isolation degree is low.
(2) By stacking multiple pHEMT-structure transistor switches in series or in parallel, overall isolation can be improved at the expense of increased power consumption and reduced efficiency, with limited improvement in isolation.
(3) The new communication system requires a chip switch with higher isolation, and maintains the advantages of low power consumption, chip integration and the like.
Disclosure of Invention
The invention aims to: in response to all or some of the above problems, a vertical pHEMT transistor structure is provided to improve transistor isolation. A switching chip based on vertical pHEMT transistors, which has high isolation, low power consumption and high integration, is also provided.
The technical scheme adopted by the invention is as follows:
a vertical pHEMT transistor structure comprising:
the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the metalized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are all of a columnar structure, the axial direction of the metalized through hole is the same as the normal direction of the substrate, and a source electrode, a grid electrode and a drain electrode are respectively arranged on the side wall of the barrier layer.
Furthermore, the source electrode, the grid electrode and the drain electrode are arranged horizontally or vertically.
Further, the source electrode, the grid electrode and the drain electrode are vertically arranged, and the source electrode, the grid electrode and the drain electrode respectively surround the side wall of the barrier layer partially or circularly. The terms "portion" and "perimeter" refer to the perimeter of the cross-section of the sidewall, not to the area of the sidewall.
Further, at least one circle of the side wall of the barrier layer is surrounded by the grid electrode.
Further, the buffer layer is an undoped GaAs/AlGaAs superlattice buffer layer, the channel layer is an undoped InGaAs channel layer, the isolation layer is an undoped AlGaAs isolation layer, the barrier layer is an N-type AlGaAs barrier layer, and the source electrode and the drain electrode are both formed by an N-type heavily doped GaAs contact layer.
Further, the columnar structure is a cylinder or a rectangular column.
A switch chip based on vertical pHEMT transistors is formed by vertically stacking a plurality of layers of vertical pHEMT transistors, wherein each two adjacent layers of vertical pHEMT transistors comprise an upper layer transistor and a lower layer transistor, a second isolation layer is arranged between the upper layer transistor and the lower layer transistor, and metalized through holes vertically penetrating through the second isolation layer are formed; the upper layer transistor and the lower layer transistor respectively adopt the vertical pHEMT transistor structure.
Further, the source electrode, the grid electrode and the drain electrode of the upper transistor and the lower transistor are vertically arranged, and the source electrode of one transistor is connected with the drain electrode of the other transistor through the metalized through hole on the second isolation layer between the upper transistor and the lower transistor.
Furthermore, the source electrodes, the grid electrodes and the drain electrodes of the upper layer transistor and the lower layer transistor are all horizontally arranged, and corresponding electrodes between the upper layer transistor and the lower layer transistor are connected through corresponding metalized through holes in the second isolation layer.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
1. the vertical pHEMT microwave transistor structure and the switch chip have high isolation, when the grid surrounds the side wall of the columnar transistor, the barrier control capability is strongest, and the isolation for opening and closing the microwave switch is highest. Compared with the traditional horizontally-arranged planar structure pHEMT microwave switch, the novel columnar structure transistor provided by the invention has the advantage that the isolation degree can be improved by more than 3 dB.
2. The center of the transistor with the columnar structure designed by the invention is a metalized through hole which is directly grounded, so that the transistor has good heat dissipation characteristic, and the microwave switch chip formed by the transistor has higher power capacity. Compared with the traditional horizontally-arranged planar structure pHEMT microwave switch, the power capacity of the transistor designed by the invention can be improved from 5W to more than 10W.
3. The transistor adopts a vertical stacking mode, when more switches are connected in series and in parallel, the area in the horizontal direction is not increased, but the height in the vertical direction is increased, and the integration of a chip and a module is better. Compared with the traditional horizontally-arranged planar structure pHEMT microwave switch, the novel columnar structure transistor provided by the invention has the area of 1mm2Reduced to 0.1mm2。
4. The switch chip has the characteristics of miniaturization and high integration, so that the interconnection distance between the switches is shorter, the broadband characteristics of the chip and the module are improved, the power consumption is reduced, the efficiency is improved, and particularly, the novel columnar structure transistor designed by the invention adopts the metallized through hole TSV, so that the interconnection distance between the switch units is further reduced. Compared with the traditional horizontally-arranged planar structure pHEMT microwave switch, the novel columnar structure transistor provided by the invention has the advantages that the broadband characteristic can cover a millimeter wave frequency band above 28GHz, the power consumption can be reduced from 1W to 0.5W, and the efficiency can be improved from 30% to 40%.
Drawings
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
fig. 1 is a conventional GaAs pHEMT substrate structure.
Fig. 2 is a prior art power transistor layout.
Fig. 3 is a structure diagram of a conventional multi-tube stacked single-pole double-throw switch chip based on pHEMT structure transistors.
Fig. 4 is a structural view of a vertical-structure pHEMT transistor in which source and drain electrodes are horizontally arranged.
Fig. 5 is a structural view of a horizontal-structured pHEMT transistor in which source, gate and drain are horizontally arranged.
Fig. 6 is a diagram of a pHEMT transistor series stack architecture.
Fig. 7 is a diagram of a parallel stack structure of pHEMT transistors.
Detailed Description
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification (including any accompanying claims, abstract) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
A vertical pHEMT transistor structure, the transistor structure comprising:
the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the periphery of the metalized through hole, and the axial direction of the metalized through hole is the same as the normal direction of the substrate; a source electrode, a grid electrode and a drain electrode are arranged on the side wall (obviously, the outer side) of the barrier layer, and the source electrode and the drain electrode are contact layers arranged on the side wall of the barrier layer, so that two-dimensional electron gas is distributed around the axial direction of the metalized through hole, the grid electrode can well control the barrier layer, the control capability of the on-off of current between the source electrode and the drain electrode is improved, and the isolation degree is improved. The metallized through hole is in a columnar structure along the normal direction of the substrate, and correspondingly, the structures of all layers (the buffer layer, the channel layer, the first isolation layer and the barrier layer are all in a columnar structure) at the periphery of the metallized through hole are also in a columnar structure which can be a cylinder or a rectangular column. The source electrode, the grid electrode and the drain electrode can be horizontally arranged or vertically arranged along the side wall of the barrier layer. For the case of vertical arrangement, the source, the gate and the drain may be partially arranged on the sidewall of the barrier layer, or may surround the sidewall of the barrier layer for one turn. Fig. 4 shows a transistor structure in which the source, the gate, and the drain are horizontally arranged, and the corresponding two-dimensional electron current flows horizontally from the source to the drain on the sidewall of the pillar, and fig. 5 shows a transistor structure (partially arranged) in which the source, the gate, and the drain are vertically arranged, and the corresponding two-dimensional electron current flows vertically from the source to the drain on the sidewall of the pillar. Under the condition that the grid electrodes are vertically arranged, the grid electrodes surround the cylindrical side wall for one circle, the barrier control capability is strongest, and the isolation degree of opening and closing of the switch is highest.
The vertical pHEMT microwave transistor structures are arrayed along the substrate normal direction, and then columnar vertical pHEMT transistors can be formed.
Example two
This embodiment discloses a vertical pHEMT microwave transistor structure, which includes:
around the periphery of the metalized through hole, sequentially arranging an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and an N-type AlGaAs barrier layer from the inner layer to the outer layer, wherein the axial direction of the metalized through hole is the same as the normal direction of the substrate; and a source electrode, a grid electrode and a drain electrode are arranged on the side wall of the N-type AlGaAs barrier layer, and the source electrode and the drain electrode are N-type heavily doped GaAs contact layers arranged on the side wall of the N-type AlGaAs barrier layer, so that the two-dimensional electron gas is axially distributed around the metalized through hole. The metalized through holes are in a columnar structure along the normal direction of the substrate, and correspondingly, all layers of structures on the periphery of the metalized through holes are also in a columnar structure which can be a cylinder or a rectangular column. The source electrode, the grid electrode and the drain electrode can be horizontally arranged along the side wall of the N-type AlGaAs barrier layer and can also be vertically arranged. For the case of vertical arrangement, the source electrode, the gate electrode and the drain electrode can be partially arranged on the side wall of the N-type AlGaAs barrier layer, and can also surround the side wall of the N-type AlGaAs barrier layer for a circle. As shown in fig. 4, the transistor structure with the source, the gate and the drain arranged horizontally, and the corresponding two-dimensional electron gas current flows horizontally from the source to the drain on the side wall of the pillar, as shown in fig. 5, the transistor structure with the vertical arrangement (partial arrangement), and the corresponding two-dimensional electron gas current flows vertically from the source to the drain on the side wall of the pillar.
EXAMPLE III
The embodiment discloses a pHEMT transistor vertical stacking structure, which is formed by vertically stacking a plurality of vertical pHEMT microwave transistor structures in the above embodiments on a substrate, wherein each two adjacent layers of vertical pHEMT microwave transistors each include an upper layer transistor and a lower layer transistor, the upper layer transistor and the lower layer transistor are vertically stacked (i.e., stacked along the normal direction of the substrate), a second isolation layer is arranged between the upper layer transistor and the lower layer transistor, and a metalized via hole for conducting electricity and heat is vertically arranged through the second isolation layer. The structures of the upper transistor and the lower transistor are the above pHEMT microwave transistor structures, respectively, and it should be noted that, although the vertical pHEMT microwave transistor structures of the above embodiments are both used, the structures of the upper transistor and the lower transistor may be the same or different, that is, the upper transistor and the lower transistor may correspond to the vertical pHEMT microwave transistor structures of different embodiments, respectively. Vertical stacking includes both series stacking and parallel stacking. The series stack is shown in fig. 6, i.e. the drain and source connections between the upper and lower transistors. The parallel stack is shown in fig. 7, i.e. source and source connections, drain and drain connections between the upper and lower transistors.
As shown in fig. 6, a stacked structure of two vertical pHEMT microwave transistor structures is shown, wherein a lower transistor and an upper transistor are grown on a GaAs substrate, a second isolation layer is disposed between the upper and lower transistors, and a metalized via hole is disposed through the second isolation layer. The upper transistor and the lower transistor are both in the following structures: arranging an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and an N-type AlGaAs barrier layer in sequence from the inner layer to the outer layer around the metalized through hole, wherein the axial direction of the metalized through hole is the same as the normal direction of the substrate; and a source electrode, a grid electrode and a drain electrode are arranged on the side wall of the N-type AlGaAs barrier layer, the source electrode, the grid electrode and the drain electrode are sequentially and vertically arranged (namely horizontally arranged) along the side wall of the AlGaAs barrier layer, and the drain electrode of the upper layer transistor is connected with the source electrode of the lower layer transistor through a metalized through hole on the isolating layer, so that series stacking is realized. In the specific implementation, the connection between the electrodes needs to be made through gold/copper wires, which belongs to the common general knowledge in the art and is not explained in detail herein, and the present invention mainly introduces the pillar transistor structure and the corresponding vertical stack structure.
As shown in fig. 7, a stacked structure of two vertical pHEMT microwave transistor structures is shown, wherein a lower transistor and an upper transistor are grown on a GaAs substrate, a second isolation layer is disposed between the upper and lower transistors, and a metalized via hole is disposed through the second isolation layer. The upper transistor and the lower transistor are both in the following structures: arranging an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and an N-type AlGaAs barrier layer in sequence from the inner layer to the outer layer around the metalized through hole, wherein the axial direction of the metalized through hole is the same as the normal direction of the substrate; and a source electrode, a grid electrode and a drain electrode are arranged on the side wall of the N-type AlGaAs barrier layer, the source electrode, the grid electrode and the drain electrode are sequentially and horizontally arranged (namely vertically arranged) along the side wall of the AlGaAs barrier layer, and the drain electrode of the upper transistor is connected with the drain electrode of the lower transistor, the grid electrode of the upper transistor is connected with the grid electrode of the lower transistor, and the source electrode of the upper transistor is connected with the source electrode of the lower transistor through corresponding metalized through holes on the isolation layer respectively, so that parallel stacking is realized.
The present embodiment is merely an example of a vertical stack, and in practical applications, the materials of the layers (the buffer layer, the channel layer, the isolation layer, and the barrier layer) may be different for different transistors, but the structures are the same.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed.
Claims (9)
1. A vertical pHEMT transistor structure comprising:
the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the metalized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are all of a columnar structure, the axial direction of the metalized through hole is the same as the normal direction of the substrate, and a source electrode, a grid electrode and a drain electrode are respectively arranged on the side wall of the barrier layer.
2. The vertical pHEMT transistor structure of claim 1, wherein the source, gate, and drain are arranged horizontally or vertically.
3. The vertical pHEMT transistor structure of claim 2, wherein the source, gate, and drain are vertically arranged, and the source, gate, and drain respectively surround a portion or a perimeter of a sidewall of the barrier layer.
4. The vertical pHEMT transistor structure of claim 3, in which at least the gate surrounds a perimeter of the barrier layer sidewalls.
5. The vertical pHEMT transistor structure of claim 1, wherein the buffer layer is an undoped GaAs/AlGaAs superlattice buffer layer, the channel layer is an undoped InGaAs channel layer, the isolation layer is an undoped AlGaAs isolation layer, the barrier layer is an N-type AlGaAs barrier layer, and the source and drain are both formed from N-type heavily doped GaAs contact layers.
6. The vertical pHEMT transistor structure of any one of claims 1 to 5, wherein the columnar structure is a cylindrical or rectangular column.
7. A switch chip based on vertical pHEMT transistors is characterized in that the switch chip is formed by vertically stacking a plurality of layers of vertical pHEMT transistors, each two adjacent layers of vertical pHEMT transistors comprise an upper layer transistor and a lower layer transistor, a second isolation layer is arranged between the upper layer transistor and the lower layer transistor, and metalized through holes vertically penetrate through the second isolation layer; the upper layer transistor and the lower layer transistor respectively adopt the vertical pHEMT transistor structure as claimed in any one of claims 1-5.
8. The vertical pHEMT transistor based switch chip of claim 7, wherein the source, gate, and drain of the upper and lower transistors are in a vertical arrangement, and wherein the source of one and the drain of the other are connected between the upper and lower transistors by a metalized via on the second isolation layer.
9. The vertical pHEMT transistor-based switch chip of claim 7, wherein the sources, gates, and drains of the upper and lower transistors are arranged horizontally, and corresponding electrodes between the upper and lower transistors are connected by corresponding metallized vias in the second isolation layer.
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