CN112420514A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

Info

Publication number
CN112420514A
CN112420514A CN202010397989.XA CN202010397989A CN112420514A CN 112420514 A CN112420514 A CN 112420514A CN 202010397989 A CN202010397989 A CN 202010397989A CN 112420514 A CN112420514 A CN 112420514A
Authority
CN
China
Prior art keywords
region
germanium
layer
semiconductor
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010397989.XA
Other languages
Chinese (zh)
Inventor
刘书豪
陈文彦
陈资宪
宋承融
王立廷
陈亮吟
张惠政
杨育佳
章勋明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112420514A publication Critical patent/CN112420514A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor device includes forming a gate stack over a first semiconductor region; removing a second portion of the first semiconductor region on one side of the gate stack to form a recess; growing a second semiconductor region starting from the recess; implanting a second semiconductor region with impurities; and performing a melting laser annealing on the second semiconductor region. The first portion of the second semiconductor region is melted at the melting laser annealing without melting the second portion and the third portion of the second semiconductor region on both sides of the first portion of the second semiconductor region.

Description

Method for forming semiconductor device
Technical Field
Embodiments of the present invention relate to semiconductor devices, and more particularly, to fusion laser annealing an epitaxial region of a finfet.
Background
In an integrated circuit, the source/drain contact plug is used to electrically couple to the source and drain regions, and the formation method may be epitaxy. The source/drain contact plugs are typically connected to the source/drain silicide regions. The method of forming the source/drain silicide regions includes etching a dielectric layer overlying the source/drain regions to form contact openings, wherein the etched dielectric layer may include a silicon nitride layer and an oxide layer on the silicon nitride layer. The contact openings thus expose the source/drain regions. An additional silicon nitride layer is conformally formed to cover the sidewalls and bottom of the contact opening. A second etch process is then performed to remove the bottom of the silicon nitride layer to expose the epitaxial source/drain regions. A metal layer is formed to extend into the contact opening, and an anneal is performed to react the metal layer with the source/drain region to form a silicide region of the source/drain. Then, metal is filled into the rest part of the contact opening to form source/drain contact plug.
Disclosure of Invention
Some embodiments of the invention provide methods of forming a semiconductor device comprising: forming a gate stack on a first portion of the first semiconductor region; removing a second portion of the first semiconductor region on one side of the gate stack to form a recess; growing a second semiconductor region starting from the recess; implanting a second semiconductor region with impurities; and performing a melting laser anneal on the second semiconductor region, wherein the first portion of the second semiconductor region is melted at the melting laser anneal without melting the second portion and the third portion of the second semiconductor region on both sides of the first portion of the second semiconductor region.
An embodiment of the invention provides a method for forming a semiconductor device, including: etching a portion of the semiconductor fin on one side of the gate stack to form a recess; epitaxially growing a silicon germanium layer, and the silicon germanium layer comprises: a first portion and a second portion respectively connected to and overlapping the first semiconductor strip and the second semiconductor strip; and a third portion connecting the first portion and the second portion; performing fusion laser annealing via a plurality of laser shots; and forming a silicide layer on the silicon germanium layer to contact the silicon germanium layer.
An embodiment of the present invention provides a semiconductor device including: an isolation region; a first semiconductor strip and a second semiconductor strip located between the isolation regions; a first semiconductor fin and a second semiconductor fin protruding above an upper surface of the isolation region, wherein the first semiconductor fin and the second semiconductor fin overlap the first semiconductor strip and the second semiconductor strip, respectively; a gate stack on an upper surface and sidewalls of each of the first and second semiconductor fins; a source/drain region on one side of the gate stack, wherein the source/drain region comprises silicon germanium, and the source/drain region comprises: a first portion and a second portion overlapping the first semiconductor strip and the second semiconductor strip, respectively; and a third portion between the first and second portions of the source/drain region; and silicide regions on and interfacing with the source/drain regions, wherein the interface and the source/drain regions comprise: a first point located in a first intermediate line between the first semiconductor strip and the second semiconductor strip, wherein the source/drain region has a first atomic germanium at the first point; and a second point located in a second intermediate line of the first semiconductor strip, wherein the source/drain region has a second atomic% germanium at the second point, and the second atomic% germanium is lower than the first atomic% germanium.
Drawings
Fig. 1-4, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, 9C, 10, 11A, 11B, 11C, 12, 13A, 13B, 13C, and 14 are perspective and cross-sectional views of intermediate stages in the formation of a finfet in some embodiments.
Figure 15 is a graph of atomic percent germanium versus depth in deposited silicon germanium regions, in some embodiments.
Fig. 16 is a graph of atomic% silicon and atomic% germanium versus depth in the vertical direction in some embodiments.
Fig. 17 is a graph of atomic% silicon and atomic% germanium versus depth in an oblique direction for some embodiments.
Figure 18 is a graph comparing germanium% in some embodiments.
Figure 19 is a process flow diagram of forming a finfet in some embodiments.
Description of reference numerals:
a, B, C: dot
D1: depth of field
5B-5B, 6B-6B, 9B-9B, 9C-9C, 13A-13A, 13B-13B: cutting line
10: wafer
11B/11C-11B/11C: reference profile
20: substrate
22: shallow trench isolation region
22A, 42S, 42S': upper surface of
22B: lower surface
24: semiconductor strip
24': raised fin
30: dummy gate stack
32: dummy gate dielectric layer
34: virtual grid
36: hard mask layer
38: gate spacer
40: depressions
42: epitaxial region
42',45, 66: dotted line
42A: lower part
42B: upper side part
42-I, 42-O, 44: region(s)
43: air gap
44': germanium concentration zone
46: contact etch stop layer
47A, 47B: arrow head
48, 82: interlayer dielectric layer
52: gate dielectric layer
54: grid electrode
56: gate stack
58: hard mask
60: contact opening
62: pre-amorphization implant region
64: annealing process
68: metal layer
70: metal nitride layer
71: metallized material
72: silicide region
76: fin-shaped field effect transistor
80: etch stop layer
74, 86: source/drain contact plug
88: gate contact plug
110, 112, 114, 116, 130, 132, 136, 138, 150A, 150B, 152: line segment
160, 162: spin coating glass zone
200: process flow
202, 204, 206, 208, 210, 212, 214, 216, 218, 220: process for the preparation of a coating
Detailed Description
The different embodiments or examples provided below may implement different configurations of the present invention. The following embodiments of specific components and arrangements are provided to simplify the present disclosure and not to limit the same. For example, the description of forming a first element on a second element includes embodiments in which the two are in direct contact, or embodiments in which the two are separated by additional elements other than direct contact. In addition, the structures of the embodiments of the present invention are formed on, connected to, and/or coupled to another structure, and the structures may directly contact the other structure, or additional structures may be formed between the structures and the other structure (i.e., the structures do not contact the other structure). Moreover, various examples of the invention may be repeated using the same reference numerals for brevity, but elements having the same reference numerals in the various embodiments and/or arrangements do not necessarily have the same correspondence.
Furthermore, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to refer to a relationship of one element to another in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.
Some embodiments provide transistors and methods of forming the same. In some embodiments, an intermediate stage of forming a transistor is illustrated. The following illustrates some variations of some embodiments. In the various figures and embodiments, like darts are used to designate like elements. In some embodiments, methods of forming finfet devices are used to illustrate the present concepts. Other types of transistors, such as planar transistors, may also employ the concepts of the embodiments of the present invention. In some embodiments of the present invention, a fusion laser anneal is employed to anneal epitaxial regions (e.g., source/drain regions) of the finfet and may melt at least some portions of the source/drain regions during the anneal. Germanium may be deposited on the surface region of the source/drain region due to the melting laser annealing, resulting in a higher atomic% of germanium in the surface region. The higher ge% reduces the schottky barrier between the source/drain regions and the silicide regions, thereby reducing the contact resistance of the source and drain regions.
Fig. 1-4, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, 9C, 10, 11A, 11B, 11C, 12, 13A, 13B, and 13C are cross-sectional and perspective views of intermediate stages in the formation of a finfet in accordance with some embodiments of the present invention. The process illustrated in these figures is also reflected in the process flow 200 illustrated in fig. 19.
Fig. 1 shows a perspective view of a starting structure formed on a wafer 10. The wafer 10 includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type or n-type impurities. Isolation regions, such as shallow trench isolation regions 22, may extend from the upper surface of the substrate 20 into the substrate 20. The portion of the substrate 20 between adjacent shallow trench isolation regions 22 may be considered as a semiconductor strip 24. In some embodiments, the upper surface of the semiconductor stripes 24 and the upper surface of the shallow trench isolation regions 22 may be substantially flush with each other. In some embodiments of the present invention, the semiconductor strips 24 are part of the initial substrate 20, and thus the semiconductor strips 24 are the same material as the substrate 20. In some other embodiments of the present invention, the semiconductor strips 24 are replacement strips formed by etching the substrate 20 between the sti regions 22 to form recesses, and epitaxially growing another semiconductor material in the recesses. In summary, the composition of the semiconductor stripes 24 is different from the semiconductor material of the substrate 20. In some embodiments, the composition of the semiconductor strips 24 is silicon germanium, silicon carbide, or a group III-V semiconductor compound material.
The shallow trench isolation region 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The pad oxide may also be a deposited silicon oxide layer formed by atomic layer deposition, high density plasma chemical vapor deposition, or chemical vapor deposition. The shallow trench isolation 22 may comprise a dielectric material on a pad oxide, wherein the dielectric material may be formed by a flowable chemical vapor deposition, spin-on coating, or the like.
As shown in fig. 2, the shallow trench isolation region 22 is recessed and the top of the semiconductor stripe 24 is raised above the upper surface 22A of the remaining portion of the shallow trench isolation region 22 to form a raised fin 24' of the semiconductor. Corresponding to process 202 in process flow 200 shown in fig. 19. The etching may be performed using a dry etching process in which hydrogen trifluoride and ammonia are used as etching gases. During the etching process, plasma may be generated. The etching process may also include argon. In other embodiments of the present invention, the method for recessing the sti regions 22 may employ a wet etching process. For example, the etch chemistry may include hydrofluoric acid.
In the above embodiments, the method of patterning the fin may be any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-aligned processes that produce a pattern pitch that is smaller than that obtained using a single direct lithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. Spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers (or cores) are used to pattern the fins.
As shown in fig. 3, dummy gate stack 30 is formed to extend over the top surface and sidewalls of raised fin 24'. Corresponding to process 204 in process flow 200 shown in fig. 19. Dummy gate stack 30 may include a dummy gate dielectric layer 32 and a dummy gate 34 over dummy gate dielectric layer 32. For example, the dummy gate 34 may be formed of polysilicon, or other materials. Each of the dummy gate stacks 30 may also include one or more hard mask layers 36 on the dummy gate 34. The hard mask layer 36 may be composed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 30 may override the single or multiple raised fins 24' and/or the shallow trench isolation region 22. The longitudinal direction of the dummy gate stack 30 is perpendicular to the longitudinal direction of the raised fins 24'.
Gate spacers 38 are then formed on the sidewalls of the dummy gate stacks 30. In some embodiments of the present invention, the gate spacer 38 is composed of a dielectric material such as silicon nitride, silicon carbonitride, or the like, and may have a single layer structure or a multi-layer structure including a plurality of dielectric layers.
An etching step is then performed to etch the portion of raised fin 24' not covered by dummy gate stack 30 and gate spacer 38, resulting in the structure shown in fig. 4. The recess step may be non-isotropic, thus protecting and not etching the portion of raised fin 24' directly under dummy gate stack 30 and gate spacer 38. In some embodiments, the upper surface of the recessed semiconductor stripes 24 may be lower than the upper surface 22A of the shallow trench isolation region 22. Thus, the recess 40 is formed between the shallow trench isolation regions 22. The recess 40 is located on both sides of the dummy gate stacks 30, and may include portions lower than the upper surface of the shallow trench isolation 22 and portions higher than the upper surface of the shallow trench isolation 22 and located between the adjacent dummy gate stacks 30.
An epitaxy process is then performed to form an epitaxial lower portion 42A, which may be selectively grown from the recess 40 to obtain the structure of fig. 5A. Corresponding to process 206 in process flow 200 shown in fig. 19. In some embodiments, epitaxial lower portion 42A comprises silicon germanium or silicon. In some embodiments of the present invention, the out-delay may be performed by in-situ doping a p-type dopant, such as boron or indium, into the epitaxial lower portion 42A. After the epitaxial lower portion 42A completely fills the recess 40, the epitaxial lower portion 42A begins to laterally expand and a crystal plane may be formed. Adjacent epitaxial regions 42 begin to merge with one another. In this way, an extended lower portion 42A is formed, the upper surface of which is wavy. The lower portion 42A of the epitaxy may sometimes be considered as or comprise part of layer L1 of epitaxial region 42 (see fig. 6A).
In some embodiments of the present invention, epitaxial lower portion 42A includes silicon germanium at a first atomic percent germanium (which may be between about 0% and about 40%). The ge% from the bottom to the top of the epitaxial lower portion 42A may be constant or graded (increasing from bottom to top).
Fig. 5B is a cross-sectional view of the structure shown in fig. 5A, wherein the cross-sectional view is from a vertical plane containing section line 5B-5B in fig. 5A. In some embodiments shown in fig. 5B, the location of the raised fins 24 'is not in the plane shown, and dashed lines are used in the drawings to indicate the relative location of the raised fins 24' and the extended lower portion 42A.
Fig. 6A shows continued growth of epitaxial region 42. Corresponding to process 208 in process flow 200 shown in fig. 19. Epitaxial region 42 includes an upper portion 42B and a lower portion 42A. Epitaxial upper portion 42B may comprise silicon germanium and may or may not be doped with p-type impurities such as boron, indium, gallium, or the like upon epitaxy. The upper portion 42B may sometimes be considered or comprise part of the layer L2 of the epitaxial region 42. The terms layer L1 and layer L2 are used to separate the lower ge% portion and the upper ge% portion of epitaxial region 42, respectively. It should be understood that the interface between layers L1 and L2 may be lower than the illustrated position (such as the position shown by dashed line 42'). In some embodiments of the present invention, the second germanium% of the upper portion 42B is higher than the first germanium% of the lower portion 42A. For example, the second germanium% may be between about 40% to about 65%. For example, the difference between the atomic% of the upper portion 42B and the lower portion 42A may be higher than about 20%. The second ge% from the bottom to the top of the epitaxial upper portion 42B may be constant or graded (increasing). In some embodiments, upper portion 42B includes a first portion having a graded (and gradually increasing) germanium percentage (e.g., gradually increasing from about 30% to about 50%), and a second portion over the first portion, and the second portion has a uniform germanium percentage (e.g., between about 50% to about 60%). Fig. 15 shows the elemental% of epitaxial region 42, where segment 152 shows upper portion 42B having increasing germanium and segment 150B shows upper portion 42B having constant germanium, in some embodiments of the present invention. The upper surface of the upper portion 42B may be flat as shown in fig. 6A. In the illustration, the epitaxial regions 42 may instead be considered source/drain regions.
FIG. 6B shows a cross-sectional view of the structure shown in FIG. 6A, wherein the cross-sectional view is from a vertical plane containing section line 6B-6B in FIG. 6A. In some embodiments, layer L1 is thin, while layer L2 is much thicker than layer L1. The dashed line 42 'indicates where the layer L1 may meet the corresponding upper layer L2, and the upper surface of the layer L1 may be anywhere between the dashed lines 42'.
In the example shown in fig. 15, the% germanium in epitaxial region 42 is a function of the depth of epitaxial region 42. The depth is shown in fig. 5B. The X-axis in fig. 15 represents the depth of the epitaxial region 42, wherein the value of the X-axis is equal to 0 and corresponds to the upper surface of the epitaxial region 42 (fig. 6B). In some embodiments of the present invention, germanium in epitaxial region 42 is represented by segments 150A and 150B (without any subsequent anneal after deposition), which shows that the germanium in layers L1 and L2 has a fixed atomic% germanium. In other embodiments of the present invention, the germanium% in epitaxial region 42 is represented by line 152 (without any subsequent anneal after deposition), which shows that the upper portion of epitaxial region 42 has a gradually increasing germanium% (higher than the corresponding lower portion).
During epitaxy, the epitaxial regions 42 grown from adjacent recesses merge with one another to form an integrated epitaxial region 42. Voids such as air gaps 43 (see fig. 6A and 6B) may be created. In some embodiments of the present invention, the formation of the epitaxial region 42 is completed while the upper surface of the epitaxial region 42 is still wavy. In other embodiments of the present invention, the formation of epitaxial region 42 is completed when the upper surface of epitaxial region 42 becomes planar.
Fig. 7 shows a perspective view of the structure after formation of contact etch stop layer 46 and interlayer dielectric layer 48. Corresponding to process 210 in process flow 200 shown in fig. 19. The contact etch stop layer 46 may be composed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed by chemical vapor deposition, atomic layer deposition, or the like. The interlayer dielectric layer 48 may comprise a dielectric material and may be formed by flowable chemical vapor deposition, spin-on coating, chemical vapor deposition, or another deposition method. The composition of the interlayer dielectric layer 48 may be an oxygen-containing dielectric material, which may be a silicon oxide-based material such as an oxide of tetraethoxysilane, a plasma-assisted chemical vapor deposited oxide (e.g., silicon oxide), a phosphosilicate glass, a borosilicate glass, a borophosphosilicate glass, or the like. A planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, may be performed to make the interlayer dielectric layer 48, the dummy gate stack 30, and the upper surface of the gate spacer 38 flush with each other.
Dummy gate stack 30 (including hard mask layer 36, dummy gate 34, and dummy gate dielectric layer 32) is then replaced with replacement gate stack 56 (including metal gate 54 and gate dielectric layer 52), as shown in fig. 8. In forming the replacement gate stack 56, the hard mask layer 36, dummy gate 34, and dummy gate dielectric layer 32 of fig. 7 are removed in one or more etching steps to form a trench or opening between the gate spacers 38. The resulting trench exposes the top surface and sidewalls of raised fin 24'.
A (replacement) gate dielectric layer 52 is then formed that extends into the trench between the gate spacers 38. In some embodiments of the present invention, each gate dielectric layer 52 includes an interfacial layer as an underside portion to contact the exposed surface of the corresponding raised fin 24'. The interfacial layer may comprise an oxide layer, such as a silicon oxide layer, which may be formed by a thermal oxidation of the raised fins 24', a chemical oxidation process, or a deposition process. The gate dielectric layer 52 may also include a high-k dielectric layer formed on the interfacial layer. The high-k dielectric layer may comprise a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The high-k dielectric material has a dielectric constant greater than 3.9 and may be greater than about 7.0. A high-k dielectric layer is formed as a conformal layer and extends over the sidewalls of raised fins 24' and the sidewalls of gate spacers 38. In some embodiments of the present invention, the method for forming the high-k dielectric layer uses atomic layer deposition or chemical vapor deposition.
As shown in fig. 8, a gate 54 is formed on the gate dielectric layer 52. The gate 54 includes a conductive sublayer. The sublayers are not particularly shown, and the sublayers may be distinguished from each other. The method of depositing the sub-layer may employ a compliant deposition method such as atomic layer deposition or chemical vapor deposition.
The stacked conductive layers may include a diffusion barrier layer and one or more work function layers on the diffusion barrier layer. The diffusion barrier layer may be comprised of titanium nitride, which may or may not be doped with silicon. The work function layer may determine the work function of the gate and may comprise at least one layer or a plurality of layers of different materials. The material selection for the work function layer depends on the requirements of the respective finfet, such as p-type finfet. For example, when the finfet is a p-type finfet, the work function layer may comprise a layer of tantalum nitride, a layer of titanium nitride on top of the nitrided layer, and a layer of titanium aluminum on top of the titanium nitride layer. After depositing the work function layer, a barrier layer (which may be another titanium nitride layer) may be formed.
The deposited gate dielectric layer and conductive layer extend conformably into the trench and may include portions overlying the interlayer dielectric layer 48. A metallization material is then deposited to fill the remainder of the trench between the gate spacers 38. For example, the composition of the metallization material may be tungsten or cobalt. In subsequent steps, a planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, is performed to remove portions of the gate dielectric layer, the conductive sub-layer, and the metallization material over the interlayer dielectric layer 48. In this way, the metal gate 54 and the gate dielectric layer 52 are formed. The gate 54 together with the gate dielectric layer 52 is seen as a replacement gate stack 56. The top surfaces of the replacement gate stack 56, gate spacers 38, contact etch stop layer 46, and interlevel dielectric layer 48 are now substantially coplanar.
As shown in some embodiments in fig. 8, a hard mask 58 is formed. The method of forming the hard mask 58 may include performing an etching step to recess the gate stack 56 so that a recess is formed between the gate spacers 38. The recess is filled with a dielectric material, and a planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, is performed to remove an excess portion of the dielectric material. The composition of the hard mask 58 may be silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.
Fig. 9A shows a step of forming the contact opening 60. Corresponding to process 212 in the process flow shown in fig. 19. The contact opening 60 is formed by etching the interlayer dielectric 48 to expose an underlying portion of the contact etch stop layer 46, followed by etching the exposed portion of the contact etch stop layer 46 to expose the epitaxial region 42. In some embodiments of the present invention shown in fig. 9A, the length of the contact opening 60 is substantially equal to the length of the planar upper surface of the epitaxial region 42. In other embodiments of the present invention, the contact openings 60 are larger than the contact openings in the figures and may extend to the position indicated by the dashed line 45 or larger. As such, the upper crystal plane (and possibly the lower crystal plane) of epitaxial region 42 may be exposed after etching the corresponding portion of contact etch stop layer 46. In addition, some remaining portions of the interlayer dielectric layer 48 may be spaced between the gate spacers 38 and the nearest contact opening 60, as shown in some embodiments of the present invention in fig. 9A. In some other embodiments, the contact opening 60 exposes sidewalls of the gate spacer 38.
Fig. 9B is a cross-sectional view of the contact opening 60, and the cross-sectional view is from a vertical plane containing the cross-sectional line 9B-9B in fig. 9A. Fig. 9C is a cross-sectional view of the contact opening 60, and the cross-sectional view is taken from a vertical plane containing the cross-sectional line 9C-9C in fig. 9A. In fig. 9C, the height of upper surface 22A and lower surface 22B of sti regions 22 is shown, and raised fins 24' are located on upper surface 22A.
As shown in fig. 10, a patterned mask (not shown) may be formed that may be used to cover some device regions, such as n-type finfet regions, and to expose some other portions, such as p-type finfet regions. A pre-amorphization implant process may be performed to form a pre-amorphized implant region 62 in the epitaxial region 42. Corresponding to process 214 in process flow 200 shown in fig. 19. In some embodiments, silicon or germanium is implanted. In some other embodiments, an inert species such as neon, argon, xenon, or radon may be implanted. The bottom of the pre-amorphized implant region 62 is higher than the top of the air gap 43 (fig. 9B). In addition, the bottom height of the preamorphized implant region 62 may be higher than 2/3 of the depth D1 (see FIG. 9) of the air gap 43. The pre-amorphized implant region 62 may be in the epitaxial upper portion 42B and not extend into the epitaxial lower portion 42A. In other embodiments, the pre-amorphized implant regions 62 may extend slightly into the epitaxial lower portion 42A. The pre-amorphization implant destroys the spacer structure of the implanted region and the pre-amorphization implant 62 is converted to an amorphous region.
A p-type impurity (dopant) implant may then be performed. The corresponding process is also shown as process 214 in the process flow 200 of fig. 19. For example, boron, gallium, and/or indium may be implanted. In other embodiments, the steps of forming a patterned mask, pre-amorphization implantation, and p-type impurity (dopant) implantation may be skipped.
Fig. 11A shows an annealing process 64. Corresponding to process 216 in process flow 200 shown in fig. 19. In some embodiments, the annealing process comprises a fusion laser annealing process. In the fusion laser annealing process, at least some portions of the epitaxial region 42, or only the surface portion, are fused. In addition to the melting laser annealing process, the annealing process may or may not include other non-melting annealing processes, such as, but not limited to, a microsecond annealing process (which may be annealed using a laser, ultraviolet light, flash lamp, or the like). Portions of the epitaxial region 42 are not melted during the non-melt annealing process. The non-melting annealing process has the effect of activating dopants in the non-melted portions of the source/drain regions in addition to the melted portions of the source/drain regions. The pre-amorphized implant region 62 may be recrystallized during the fusion laser annealing process.
FIG. 11B shows the reference section 11B/11C-11B/11C in FIG. 11A. Due to the high germanium concentration at the surface of the epitaxial region 42, the surface portions of the epitaxial region 42 are susceptible to oxidation by oxygen in the air and oxidizing agents in the chemistry of the cleaning process. As such, the upper surface 42S of the epitaxial region 42 is concave and may be continuously curved and continuously rounded.
In some embodiments of the present invention, a laser beam is projected onto the portion of the wafer 10 to be annealed to perform fusion laser annealing. Where a laser beam is employed, the size of the laser beam may be a single die or multiple dies, or may be the entire wafer, such that the generated laser pulses may anneal the entire die, multiple dies, or the entire wafer simultaneously. The size of the laser beam may be a fraction (e.g., one-quarter, one-third, one-half, or the like) of the device die. In these cases, all of the grains may be covered by a combination of multiple laser pulses to anneal the device grains. The laser pulse duration is about 10 nanoseconds to about 1 microsecond. The laser beam may also be small in size and the wafer may be scanned with the laser beam for laser annealing. In some embodiments of the invention, the laser source has a polarizing function, and thus can polarize the laser beam (with its corresponding electric field parallel or perpendicular to the plane of incidence of the laser beam). The laser source may also have a preheat function that warms the source/drain regions to be annealed from room temperature to a sub-melting temperature (e.g., about 200 c to 900 c). A pre-heat step is performed before the source/drain regions are melted. The pre-heating may also be performed by laser annealing the wafer using multiple projection sources projecting laser light at different angles of incidence to control the energy and resulting depth and area of fusion.
In some embodiments of the present invention, the power and time of the melting laser anneal are adjusted such that some upper portions (as described in detail in the following paragraphs) of epitaxial region 42 melt and some lower portions do not melt. Due to the presence of the air gap 43 (see fig. 9B), if the lower portion of the epitaxial region 42 of the source/drain exposed to the air gap 43 melts, the epitaxial region 42 may undesirably collapse into the air gap 43, and thus it is desirable that at least a portion of the epitaxial region 42 of the source/drain does not melt.
The melting point of silicon germanium is related to the atomic% germanium in epitaxial region 42, with a lower melting point for higher% germanium. For example, the melting point of silicon is 1415 ℃ and the melting point of germanium is 937 ℃. The melting point of silicon germanium may be between about 937 deg.c to about 1415 deg.c, depending on the atomic% of germanium. Since the germanium% of the lower portion of epitaxial region 42 is lower than the germanium% of the upper portion, the melting point of the lower portion is higher than the melting point of the corresponding upper portion. Thus, by adjusting the power and the laser time, the temperature of the annealing portion can be made higher than the melting point of the portion where melting is not expected and lower than the melting point of the portion where melting is expected, causing some portions to melt and some other portions not to melt, as described later.
Furthermore, the melting point of the pre-amorphized implant region 62 is lower than the melting point of the non-amorphized portion of the epitaxial region 42. The temperature of the melting laser anneal may thus be controlled to be above the melting point of the pre-amorphized implant regions 62 and below the melting point of the non-amorphized portions of the epitaxial regions 42, such that the pre-amorphized implant regions 62 melt and the epitaxial regions 42 of the source/drain do not melt. In summary, the depth of the pre-amorphized implant region 62 (e.g., depth D1 of 100% or 2/3 in FIG. 9B) is adjusted to control the melting depth to be less than depth D1.
As shown in FIG. 11B, epitaxial region 42 includes regions (portions) 42-O and 42-I. Region 42-O is the area on the fin that overlaps semiconductor strip 24. Region 42-I is the area within the fin that is located between regions 42-O on the fin. Region 42-I within the fin may overlap with air gap 43. After the fusion laser anneal, heat may be dissipated down into the wafer 10 to solidify the fused portions. Since the thermal conductivity of the air gaps 43 is lower than the thermal conductivity of the semiconductor strips 24, the rate of heat dissipation in the region 42-I in the fin is lower than the rate of heat dissipation in the region 42-O on the fin. As such, after the fusion laser anneal, region 42-O on the fin may be solidified prior to solidifying region 42-I in the fin. Solidification may progress from region 42-O on the fin to region 42-I in the fin, and from the lower portion to the upper portion of epitaxial region 42.
The solubility of germanium in molten silicon germanium is higher than in solid silicon germanium. In summary, germanium tends to concentrate into the molten silicon germanium from a solid or sub-molten (partially molten and of higher viscosity). As such, germanium migrates (concentrates) from the solidified silicon germanium surface portion into the molten portion and from region 42-O on the fin (melt post-solidification) into region 42-I in the fin (melt post-solidification). Thus after the fusion laser anneal, the germanium% of region 44 is higher than the germanium% of the adjacent region. Region 44 is primarily in region 42-I in the fin and may extend to some upper portion of region 42-O on the fin. Also in region 44, the upper portion has a higher atomic% of germanium than the corresponding lower portion.
In some embodiments of the present invention, the melting laser annealing is performed as a single shot laser annealing, wherein a single shot (pulse) of laser light is performed followed by solidification of the molten region. In other embodiments of the invention, the melting laser anneal may be performed by a multi-shot laser anneal performed 2, 3, 4, or more (e.g., up to 9) laser shots before or after fully solidifying the molten region. The interval between laser shots may be less than about 1 second, may be less than about 0.1 second, or even less than the laser pulse time, so that the molten zone remains uncured when subsequent shots are taken. The experimental results indicate that the number of shots affects the sheet resistance of the annealed area, since recrystallization is preferred when more shots are taken to eliminate defects. When the energy per shot is low (e.g., less than about 1.3J/cm)2) Each shot may lower the sheet resistance than the previous shot. When the energy per shot is high (e.g., greater than about 1.3J/cm)2) Then more shots will not be firedFurther reducing the sheet resistance and enabling single shot fusion laser annealing.
In some embodiments, the energy of the laser shots is between about 0.2J/cm2To about 1.8J/cm2In the meantime. In some embodiments, less than about 1.3J/cm is employed2Multiple shots of energy, which may be between about 0.2J/cm2To about 1.3J/cm2In the meantime. Low energy (e.g., less than about 1J/cm)2) Can be used to control the melting zone not to be too deep, and multiple shots are used to compensate for the lack of melting caused by the lower energy, and can sufficiently melt the shallow portion of the epitaxial region 42.
As shown in fig. 11B, dashed line 66 refers to the interface between the source/drain silicide regions 72 (fig. 13A) and the unsilicided portions of the epitaxial regions 42 of the underlying source/drain. In a subsequent silicidation process, the top of the source/drain epitaxial region 42 may be silicided, with dashed line 66 being the top surface of the subsequent source/drain epitaxial region 42. Points A, B, and C are shown. Point a is in dashed line 66, which is aligned to a middle line (vertical line) between two adjacent semiconductor stripes 24. Points B and C are located on both sides of point a and are vertically aligned with the centerline (vertical line) of the semiconductor strip 24. The atomic% of germanium at point a may increase by more than about 10%, more than about 20%, or more due to germanium concentration caused by the melting laser anneal. For example, the atomic% of germanium at point a before the melting laser anneal may be between about 30% and about 60%, and the atomic% of germanium at point a after the melting laser anneal may be between about 50% and about 90%. On the other hand, the atomic% of germanium in points B and C in some embodiments may be substantially the same before and after the melting laser anneal, or may be increased after the melting laser anneal. For example, the atomic% increase in germanium at points B and C can range from 0% to about 10%. In some embodiments, the atomic% germanium of points B and C before the melting laser anneal may be between about 30% and about 60%, and the atomic% germanium of points B and C after the melting laser anneal may be between about 30% and about 70%. However, the increase of points B and C is less than the increase of point a. Further, the atomic% of germanium at point a, point B, and point C prior to the fusion laser anneal may be substantially the same as each other, differing by less than about 5 atomic%. After the fusion laser anneal, the difference may be greater than about 10 atomic%, and may be any value between about 10 atomic% and about 50 atomic%.
Figures 16 and 17 show the atomic% difference of germanium in region 42-I in the fin and region 42-O on the fin. Figure 16 shows atomic% silicon and germanium as measured in the direction of arrow 47A in figure 11B, where arrow 47A is aligned with the middle line of region 42-I in the fin. The measurement sample was spin-on glass, which contained silicon oxide on the epitaxial region 42. The line segments 130 and 132 in fig. 16 are atomic% (excluding other elements such as oxygen) of silicon and germanium, respectively. Spin-on-glass region 160, epitaxial region 42, and semiconductor ribbon 24 are indicated. As shown in fig. 16, near the upper surface of epitaxial region 42 (also near point a in fig. 11B), its germanium concentration increases significantly due to concentration caused by the melting laser anneal. In the example, the germanium% of the peak reaches about 80%. The deeper the location in epitaxial region 42, the lower the atomic% germanium, and the rate of decrease depends on the depth of the molten zone.
Fig. 17 shows the measured atomic% of silicon and germanium in the direction indicated by arrow 47B of fig. 11B. Spin-on-glass region 162, epitaxial region 42, and semiconductor strips 24 are also shown. Segments 136 and 138 are atomic percent of silicon and germanium (exclusive of other elements such as oxygen), respectively. As shown in fig. 17, the increase in germanium concentration in the direction of arrow 47B (fig. 11B) is much less than the increase in germanium concentration in the direction of arrow 47A (fig. 11B). In the example, the germanium% of the peak is about 43%, which is close to the atomic% of germanium before the melting laser anneal.
In some embodiments, the molten region is relatively shallow (as shown in fig. 11B), so that a germanium concentration region 44' (in which germanium is significantly increased, e.g., more than about 10%) is shown as the dashed region. In the examples, the melting zone is shallow. In the embodiment of FIG. 11C, when the molten zone is larger than that of FIG. 11B, the germanium concentration zone 44' extends to the air gap 43. Since the melting time is very short, the molten zone may or may not collapse into the air gap 43. In addition, the portion of the molten zone directly exposed to the air gap 43 may be sub-molten to avoid collapse.
As shown in fig. 12, a metal layer 68 and a metal nitride layer 70 are deposited by a conformal deposition process. Corresponding to process 218 in process flow 200 shown in fig. 19. In some embodiments, the metal layer 68 is a titanium layer. The metal nitride layer 70 may be a titanium nitride layer, and the formation method thereof may employ atomic layer deposition, chemical vapor deposition, or the like. Metal nitride layer 70 may also be formed by nitriding the top of metal layer 68 while leaving the bottom of metal layer 68 un-nitrided.
An anneal, such as a rapid thermal anneal, is then performed to react the metal layer 68 with the top of the source/drain epitaxial regions 42 to form silicide regions 72, as shown in fig. 13A. The silicide regions 72 and the underlying source/drain epitaxial regions 42 form an arcuate upper surface 42S'. Corresponding to process 220 in process flow 200 shown in fig. 19. The portion of metal layer 68 on the sidewalls of interlayer dielectric layer 48 is unreacted. Regardless of whether the previously formed metal nitride layer 70 is retained (not removed) or removed, the new metal nitride layer (e.g., titanium nitride layer) subsequently deposited is thinner than the removed metal nitride layer. A metallization material 71, such as tungsten, cobalt, or the like, is then filled into the contact openings 60, followed by planarization to remove excess material, i.e., the source/drain contact plugs 74. In summary, the source/drain contact plugs 74 comprise the metal layer 68, the metal nitride layer 70, and the remaining portions of the metallization material 71.
Fig. 13B and 13C show a cross-sectional view and a perspective view of finfet 76, respectively. The cross-sectional view shown in FIG. 13A is from a vertical plane containing section line 13A-13A in FIG. 13C. The cross-sectional view shown in FIG. 13B is from a vertical plane containing section line 13B-13B in FIG. 13C.
In some embodiments of the present invention, as shown in fig. 14, an etch stop layer 80 is formed. The etch stop layer 80 may be composed of silicon nitride, silicon carbonitride, silicon carbide, silicon oxycarbonitride, or another dielectric material, and may be formed by a process including plasma assisted chemical vapor deposition, atomic layer deposition, chemical vapor deposition, or the like. An interlayer dielectric 82 is then formed over the etch stop layer 80. The material and formation method of the interlayer dielectric layer 82 may be the same as those used for forming the interlayer dielectric layer 48. In some embodiments, the interlayer dielectric layer 82 may be formed by plasma-assisted chemical vapor deposition, flowable chemical vapor deposition, spin-on coating, or the like.
The interlayer dielectric layer 82 and the etch stop layer 80 are etched to form an opening. For example, the etching may employ reactive ion etching. In the subsequent steps, source/drain contact plugs 86 and gate contact plugs 88 are formed. In some embodiments, the source/drain contact plugs 86 and the gate contact plugs 88 include a barrier layer and a metal-containing material on the corresponding barrier layer.
Figure 18 shows experimental results for germanium profiles in which% germanium is a function of depth in epitaxial silicon germanium regions, in some embodiments. The value 0 of the X-axis corresponds to the upper surface of the epitaxial silicon germanium regions, while the value of the X-axis increases, i.e., the depth in the silicon germanium regions increases. Segment 110 is germanium% prior to the pre-amorphization implantation and annealing process. Line segment 112 is the germanium% after the non-melt annealing process. Line segment 112 substantially overlaps line segment 110, indicating that the non-melt anneal does not cause germanium redistribution. Segment 114 is the% germanium after the lower power (and lower temperature) melting laser anneal process. Segment 116 is the% germanium after the higher power (and higher temperature) melting laser anneal process. In segments 114 and 116, it has been found that the melting laser anneal causes significant germanium redistribution.
Embodiments of the invention may have some advantages. The molten laser anneal causes germanium to concentrate at the upper surface of the source/drain regions. The schottky barrier and contact resistance is reduced due to the high atomic germanium concentration in the source/drain regions where they contact the source/drain silicide regions. Defects in the source/drain regions may be eliminated due to the liquefaction and recrystallization caused by the fusion laser annealing. In addition, air gaps, amorphizing implants, and multiple short anneals may be formed to control the depth of the melt region. In addition, the fusion laser anneal may completely repair defects caused by implanted source/drain regions, which may cause voids at the interface between the silicide region and the epitaxial region.
In some embodiments of the present invention, the method includes forming a gate stack on a first portion of the first semiconductor region; removing a second portion of the first semiconductor region on one side of the gate stack to form a recess; growing a second semiconductor region starting from the recess; implanting a second semiconductor region with impurities; and performing a melting laser anneal on the second semiconductor region, wherein the first portion of the second semiconductor region is melted at the melting laser anneal without melting the second portion and the third portion of the second semiconductor region on both sides of the first portion of the second semiconductor region. In one embodiment, the fusion laser annealing includes a plurality of laser shots. In one embodiment, the first portion overlaps the air gap, and the second portion and the third portion are connected to and overlap the semiconductor strips extending between the isolation regions. In one embodiment, the melting laser anneals do not melt the portion of the first portion exposed to the air gap. In one embodiment, the second semiconductor region is implanted to a depth less than about 2/3 a of the air gap depth. In an embodiment, the second semiconductor region includes a lower portion and an upper portion on the lower portion, and does not melt the lower portion and melts the upper portion at the time of the melting laser annealing. In an embodiment, the first germanium% of the lower portion is lower than the second germanium% of the upper portion. In one embodiment, the step of implanting the second semiconductor region uses silicon, germanium, or an inert gas. In an embodiment, the method further comprises: depositing a contact etch stop layer on the second semiconductor region; forming an interlayer dielectric layer on the contact etch stop layer; and etching the inter-layer dielectric layer and the contact etch stop layer to form a contact opening, and performing implantation and melting laser annealing through the contact opening.
In some embodiments of the invention, a method includes etching a portion of a semiconductor fin on one side of a gate stack to form a recess; epitaxially growing a silicon germanium layer, and the silicon germanium layer comprises: a first portion and a second portion respectively connected to and overlapping the first semiconductor strip and the second semiconductor strip; and a third portion connecting the first portion and the second portion; performing fusion laser annealing via a plurality of laser shots; and forming a silicide layer on the silicon germanium layer to contact the silicon germanium layer. In one embodiment, the fusion laser annealing includes three laser shots. In one embodiment, the interval between the plurality of laser shots is less than one second. In an embodiment, the melting laser anneal melts at least an upper portion of the third portion of the sige layer and does not melt the first portion and the second portion. In one embodiment, the third portion of the silicon germanium layer further includes an underside portion and the melting laser anneal does not melt the underside portion. In an embodiment, the method further comprises: amorphizing an upper portion of the gap germanium layer to form an amorphous region, wherein a lower portion of the silicon germanium layer underlies the amorphous region and melts the amorphous region of the silicon germanium layer upon melting laser annealing, while the lower portion of the silicon germanium layer remains solid.
In some embodiments of the present invention, an apparatus includes an isolation region; a first semiconductor strip and a second semiconductor strip located between the isolation regions; a first semiconductor fin and a second semiconductor fin protruding above an upper surface of the isolation region, wherein the first semiconductor fin and the second semiconductor fin overlap the first semiconductor strip and the second semiconductor strip, respectively; a gate stack on an upper surface and sidewalls of each of the first and second semiconductor fins; a source/drain region on one side of the gate stack, wherein the source/drain region comprises silicon germanium, and the source/drain region comprises: a first portion and a second portion overlapping the first semiconductor strip and the second semiconductor strip, respectively; and a third portion between the first and second portions of the source/drain region; and silicide regions on and interfacing with the source/drain regions, wherein the interface and the source/drain regions comprise: a first point located in a first intermediate line between the first semiconductor strip and the second semiconductor strip, wherein the source/drain region has a first atomic germanium at the first point; and a second point located in a second intermediate line of the first semiconductor strip, wherein the source/drain region has a second atomic% germanium at the second point, and the second atomic% germanium is lower than the first atomic% germanium. In one embodiment, the first germanium atomic% is about 10% higher than the second germanium atomic%. In one embodiment, in the third portion of the source/drain region, the atomic% germanium reaches a peak near the interface. In one embodiment, the first germanium atom% is between about 50% and about 90%, and the second germanium atom% is between about 30% and about 70%. In one embodiment, the atomic% of germanium in the source/drain regions decreases continuously from the first point down.
The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.

Claims (1)

1. A method of forming a semiconductor device, comprising:
forming a gate stack on a first portion of a first semiconductor region;
removing a second portion of the first semiconductor region on one side of the gate stack to form a recess;
growing a second semiconductor region from the recess;
implanting the second semiconductor region with an impurity; and
performing a melting laser annealing on the second semiconductor region, wherein a first portion of the second semiconductor region is melted without melting a second portion and a third portion of the second semiconductor region on both sides of the first portion of the second semiconductor region at the time of the melting laser annealing.
CN202010397989.XA 2019-08-23 2020-05-12 Method for forming semiconductor device Pending CN112420514A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/549,213 US10978344B2 (en) 2019-08-23 2019-08-23 Melting laser anneal of epitaxy regions
US16/549,213 2019-08-23

Publications (1)

Publication Number Publication Date
CN112420514A true CN112420514A (en) 2021-02-26

Family

ID=74647054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010397989.XA Pending CN112420514A (en) 2019-08-23 2020-05-12 Method for forming semiconductor device

Country Status (3)

Country Link
US (2) US10978344B2 (en)
CN (1) CN112420514A (en)
TW (1) TW202109677A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210391464A1 (en) * 2020-06-10 2021-12-16 Samsung Electronics Co., Ltd. Integrated circuit device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240120388A1 (en) * 2022-10-06 2024-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Tunable structure profile

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573531B1 (en) * 1999-09-03 2003-06-03 The Trustees Of Columbia University In The City Of New York Systems and methods using sequential lateral solidification for producing single or polycrystalline silicon thin films at low temperatures
US20040087116A1 (en) * 2002-10-30 2004-05-06 Junichiro Nakayama Semiconductor devices and methods of manufacture thereof
EP1922745A1 (en) * 2005-08-16 2008-05-21 The Trustees of Columbia University in the City of New York Systems and methods for uniform sequential lateral solidification of thin films using high frequency lasers
CN104882371B (en) * 2008-01-07 2018-01-26 株式会社 Ihi Laser anneal method and device
US9196704B2 (en) * 2011-12-19 2015-11-24 Intel Corporation Selective laser annealing process for buried regions in a MOS device
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US9159811B2 (en) * 2013-12-18 2015-10-13 International Business Machines Corporation Growing buffer layers in bulk finFET structures
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
KR102167519B1 (en) * 2014-03-21 2020-10-19 인텔 코포레이션 Techniques for integration of ge-rich p-mos source/drain contacts
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9318608B1 (en) * 2014-09-29 2016-04-19 Globalfoundries Inc. Uniform junction formation in FinFETs
US10083843B2 (en) * 2014-12-17 2018-09-25 Ultratech, Inc. Laser annealing systems and methods with ultra-short dwell times
US9564489B2 (en) 2015-06-29 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple gate field-effect transistors having oxygen-scavenged gate stack
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10304957B2 (en) * 2016-09-13 2019-05-28 Qualcomm Incorporated FinFET with reduced series total resistance
KR102551745B1 (en) * 2016-11-09 2023-07-06 삼성전자주식회사 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210391464A1 (en) * 2020-06-10 2021-12-16 Samsung Electronics Co., Ltd. Integrated circuit device
US11575044B2 (en) * 2020-06-10 2023-02-07 Samsung Electronics Co., Ltd. Integrated circuit device

Also Published As

Publication number Publication date
TW202109677A (en) 2021-03-01
US20210257255A1 (en) 2021-08-19
US10978344B2 (en) 2021-04-13
US11532516B2 (en) 2022-12-20
US20210057276A1 (en) 2021-02-25

Similar Documents

Publication Publication Date Title
CN110783274B (en) Integrated circuit device and method of manufacturing the same
US11211455B2 (en) Formation of dislocations in source and drain regions of FinFET devices
CN110648918B (en) Semiconductor structure and manufacturing method thereof
US9583393B2 (en) Epitaxial growth of doped film for source and drain regions
US10510851B2 (en) Low resistance contact method and structure
US11264487B2 (en) Reduction of fin loss in the formation of FinFETs
US20180145131A1 (en) Semiconductor Device and Method
KR20140112363A (en) Mechanisms for doping lightly-doped-drain(ldd) regions of finfet devices
US11973127B2 (en) Semiconductor structure with source/drain structure having modified shape
US11830947B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
TWI764292B (en) Semiconductor device and manufacturing method thereof
US11532516B2 (en) Melting laser anneal of epitaxy regions
TW202139269A (en) Method of forming semiconductor device
US20230008413A1 (en) Semiconductor device and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20210226