CN112420101A - Storage module control method and device - Google Patents
Storage module control method and device Download PDFInfo
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- CN112420101A CN112420101A CN202011307005.0A CN202011307005A CN112420101A CN 112420101 A CN112420101 A CN 112420101A CN 202011307005 A CN202011307005 A CN 202011307005A CN 112420101 A CN112420101 A CN 112420101A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
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Abstract
The invention provides a storage module control method, which comprises the following steps: determining the enabling signal state of the clock according to the read-write request state; determining the working state of the clock according to the enabling signal state of the clock; sending a read-write signal to a storage module according to the working state of the clock; and sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal. The invention can reduce the power consumption of the memory module on the basis of the existing memory structure.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a method and an apparatus for controlling a memory module.
Background
In the field of chip design and manufacture, the number of transistors in a unit area is increased sharply, the dominant frequency is higher and higher, and the demand for power consumption is also increased, so that reducing the power consumption is an indispensable part in chip design. Different chip designs and manufacturers provide different technical schemes for reducing chip power consumption, such as different modes of low power consumption states, memory cell manufacturing process improvement, operating frequency adjustment and the like. There are also schemes proposed in the design to reduce power consumption by reducing the frequency of Static Random Access Memory (SRAM).
In the foregoing SRAM power reduction design, the mainstream idea is to change the SRAM storage structure. The main technical directions are two, one is to reduce the correlation degree between the storage units in the read-write process, reduce the unit influence degree in the row-column operation and realize the purpose of reducing the power consumption; the other is to reduce the leakage current and the pre-charging time to achieve the purpose of reducing the power consumption by changing the design of a storage structure.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
in the existing SRAM power consumption reduction design, the SRAM storage structure needs to be changed, so that the difficulty and complexity of the design can be increased.
Disclosure of Invention
The method, the device, the apparatus and the user equipment for controlling the memory module provided by the invention can reduce the power consumption of the memory module on the basis of the existing memory structure.
In a first aspect, the present invention provides a method for controlling a memory module, including:
determining the enabling signal state of the clock according to the read-write request state;
determining the working state of the clock according to the enabling signal state of the clock;
sending a read-write signal to a storage module according to the working state of the clock;
and sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
Optionally, determining the enable signal state of the clock according to the read-write request state includes:
receiving a read-write request signal and determining the state of the read-write request signal;
and determining the enabling signal state of the clock according to the state of the read-write request signal.
Optionally, determining the enable signal state of the clock according to the state of the read/write request signal includes:
when the read-write request signal is in a state needing to be read and written, determining that the enabling signal state of the clock is an enabling state;
and when the read-write request signal is in a state which does not need to be read and written, determining that the enable signal state of the clock is in a non-enable state.
Optionally, when the read-write request signal is in a state that read-write is not required, determining an enable signal state of a clock includes:
when the read-write request signal is in a state of not needing reading and writing, determining read-write delay time;
and when the read-write delay time is over, determining the enable signal state of the clock as a non-enable state.
Optionally, determining the enable signal state of the clock according to the read-write request state includes:
determining whether the cache data meets the read-write requirements or not according to the read-write request state;
and when the cache data does not meet the read-write requirements, determining the enabling signal state of the clock as an enabling state.
Optionally, determining the working state of the clock according to the state of the enable signal of the clock includes:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
Optionally, sending the read-write signal to the storage module according to the working state of the clock includes:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
In a second aspect, the present invention provides a memory module control apparatus, including:
the read-write request receiving module is used for determining the enabling signal state of the clock according to the read-write request state;
the clock output control module is used for determining the working state of the clock according to the enabling signal state of the clock;
the read-write control module is used for sending a read-write signal to the storage module according to the working state of the clock;
and the data interaction module is used for sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
Optionally, the read-write request receiving module includes:
the read-write request receiving submodule is used for receiving a read-write request signal and determining the state of the read-write request signal;
and the enabling signal generating submodule determines the enabling signal state of the clock according to the state of the read-write request signal.
Optionally, the enable signal generating unit includes:
an enable state unit, configured to determine that an enable signal state of the clock is an enable state when the read/write request signal is in a state requiring reading and writing;
and the non-enabling state unit is used for determining the enabling signal state of the clock as the non-enabling state when the read-write request signal is in the state of not needing reading and writing.
Optionally, the disable state unit comprises:
a delay counting subunit, for determining the read-write delay time when the read-write request signal is in a state of not needing to be read-written;
and the non-enabling determining subunit determines that the enabling signal state of the clock is a non-enabling state when the read-write delay time is over.
Optionally, the method further comprises:
the cache module is used for storing data with the reading frequency higher than a preset threshold value;
the read-write request receiving module further comprises:
the cache query submodule is used for determining whether the cache data meet the read-write requirement according to the read-write request state;
and the enabling signal determining submodule is used for determining the enabling signal state of the clock as the enabling state when the cache data does not meet the read-write requirement.
Optionally, the clock output control module is configured to:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
Optionally, the clock output module is further configured to:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
The invention controls the on-off of the clock according to the read-write request, can dynamically adjust the on-off state of the clock in real time, can effectively reduce the power consumption of the storage module, and has better and obvious effect of reducing the power consumption when each storage module respectively adopts the technical scheme provided by the invention to control the on-off of the clock in a state that a plurality of storage modules are integrated. In the technical scheme of the invention, a proper fit point is found between the reduction of power consumption and the performance balance under the normal working state of the storage module, and the technical realization difficulty is lower and the effect is more obvious.
Drawings
FIG. 1 is a flow chart of a memory module control method according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating an enable signal status determination method according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating the detailed operation of a memory module control method according to another embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a memory module control apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a memory module control apparatus according to another embodiment of the present invention;
fig. 6 is a schematic structural diagram of a memory module control device according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for controlling a memory module, as shown in fig. 1, including:
in some embodiments, the read-write request state represents whether a read-write request is currently available, and mainly includes two states of read-write operation and no read-write operation, the enable signal is a signal for driving the clock switch, and mainly includes an enable state and a non-enable state, and the read-write request state corresponds to the enable signal state. For example, when the read/write request state is a state requiring reading and writing, the state of the enable signal is determined to be an enable state, and when the read/write request state is a state not requiring reading and writing, the state of the enable signal is determined to be a non-enable state.
in some embodiments, the working state of the clock refers to whether the current clock is on, i.e. whether a clock signal is sent out; in general, the clock operation state includes two states, one is an on state, i.e., a state in which a clock signal is asserted, and the other is an off state, i.e., a state in which no clock signal is asserted. The enable signal is a signal that drives the clock on and off. For example, when the enable signal is in the enable state, the driving clock is turned on and the clock signal is sent out, and when the enable signal is in the disable state, the driving clock is turned off and the clock signal is not sent out.
in some embodiments, the read and write operations of the memory module require a rising or falling edge of the clock signal to be driven, such that in the clock-on state, the clock signal is asserted, and the module receiving the clock signal is asserted to have a rising or falling edge, and in the clock-off state, the clock signal is not asserted, and the module receiving the clock signal is asserted to have no rising or falling edge. And after the clock is started, triggering the sending of the read-write signal according to the rising edge and the falling edge of the clock signal, and outputting the read-write signal to the storage module.
And step 400, sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
In some embodiments, the read signal generally includes a data address to be read, and data of the corresponding address is sent to the corresponding call interface according to the data address in the read signal. In the write signal, data to be written and an address to be written are generally included, and the data to be written is written into the corresponding address according to the address to be written in the write signal.
The embodiment controls the on-off of the clock according to the read-write request, can dynamically adjust the on-off state of the clock in real time, and can effectively reduce the power consumption of the memory modules. In the technical scheme of the embodiment, a proper fit point is found between power consumption reduction and performance balance under the normal working state of the storage module, and the technical implementation difficulty is low and the effect is obvious.
On the basis of the embodiment shown in fig. 1, as shown in fig. 2, step 100 may comprise:
in some embodiments, receiving the read/write request signal means maintaining a state capable of receiving the read/write request signal. However, it should be understood that the read and write request signals are not continuously transmitted. When there is no read/write request signal, the state of the read/write request signal is judged as not needing to be read/written, and when there is a read/write request signal, the state of the read/write request signal is judged as needing to be read/written.
And step 120, determining the enabling signal state of the clock according to the state of the read-write request signal.
In some embodiments, it is determined whether reading or writing is currently required according to the manner in step 110, when reading or writing is required, a rising edge and a falling edge of a clock signal are required to trigger in the reading or writing process, so that the current state of the clock enable signal is changed to an enable state, and when reading or writing is not required, no clock signal is required to trigger any operation, so that if the transmission of the clock signal is still maintained at this time, invalid power consumption is generated, so that the state of the enable signal is changed to a non-enable state, and the enable signal in the non-enable state drives a clock to be turned off, and the transmission of the clock signal is stopped, so as to reduce the power consumption.
On the basis of the embodiment shown in fig. 2, step 110 comprises:
when the read-write request signal is in a state needing to be read and written, determining that the enabling signal state of the clock is an enabling state;
and when the read-write request signal is in a state which does not need to be read and written, determining that the enable signal state of the clock is in a non-enable state.
In some embodiments, the enable signal state may be represented in the form of a high level and a low level, respectively, for example, the non-enabled state of the enable signal is represented in the low level, and the enabled state of the enable signal is represented in the high level. By switching high and low levels, an enable signal for driving the clock to be turned on and off can be generated.
On the basis of the previous embodiment, when the read-write request signal is in a state that does not require reading and writing, determining the enable signal state of the clock includes:
when the read-write request signal is in a state of not needing reading and writing, determining read-write delay time;
and when the read-write delay time is over, determining the enable signal state of the clock as a non-enable state.
In some embodiments, the enable signal of the clock cannot be switched to the disable state immediately after the read/write request is sent because the read/write logic is not yet completed. Therefore, when the read-write request state is switched to the read-write unnecessary state, the delayed counting is started, and after the delayed counting is finished, the enable signal of the clock is switched to the non-enable state. And resetting the counting if the read-write request state is the state needing reading and writing before the counting is finished. The specific execution flow in this embodiment is shown in fig. 3.
On the basis of the foregoing embodiment, determining the enable signal state of the clock according to the read-write request state includes:
determining whether the cache data meets the read-write requirements or not according to the read-write request state;
and when the cache data does not meet the read-write requirements, determining the enabling signal state of the clock as an enabling state.
In some embodiments, since data accessed by a part of functions during execution is usually concentrated, in order to save power consumption, frequently accessed data may be stored in a cache, when a read-write request state is a state requiring reading and writing, it is first determined whether the data in the cache can meet a read-write requirement, and if the data in the cache meets the read-write requirement, no access is required to the storage module, so that an enable signal state is still maintained in a non-enable state. When the data on the cache does not meet the read-write requirement, the memory module needs to be accessed at the moment, so that the state of the enabling signal is changed into the enabling state, and the data in the memory module can be conveniently read.
As an optional implementation manner, determining the working state of the clock according to the state of the enable signal of the clock includes:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
In some embodiments, the enable signal is used as a signal for driving the clock operation state, and as can be seen from the foregoing embodiments, the enable signal is determined according to the read/write state, so that the read/write state indirectly controls the operation state of the clock by controlling the state of the enable signal, and the enable signal enables the clock state to be controlled by the read/write state.
As an optional implementation manner, sending the read-write signal to the storage module according to the working state of the clock includes:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
In some embodiments, the working state of the clock controls the working state of the storage module, and as described in the previous embodiment, the read-write state indirectly controls the working state of the storage module sequentially through the enable signal and the clock signal, so that the working state of the storage module can change along with the read-write state, when there is a read-write demand, the storage module works to ensure that the read-write demand is met, and when there is no read-write demand, the storage module is turned off, thereby saving power consumption.
An embodiment of the present invention further provides a memory module control device, as shown in fig. 4-5, where fig. 4 is a schematic diagram of the device of this embodiment applied to an SRAM memory module, and fig. 5 is a schematic diagram of the device of this embodiment applied to a register bank memory module, and the memory module control device includes:
the read-write request receiving module is used for determining the enabling signal state of the clock according to the read-write request state;
in some embodiments, the read-write request state represents whether a read-write request is currently available, and mainly includes two states of read-write operation and no read-write operation, the enable signal is a signal for driving the clock switch, and mainly includes an enable state and a non-enable state, and the read-write request state corresponds to the enable signal state. For example, when the read/write request state is a state requiring reading and writing, the state of the enable signal is determined to be an enable state, and when the read/write request state is a state not requiring reading and writing, the state of the enable signal is determined to be a non-enable state.
The clock output control module is used for determining the working state of the clock according to the enabling signal state of the clock;
in some embodiments, the working state of the clock refers to whether the current clock is on, i.e. whether a clock signal is sent out; in general, the clock operation state includes two states, one is an on state, i.e., a state in which a clock signal is asserted, and the other is an off state, i.e., a state in which no clock signal is asserted. The enable signal is a signal that drives the clock on and off. For example, when the enable signal is in the enable state, the driving clock is turned on and the clock signal is sent out, and when the enable signal is in the disable state, the driving clock is turned off and the clock signal is not sent out.
The read-write control module is used for sending a read-write signal to the storage module according to the working state of the clock;
in some embodiments, the read and write operations of the memory module require a rising or falling edge of the clock signal to be driven, such that in the clock-on state, the clock signal is asserted, and the module receiving the clock signal is asserted to have a rising or falling edge, and in the clock-off state, the clock signal is not asserted, and the module receiving the clock signal is asserted to have no rising or falling edge. And after the clock is started, triggering the sending of the read-write signal according to the rising edge and the falling edge of the clock signal, and outputting the read-write signal to the storage module. In addition, the module is also responsible for maintaining the current read and write request state until the clock is turned on.
And the data interaction module is used for sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
In some embodiments, the read signal generally includes a data address to be read, and data of the corresponding address is sent to the corresponding call interface according to the data address in the read signal. In the write signal, data to be written and an address to be written are generally included, and the data to be written is written into the corresponding address according to the address to be written in the write signal.
The embodiment controls the on-off of the clock according to the read-write request, can dynamically adjust the on-off state of the clock in real time, and can effectively reduce the power consumption of the memory modules. In the technical scheme of the embodiment, a proper fit point is found between power consumption reduction and performance balance under the normal working state of the storage module, and the technical implementation difficulty is low and the effect is obvious.
As an optional embodiment, the read-write request receiving module includes:
the read-write request receiving submodule is used for receiving a read-write request signal and determining the state of the read-write request signal;
in some embodiments, receiving the read/write request signal means maintaining a state capable of receiving the read/write request signal. However, it should be understood that the read and write request signals are not continuously transmitted. When there is no read/write request signal, the state of the read/write request signal is judged as not needing to be read/written, and when there is a read/write request signal, the state of the read/write request signal is judged as needing to be read/written.
And the enabling signal generating submodule determines the enabling signal state of the clock according to the state of the read-write request signal.
In some embodiments, the read-write request receiving submodule determines whether reading or writing is currently required, when reading or writing is required, a rising edge and a falling edge of a clock signal are required to be used for triggering in the reading or writing process, so that the current state of a clock enable signal is changed into an enable state, when reading or writing is not required, no clock signal is required to trigger any operation, and therefore, if the clock signal is still transmitted at the moment, invalid power consumption is generated, so that the state of the enable signal is changed into a non-enable state, the enable signal in the non-enable state drives a clock to be turned off, and transmission of the clock signal is stopped, so that power consumption is reduced.
As an alternative embodiment, the enable signal generating unit includes:
an enable state unit, configured to determine that an enable signal state of the clock is an enable state when the read/write request signal is in a state requiring reading and writing;
and the non-enabling state unit is used for determining the enabling signal state of the clock as the non-enabling state when the read-write request signal is in the state of not needing reading and writing.
In some embodiments, the enable signal state may be represented in the form of a high level and a low level, respectively, for example, the non-enabled state of the enable signal is represented in the low level, and the enabled state of the enable signal is represented in the high level. By switching high and low levels, an enable signal for driving the clock to be turned on and off can be generated.
As an alternative embodiment, the disable state unit includes:
a delay counting subunit, for determining the read-write delay time when the read-write request signal is in a state of not needing to be read-written;
and the non-enabling determining subunit determines that the enabling signal state of the clock is a non-enabling state when the read-write delay time is over.
In some embodiments, the enable signal of the clock cannot be switched to the disable state immediately after the read/write request is sent because the read/write logic is not yet completed. Therefore, when the read-write request state is switched to the read-write unnecessary state, the delayed counting is started, and after the delayed counting is finished, the enable signal of the clock is switched to the non-enable state. And resetting the counting if the read-write request state is the state needing reading and writing before the counting is finished.
As an alternative embodiment, as shown in fig. 6, the method further includes:
the cache module is used for storing data with the reading frequency higher than a preset threshold value;
the read-write request receiving module further comprises:
the cache query submodule is used for determining whether the cache data meet the read-write requirement according to the read-write request state;
and the enabling signal determining submodule is used for determining the enabling signal state of the clock as the enabling state when the cache data does not meet the read-write requirement.
In some embodiments, since data accessed by a part of functions during execution is usually concentrated, in order to save power consumption, frequently accessed data may be stored in a cache, when a read-write request state is a state requiring reading and writing, it is first determined whether the data in the cache can meet a read-write requirement, and if the data in the cache meets the read-write requirement, no access is required to the storage module, so that an enable signal state is still maintained in a non-enable state. When the data on the cache does not meet the read-write requirement, the memory module needs to be accessed at the moment, so that the state of the enabling signal is changed into the enabling state, and the data in the memory module can be conveniently read.
As an optional implementation manner, the clock output control module is configured to:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
In some embodiments, the enable signal is used as a signal for driving the clock operation state, and as can be seen from the foregoing embodiments, the enable signal is determined according to the read/write state, so that the read/write state indirectly controls the operation state of the clock by controlling the state of the enable signal, and the enable signal enables the clock state to be controlled by the read/write state.
As an optional implementation manner, optionally, the clock output module is further configured to:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
In some embodiments, the working state of the clock controls the working state of the storage module, and as described in the previous embodiment, the read-write state indirectly controls the working state of the storage module sequentially through the enable signal and the clock signal, so that the working state of the storage module can change along with the read-write state, when there is a read-write demand, the storage module works to ensure that the read-write demand is met, and when there is no read-write demand, the storage module is turned off, thereby saving power consumption.
The apparatus in the above embodiments can be applied to a register bank module, as shown in fig. 5, and can also be applied to an SRAM memory module, as shown in fig. 4.
It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (14)
1. A memory module control method, comprising:
determining the enabling signal state of the clock according to the read-write request state;
determining the working state of the clock according to the enabling signal state of the clock;
sending a read-write signal to a storage module according to the working state of the clock;
and sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
2. The memory module control method of claim 1, wherein determining the enable signal state of the clock based on the read/write request state comprises:
receiving a read-write request signal and determining the state of the read-write request signal;
and determining the enabling signal state of the clock according to the state of the read-write request signal.
3. The memory module control method of claim 2, wherein determining the enable signal state of the clock according to the state of the read/write request signal comprises:
when the read-write request signal is in a state needing to be read and written, determining that the enabling signal state of the clock is an enabling state;
and when the read-write request signal is in a state which does not need to be read and written, determining that the enable signal state of the clock is in a non-enable state.
4. The method of claim 3, wherein determining the state of the clock enable signal when the read/write request signal is in a state not requiring reading or writing comprises:
when the read-write request signal is in a state of not needing reading and writing, determining read-write delay time;
and when the read-write delay time is over, determining the enable signal state of the clock as a non-enable state.
5. The memory module control method of claim 1, wherein determining the enable signal state of the clock based on the read/write request state comprises:
determining whether the cache data meets the read-write requirements or not according to the read-write request state;
and when the cache data does not meet the read-write requirements, determining the enabling signal state of the clock as an enabling state.
6. The memory module control method of claim 1, wherein determining the operational state of the clock based on the state of the enable signal of the clock comprises:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
7. The memory module control method of claim 6, wherein sending the read and write signals to the memory module according to the operating state of the clock comprises:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
8. A memory module control apparatus, comprising:
the read-write request receiving module is used for determining the enabling signal state of the clock according to the read-write request state;
the clock output control module is used for determining the working state of the clock according to the enabling signal state of the clock;
the read-write control module is used for sending a read-write signal to the storage module according to the working state of the clock;
and the data interaction module is used for sending the data corresponding to the read-write signal in the storage module to a calling interface according to the read-write signal.
9. The memory module control device according to claim 8, wherein the read/write request receiving module includes:
the read-write request receiving submodule is used for receiving a read-write request signal and determining the state of the read-write request signal;
and the enabling signal generating submodule determines the enabling signal state of the clock according to the state of the read-write request signal.
10. The memory module control device according to claim 9, wherein the enable signal generating unit includes:
an enable state unit, configured to determine that an enable signal state of the clock is an enable state when the read/write request signal is in a state requiring reading and writing;
and the non-enabling state unit is used for determining the enabling signal state of the clock as the non-enabling state when the read-write request signal is in the state of not needing reading and writing.
11. The memory module control device of claim 10, wherein the disable state unit comprises:
a delay counting subunit, for determining the read-write delay time when the read-write request signal is in a state of not needing to be read-written;
and the non-enabling determining subunit determines that the enabling signal state of the clock is a non-enabling state when the read-write delay time is over.
12. The memory module control device of claim 8, further comprising:
the cache module is used for storing data with the reading frequency higher than a preset threshold value;
the read-write request receiving module further comprises:
the cache query submodule is used for determining whether the cache data meet the read-write requirement according to the read-write request state;
and the enabling signal determining submodule is used for determining the enabling signal state of the clock as the enabling state when the cache data does not meet the read-write requirement.
13. The memory module control device of claim 8, wherein the clock output control module is configured to:
when the enable signal state of the clock is an enable state, determining that the working state of the clock is an open state;
and when the enable signal state of the clock is a non-enable state, determining that the working state of the clock is a closed state.
14. The memory module control method of claim 13, wherein the clock output module is further configured to:
when the working state of the clock is an open state, triggering the read-write signal to be sent to a storage module according to the rising edge or the falling edge of the clock signal and performing read-write operation on the storage module according to the read-write signal;
and when the working state of the clock is a closing state, closing the read-write function of the storage module so as to reduce the power consumption of the read-write module.
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|---|---|---|---|
| CN202011307005.0A CN112420101A (en) | 2020-11-19 | 2020-11-19 | Storage module control method and device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011307005.0A CN112420101A (en) | 2020-11-19 | 2020-11-19 | Storage module control method and device |
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