CN112417796A - Voltage drop analysis method and device compatible with IP circuit performance simulation and electronic equipment - Google Patents
Voltage drop analysis method and device compatible with IP circuit performance simulation and electronic equipment Download PDFInfo
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- CN112417796A CN112417796A CN202011306502.9A CN202011306502A CN112417796A CN 112417796 A CN112417796 A CN 112417796A CN 202011306502 A CN202011306502 A CN 202011306502A CN 112417796 A CN112417796 A CN 112417796A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The embodiment of the invention discloses a voltage drop analysis method and device compatible with IP circuit performance simulation and electronic equipment, relates to the technical field of integrated circuits, and is used for guiding circuit design optimization and reducing the influence of voltage drop on circuit performance. In the voltage drop analysis method compatible with the IP circuit performance simulation, the IP circuit performance simulation comprises the steps of setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file and performing circuit simulation, and the voltage drop analysis method comprises the following steps: searching an MOS tube with a source end or a drain end connected with a power line or a ground line from the circuit netlist; modifying the measurement file to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube; and after the circuit simulation is finished, obtaining a voltage drop result file. The invention is suitable for occasions needing voltage drop analysis.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a voltage drop analysis method and device compatible with IP circuit performance simulation, electronic equipment and a storage medium.
Background
The power lines in the chip are metal wires, which are resistive and cause a voltage drop when current flows through the resistor, so-called IR drop. If the IR drop is too large, it means that the power supply network of the chip is not strong enough, and the power supply voltage really applied to the MOS transistor will be much smaller than the ideal voltage value, which will bring a great influence on the performance of the chip, so the IR drop analysis is performed on the chip at present, and the power supply network design of the chip is optimized.
As is well known, during a Design process of a circuit, various performance simulations are performed, such as timing analysis (performance), power consumption analysis (power), area estimation (area, which is collectively referred to as PPA analysis), Signal Integrity (SI) verification, symmetric Design of an analog circuit, clock jitter (clock jitter) verification, and the like, and a general EDA (electronic Design Automation) tool separates IR drop analysis from performance simulation of the circuit, which cannot directly obtain how much influence the IR drop has on various performances of the circuit.
Specifically, a totem tool is commonly used in the industry to analyze an IR drop of an IP circuit (a circuit with certain specific functions used on a chip), although the totem is used for IR drop analysis, which is relatively accurate and can be used as a check standard of the IR drop, because the totem tool and a commonly used circuit simulation tool are not provided by the same EDA company, the IR drop analysis and the circuit simulation are separately performed in the design process of the circuit, the burden of a design flow is increased, and how much influence of the IR drop on various performances of the circuit cannot be directly obtained. In addition, the use of totem is complicated in tool setting, generally, the totem is used for performing IR drop analysis once after the layout (layout) of the circuit is completed, and at this time, if the IR drop result does not meet the requirement, the return is made to modify the layout, so that a long time is required.
Disclosure of Invention
In view of this, embodiments of the present invention provide a voltage drop analysis method, device, electronic device and storage medium compatible with IP circuit performance simulation, which can combine the performance simulation of a circuit with IR drop analysis, so as to guide circuit design optimization and reduce the influence of IR drop on circuit performance.
In a first aspect, an embodiment of the present invention provides a voltage drop analysis method compatible with IP circuit performance simulation, where the IP circuit performance simulation includes setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file, and circuit simulation, and the voltage drop analysis method includes:
searching an MOS tube with a source end or a drain end connected with a power line or a ground line from the circuit netlist;
modifying the measurement file to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube;
and after the circuit simulation is finished, obtaining a voltage drop result file.
With reference to the first aspect, in an implementation manner of the first aspect, the modifying the measurement file to increase the measurement of the found source or drain voltage of the MOS transistor includes:
if the found source end or drain end of the MOS tube is connected with the ground wire, increasing the measurement of the maximum voltage of the source end or drain end in the simulation time;
and if the source end or the drain end of the searched MOS tube is connected with a power line, increasing the measurement of the minimum voltage of the source end or the drain end in the simulation time.
With reference to the first aspect, in another implementation manner of the first aspect, the obtaining a voltage drop result file after the circuit simulation is completed includes:
and if MOS tubes with voltage drop which does not meet the requirement exist, positioning the MOS tubes on the layout, and modifying the layout.
With reference to the first aspect, in a further implementation manner of the first aspect, the positioning the MOS transistors on the layout includes:
and verifying the layout and the logic diagram by using the circuit netlist and the layout file to obtain the coordinates of the MOS tube on the layout.
With reference to the first aspect, in a further embodiment of the first aspect, the IP circuit performance simulation is a timing analysis, a power consumption analysis, or a signal integrity analysis.
In a second aspect, an embodiment of the present invention provides a voltage drop analysis apparatus compatible with IP circuit performance simulation, where the IP circuit performance simulation includes setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file, and circuit simulation, and the voltage drop analysis apparatus includes:
the searching module is used for searching an MOS (metal oxide semiconductor) tube with a source end or a drain end connected with a power supply line or a ground line from the circuit netlist;
the modification module is used for modifying the measurement file so as to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube;
and the acquisition module is used for acquiring a voltage drop result file after the circuit simulation is finished.
With reference to the second aspect, in an implementation manner of the second aspect, the modifying module is further configured to increase measurement of a maximum voltage of the source terminal or the drain terminal within the simulation time if the found source terminal or the drain terminal of the MOS transistor is connected to the ground line; and if the source end or the drain end of the searched MOS tube is connected with a power line, increasing the measurement of the minimum voltage of the source end or the drain end in the simulation time.
With reference to the second aspect, in another implementation manner of the second aspect, the obtaining module is further configured to, if there are MOS transistors whose voltage drop does not meet the requirement, position the MOS transistors on the layout, and modify the layout.
With reference to the second aspect, in a further implementation manner of the second aspect, the obtaining module is further configured to perform layout and logic diagram verification by using a circuit netlist and a layout file, so as to obtain coordinates of the MOS transistor on the layout.
In yet another embodiment of the second aspect in combination with the second aspect, the IP circuit performance simulation is a timing analysis, a power consumption analysis, or a signal integrity analysis.
In a third aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, for performing any of the methods described above.
In a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement any of the methods described above.
The voltage drop analysis method, the voltage drop analysis device, the electronic equipment and the storage medium compatible with the IP circuit performance simulation provided by the embodiment of the invention can combine the performance simulation and the voltage drop analysis of the circuit without being separated, so that the voltage drop result can be obtained while the circuit performance simulation is carried out, and the influence of the voltage drop on the circuit performance can be obtained, thereby guiding the circuit design optimization, reducing the influence of the voltage drop on the circuit performance and simplifying the design flow of the circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a voltage drop analysis method compatible with IP circuit performance simulation according to the present invention;
FIG. 2 is a schematic diagram of an IP circuit according to the embodiment of the method shown in FIG. 1;
FIG. 3 is a schematic structural diagram of an embodiment of a voltage drop analysis apparatus compatible with IP circuit performance simulation according to the present invention;
fig. 4 is a schematic structural diagram of an embodiment of an electronic device of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
On one hand, the embodiment of the invention provides a voltage drop analysis method compatible with an IP circuit performance simulation, which is used for analyzing an IP circuit, the IP circuit performance simulation mainly includes the steps of setting simulation excitation, extracting a circuit netlist with parasitic parameters (XRC) from a layout, writing a measurement file, circuit simulation and the like, the circuit performance simulation can be the aforementioned time sequence analysis, power consumption analysis, signal integrity analysis and the like, and the steps included in the circuit performance simulation are all known in the art and are not described in detail herein.
As shown in fig. 1, the voltage drop analysis method of the present embodiment includes:
step 101: searching an MOS tube with a source end or a drain end connected with a power line or a ground line from the circuit netlist;
in the step, an object to be subjected to voltage drop analysis is determined, specifically, a source terminal or a drain terminal of an MOS transistor connected with a power line (VDD) and a ground line (VSS) is found from a circuit netlist, and names of the MOS transistors in a circuit are captured to be used as an object to be subjected to voltage drop analysis.
Here, it is understood that the power supply line is not limited to VDD, and may be VDDA, VDDC, or the like; the ground line is not limited to VSS, and VSSA, VSSC, or the like may be used.
Step 102: modifying the measurement file to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube;
the special point of the method is that the measurement file needs to measure the content related to the voltage drop besides the content required to be measured in the conventional circuit performance simulation, so that the measurement file needs to be modified to increase the measurement of the found source end or drain end voltage of the MOS tube.
As an optional embodiment, the modifying the measurement file to increase the measurement of the source terminal or drain terminal voltage of the found MOS transistor (step 102) may include:
if the source end or the drain end of the searched MOS tube is connected with a ground wire (VSS), increasing the measurement of the maximum voltage of the source end or the drain end in the simulation time, namely the ground voltage actually applied to the MOS tube after the VSS is subjected to voltage drop;
if the source end or the drain end of the searched MOS tube is connected with a power line (VDD), the measurement of the minimum voltage of the source end or the drain end in the simulation time is increased, namely the power voltage actually applied to the MOS tube after the VDD is subjected to voltage drop.
Therefore, the voltage drop when the power supply voltage or the ground voltage is transmitted to the MOS tube can be accurately known.
Step 103: and after the circuit simulation is finished, obtaining a voltage drop result file.
In this step, after the circuit simulation step of the IP circuit performance simulation is completed, not only the conventional circuit simulation result but also the voltage drop result is obtained, and the voltage drop analysis can be performed according to the voltage drop result, specifically, if the voltage drop result of the MOS transistor meets the requirement, the voltage drop analysis is completed; if the voltage drop of some MOS tubes is large and does not meet the requirement, the MOS tubes are positioned on the layout, and the layout is modified correspondingly. That is, after the circuit simulation is completed, obtaining a voltage drop result file (step 103) may include: and if MOS tubes with voltage drop which does not meet the requirement exist, positioning the MOS tubes on the layout, and modifying the layout.
In a further embodiment, the positioning the MOS transistors on the layout may include:
and performing LVs (Layout and logic diagram verification) by using a circuit network table and a Layout file (such as gds file) to obtain the coordinates of the MOS tube on the Layout.
Therefore, the MOS tube with large voltage drop can be conveniently found on the layout, the layout can be modified, and then the IP circuit performance simulation and the voltage drop analysis of the invention can be executed again based on the modified layout until the voltage drop result of the MOS tube meets the requirement.
In some embodiments of the invention, a step of extracting a circuit netlist with parasitic parameters (XRC) from a layout in the IP circuit performance simulation is not necessarily required until the layout is completely finished, and the circuit netlist can be extracted at the initial stage of layout design to perform voltage drop analysis. For example, for some large MOS transistors, under the condition that it is uncertain how its layout should be drawn to better the voltage drop, the layout may be tried first, then parasitic parameters are extracted, the voltage drop analysis is performed by the method in the above technical scheme, and then the layout design is adjusted according to the voltage drop result.
As mentioned above, the EDA tool (such as totem) for voltage drop analysis in the prior art is not compatible with the circuit simulation tool, and therefore, only the circuit simulation and the voltage drop can be separately performed, and how much influence of the voltage drop on various performances of the circuit cannot be directly obtained, which brings inconvenience in the circuit design process. In addition, due to the complexity of tool setup, voltage drop analysis is usually performed after the layout of the IP circuit is completed. And after the layout is finished, voltage drop analysis is carried out, and the layout needs to be modified in case the voltage drop does not meet the requirement, so that the change of the layout is large, and the iteration time cost of the design is increased.
The voltage drop analysis method compatible with the IP circuit performance simulation of the embodiment of the invention combines the performance simulation and the voltage drop analysis of the circuit together without being separated, so that the voltage drop result can be obtained while the circuit performance simulation is carried out, and the influence of the voltage drop on the circuit performance is obtained, thereby guiding the optimization of the circuit design and reducing the influence of the voltage drop on the circuit performance. In addition, the voltage drop analysis method is compatible with circuit simulation in arrangement, voltage drop does not need to be carried out after layout is completed, voltage drop analysis can be carried out at the initial stage of layout design, and particularly for the layout design of a brand-new process, several schemes can be tried on the layout of a key place firstly, so that the scheme with the optimal voltage drop is selected. For example, as shown in fig. 2, an IP circuit is composed of modules A, B and C, where the module a is a key module affecting the whole circuit PPA, so that several layout schemes of the module a may be designed, parasitic parameter netlists of the module a are extracted respectively, then the module a is analyzed for PPA, and a voltage drop result is obtained at the same time, and a scheme in which the influence of the voltage drop on the PPA is optimal is selected from the several schemes (that is, the technical scheme of the embodiment of the present invention may be used for the whole IP circuit, or for a certain module in the IP circuit). Therefore, layout is optimized, time cost for revising the layout after the layout is completely finished is reduced, and the whole design process of the IP circuit is accelerated.
On the other hand, an embodiment of the present invention provides a voltage drop analysis apparatus compatible with IP circuit performance simulation, where the IP circuit performance simulation includes setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file, and circuit simulation, and as shown in fig. 3, the voltage drop analysis apparatus includes:
the searching module 11 is used for searching a MOS transistor of which a source end or a drain end is connected with a power line or a ground line from the circuit netlist;
a modification module 12, configured to modify the measurement file to increase measurement of the source terminal or drain terminal voltage of the found MOS transistor;
and the obtaining module 13 is configured to obtain a voltage drop result file after the circuit simulation is completed.
The device of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, the implementation principle and technical effect of which are similar, and the device can obtain a voltage drop result and how much influence the voltage drop has on the circuit performance while simulating the circuit performance, thereby guiding the circuit design optimization, reducing the influence of the voltage drop on the circuit performance, and simplifying the circuit design flow.
The voltage drop can be analyzed while each circuit simulation iteration is performed. In the initial stage of layout design, voltage drop analysis can be carried out, and layout design is adjusted according to a voltage drop result, so that time cost caused by modifying a layout due to the fact that the voltage drop does not meet requirements until the layout is finished is avoided.
Preferably, the modification module 12 is further configured to increase measurement of a maximum voltage of the source end or the drain end in the simulation time if the found source end or the drain end of the MOS transistor is connected to the ground line; and if the source end or the drain end of the searched MOS tube is connected with a power line, increasing the measurement of the minimum voltage of the source end or the drain end in the simulation time.
Preferably, the obtaining module 13 is further configured to, if there are MOS transistors whose voltage drop does not meet the requirement, position the MOS transistors on the layout, and modify the layout.
Preferably, the obtaining module 13 is further configured to perform layout and logic diagram verification by using a circuit netlist and a layout file to obtain coordinates of the MOS transistor on the layout.
Furthermore, the performance simulation of the IP circuit comprises time sequence analysis, power consumption analysis or signal integrity analysis and the like.
An embodiment of the present invention further provides an electronic device, fig. 4 is a schematic structural diagram of an embodiment of the electronic device of the present invention, and a flow of the embodiment shown in fig. 1 of the present invention may be implemented, as shown in fig. 4, where the electronic device may include: the device comprises a shell 41, a processor 42, a memory 43, a circuit board 44 and a power circuit 45, wherein the circuit board 44 is arranged inside a space enclosed by the shell 41, and the processor 42 and the memory 43 are arranged on the circuit board 44; a power supply circuit 45 for supplying power to each circuit or device of the electronic apparatus; the memory 43 is used for storing executable program code; the processor 42 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 43, for performing the method described in any of the method embodiments described above.
The specific execution process of the above steps by the processor 42 and the steps further executed by the processor 42 by running the executable program code may refer to the description of the embodiment shown in fig. 1 of the present invention, and are not described herein again.
The electronic device exists in a variety of forms, including but not limited to:
(1) a mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices can display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(5) And other electronic equipment with data interaction function.
The embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the method steps described in any of the above method embodiments.
Embodiments of the invention also provide an application program, which is executed to implement the method provided by any one of the method embodiments of the invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment. For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A voltage drop analysis method compatible with IP circuit performance simulation, the IP circuit performance simulation includes setting simulation excitation, extracting circuit netlist with parasitic parameters from a layout, writing a measurement file and circuit simulation, and the voltage drop analysis method is characterized by comprising the following steps:
searching an MOS tube with a source end or a drain end connected with a power line or a ground line from the circuit netlist;
modifying the measurement file to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube;
and after the circuit simulation is finished, obtaining a voltage drop result file.
2. The method of claim 1, wherein modifying the measurement file to increase the measurement of the source or drain voltage of the located MOS transistor comprises:
if the found source end or drain end of the MOS tube is connected with the ground wire, increasing the measurement of the maximum voltage of the source end or drain end in the simulation time;
and if the source end or the drain end of the searched MOS tube is connected with a power line, increasing the measurement of the minimum voltage of the source end or the drain end in the simulation time.
3. The voltage drop analysis method according to claim 1, wherein obtaining a voltage drop result file after the circuit simulation is completed comprises:
and if MOS tubes with voltage drop which does not meet the requirement exist, positioning the MOS tubes on the layout, and modifying the layout.
4. The voltage drop analysis method according to claim 3, wherein said positioning the MOS transistors on the layout comprises:
and verifying the layout and the logic diagram by using the circuit netlist and the layout file to obtain the coordinates of the MOS tube on the layout.
5. The voltage drop analysis method of any one of claims 1-4, wherein the IP circuit performance simulation is a timing analysis, a power consumption analysis, or a signal integrity analysis.
6. A voltage drop analysis device compatible with IP circuit performance simulation, the IP circuit performance simulation comprises setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file and circuit simulation, and the voltage drop analysis device is characterized by comprising:
the searching module is used for searching an MOS (metal oxide semiconductor) tube with a source end or a drain end connected with a power supply line or a ground line from the circuit netlist;
the modification module is used for modifying the measurement file so as to increase the measurement of the voltage of the source end or the drain end of the searched MOS tube;
and the acquisition module is used for acquiring a voltage drop result file after the circuit simulation is finished.
7. The apparatus according to claim 6, wherein the modifying module is further configured to increase the measurement of the maximum voltage of the source terminal or the drain terminal within the simulation time if the found source terminal or the drain terminal of the MOS transistor is connected to the ground line; and if the source end or the drain end of the searched MOS tube is connected with a power line, increasing the measurement of the minimum voltage of the source end or the drain end in the simulation time.
8. The voltage drop analysis device according to claim 6, wherein the obtaining module is further configured to, if there are MOS transistors whose voltage drops do not meet the requirement, position the MOS transistors on the layout, and modify the layout.
9. The voltage drop analysis device according to claim 8, wherein the obtaining module is further configured to perform layout and logic diagram verification using a circuit netlist and a layout file to obtain coordinates of the MOS transistor on the layout.
10. A voltage drop analysis device according to any one of claims 6-9, wherein the IP circuit performance simulation is a timing analysis, a power consumption analysis or a signal integrity analysis.
11. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the method of any of the preceding claims 1-5.
12. A computer readable storage medium, characterized in that the computer readable storage medium stores one or more programs which are executable by one or more processors to implement the method of any of the preceding claims 1-5.
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|---|---|---|---|---|
| CN113657071A (en) * | 2021-08-31 | 2021-11-16 | 杭州广立微电子股份有限公司 | Method for automatically correcting leakage path of MOS device |
| CN113657071B (en) * | 2021-08-31 | 2023-10-13 | 杭州广立微电子股份有限公司 | Method for automatically correcting leakage path of MOS device |
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| CN112417796B (en) | 2023-03-21 |
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