CN112416250A

CN112416250A - NVMe (network video Me) -based command processing method for solid state disk and related equipment

Info

Publication number: CN112416250A
Application number: CN202011318258.8A
Authority: CN
Inventors: 黎杨; 赵朔天; 于大治; 段廷勇
Original assignee: Shenzhen Electric Appliance Co ltd
Current assignee: Shenzhen Electric Appliance Co ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2021-02-26

Abstract

The application provides a command processing method of a solid state disk based on NVMe and related equipment. Wherein, the method comprises the following steps: updating the command queue entry and the command queue write pointer; reading a command from a Static Random Access Memory (SRAM) to obtain a command table entry, the command table entry comprising a command buffer address; according to the command table entry, obtaining a command from the SRAM and storing the command into a Command Static Random Access Memory (CSRAM) arbiter; and processing the command and updating a command completion queue in the SRAM. The method can improve the performance and efficiency of the SSD master control chip and can realize efficient processing of the command by using the NVMe protocol.

Description

NVMe (network video Me) -based command processing method for solid state disk and related equipment

Technical Field

The invention relates to the technical field of computers, in particular to a command processing method of a solid state disk based on NVMe and related equipment.

Background

A Solid State Disk (SSD) is a hard disk made of an array of solid state electronic memory chips, and the interface specification of the SSD may be a Serial Advanced Technology Attachment (SATA) interface or a peripheral component interconnect express (PCIe) interface.

At present, the design of a storage chip of an SSD adopting a SATA interface or a PCIe interface is based on an Advanced Host Controller Interface (AHCI) protocol, and some storage chips are even implemented by a Field Programmable Gate Array (FPGA), which results in poor performance and low efficiency of the SSD.

Therefore, how to improve the performance and efficiency of the main control chip of the SSD is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the invention discloses a method, a system and related equipment for realizing command processing of a solid state disk based on NVMe, which can improve the performance and efficiency of an SSD master control chip and can realize efficient command processing by utilizing an NVMe protocol.

In a first aspect, the present application provides a method for implementing command processing of a NVMe-based solid state disk, including: updating the command queue entry and the command queue write pointer; reading a command table entry from a Static Random Access Memory (SRAM), the command table entry comprising a command buffer address; according to the command table entry, obtaining a command from the SRAM and storing the command into a Command Static Random Access Memory (CSRAM) arbiter; and processing the command and updating a command completion queue in the SRAM.

In the scheme provided by the application, the NVMe command is firstly read from the SRAM to the CSRAM, then the CSRAM arbiter arbitrates the access of the relevant CSRAM, the NVMe command is finally processed, and then the command completion queue in the SRAM is updated, so that the efficient processing of the NVMe command can be improved, and the performance and the efficiency of the SSD main control chip are improved.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system searches for a slot from the CSRAM, and stores the command in the slot; the command tag list and the write command link list are updated.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system updates the command queue read pointer after obtaining the command from the SRAM and storing the command in the command static random access memory CSRAM.

With reference to the first aspect, in a possible implementation manner of the first aspect, if the command is a write command and the write command link list is not empty, the CSRAM is read to obtain a new write command; the last data unit DU transfer is determined and the slot is released.

With reference to the first aspect, in a possible implementation manner of the first aspect, if the command is a read command, the slot is released after the last DU is sent to the host.

With reference to the first aspect, in a possible implementation manner of the first aspect, the NVMe command processing system receives a command tag, where the command tag is used to suspend a command corresponding to the command tag; and setting the corresponding flag bit in the completion queue entry to 1 according to the command tag so as to terminate the command.

In a second aspect, the present application provides an NVMe command processing system, comprising: an update unit for updating the command queue entry and the command queue write pointer; a read unit for reading a command table entry from a static random access memory, SRAM, the command table entry comprising a command buffer address; and the processing unit is used for acquiring a command from the SRAM according to the command table entry, storing the command into a Command Static Random Access Memory (CSRAM), processing the command and updating a command completion queue in the SRAM.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: searching a slot from the CSRAM, and saving the command to the slot; the command tag list and the write command link list are updated.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is further configured to update a command queue read pointer.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: if the command is a writing command and the write command link list is not empty, reading the CSRAM to acquire a new write command; the last data unit DU transfer is determined and the slot is released.

With reference to the second aspect, in a possible implementation manner of the second aspect, the processing unit is specifically configured to: and if the command is a read command, releasing the slot after sending the last DU to the host.

With reference to the second aspect, in a possible implementation manner of the second aspect, the system further includes a receiving unit, where the receiving unit is configured to receive a command tag, and the command tag is configured to suspend a command corresponding to the command tag; the processing unit is further configured to set a corresponding flag bit in the completion queue entry to 1 according to the command tag to terminate the command.

In a third aspect, the present application provides a computing device, where the computing device includes a processor and a memory, where the processor and the memory are connected through an internal bus, and the memory stores instructions, and the processor calls the instructions in the memory to execute the method for data access provided by the first aspect and any implementation manner in combination with the first aspect.

In a fourth aspect, the present application provides a computer storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program can implement the first aspect and the flow of the data access method provided in connection with any one implementation manner of the first aspect.

In a fifth aspect, the present application provides a computer program product, which comprises instructions that, when executed by a computer, enable the computer to perform the first aspect and the flow of the data access method provided in connection with any one of the implementations of the first aspect.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of an NVMe multi-queue provided in an embodiment of the present application;

FIG. 2 is a diagram of a system architecture provided by an embodiment of the present application;

fig. 3 is a schematic flowchart of a command processing method for an NVMe-based solid state disk according to an embodiment of the present application;

FIG. 4 is a diagram illustrating a command table entry format according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a location of a command in an SRAM according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a command tag table provided in an embodiment of the present application;

FIG. 7 is a diagram illustrating a completion queue entry format according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an NVMe command processing system according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are described below clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

First, a part of words and related technologies referred to in the present application will be explained with reference to the accompanying drawings so as to be easily understood by those skilled in the art.

Non-Volatile memory system (NVMe) is an extensible host controller interface designed specifically for enterprise-level and client systems that employs PCIe solid state disks, including optimized register interfaces and command sets. Fundamentally, NVMe is an optimized queue interface, and the host submits commands to the queue, and the queue completes reading or writing data, not in the time sequence of host command submission. And the device has a component specially managing the queue to complete the operations of creating, deleting, command suspension, safety and the like of the queue. The NVMe protocol supports a plurality of parallel command queues, the maximum number of the command queues is 64k, each queue has 64k commands, and queue information needs to be stored for each command queue, so that a space needs to be opened up for each queue when the NVMe protocol is realized. As shown in fig. 1, which is a schematic diagram of NVMe multi-queue, the interaction between the host and the NVMe device (which may also be referred to as a controller) is realized through a queue of a shared memory, the MSI-X interrupt mechanism is supported, two queues exist in the memory of the host, namely a management queue (leftmost queue) and a normal queue (command queue), the management queue is only one, the command queue can be 65535 at most, the number and the mode of the command queues are set by the management queue, each command queue is actually a queue pair and comprises two queues, namely a command submission queue and a command completion queue, the command submission queue is used for sending NVMe commands to the NVMe device by the host, the command completion queue is used for feeding command execution conditions back to the host by the NVMe device, each command queue corresponds to a CPU core, which can perform read-write and refresh operations of commands. In order to adapt to a high-bandwidth and low-latency interface of the PCIe SSD, the interface form is designed to be a mode of multiple paths or multiple IO channels, one path or IO channel consists of one or more command submission queues and one command completion queue corresponding to the command submission queue, and the command submission queue and the command completion queue can be dynamically created in pair. If a plurality of command queues share one IO channel, the priority of the command queues can be determined through an arbitration mechanism, so that the use sequence of the IO channel can be determined.

The Host Memory Buffer (HMB) is a method and system for allowing a host end to provide currently unnecessary memory resources to the SSD for use through an NVMe protocol, and is suitable for a solid state disk without an external cache, and can use a host memory to access a Flash Translation Layer (FTL) mapping table, thereby improving performance at an accelerated speed.

At present, when a storage chip is designed, an SSD based on an SATA interface or a PCIe interface is realized by adopting an AHCI protocol or an FPGA, so that the performance of an SSD master control chip is poor and the efficiency is low. The design scheme and the command processing method of the SSD storage control chip based on the NVMe protocol and the HMB technology are provided, NVMe command processing is independently designed, design is further optimized on the basis of achieving the NVMe protocol, and performance and efficiency of the SSD main control chip are improved.

Based on the above, the application provides a command processing method for the NVMe-based solid state disk, wherein the NVMe command is processed through an independently designed NVMe command processing architecture, so that the performance and efficiency of the SSD master control chip are improved.

The technical scheme of the embodiment of the application can be applied to any system relating to command processing of an SSD control chip, in particular to the scene of an SSD using an NVMe protocol.

Fig. 2 shows a schematic diagram of a system architecture according to an embodiment of the present application. As shown in fig. 2, the system 200 includes: a microprocessor 210, a register 220, a fetch command state machine 230, an advanced extensible interface (AXI) master station 240, a command static random access memory arbiter 250, a command completion state machine 260, and a static random access memory 270. The microprocessor 210 sends the received IO command to the register 220, the register 220 includes a command queue base address and pointer register 221, a command abort register 222, a completion queue base address and pointer register 223, an interrupt status and mask register 224, and a data format register 225, the microprocessor 210 issues a read and write command using the command queue, the command queue is in the sram 270 or BTCM and notifies the fetch command state machine 230, the fetch command state machine 230 reads the command from the sram 270 through the AXI master station 240 according to the address and pointer (e.g., command queue base address and pointer register 221) stored in the register 220, and then requests the command sram arbiter 250 to obtain the command slot, the command sram arbiter 250 includes a command sram 251, a command tag array 252, and a write command linked list 253, the command sram arbiter 250 stores the command in the command sram 251, and updates the command tag table in the command tag array 252 and the write command link table in the write command link table 253, it should be noted that the initial command context is also stored in the command sram 251, and after the command processing is completed, the command completion state machine 260 requests the command sram arbiter 250 to release the command slot, and updates the command completion queue in the sram 270 through the AXI master station 240.

In the embodiment of the application, each part involved in the NVMe command processing system is independently designed, so that the NVMe command processing system can be better implemented and can be deployed in a server or a chip.

Compared with the prior art, the NVMe command processing is performed by the system shown in FIG. 2, so that the command processing efficiency and the SSD master control chip performance can be effectively improved.

With reference to the schematic diagram of the system architecture shown in fig. 2, a command processing method for the NVMe-based solid-state disk provided in the embodiment of the present application will be described below. As shown in fig. 3, the method flow includes:

s301: the command queue entry and the command queue write pointer are updated.

In particular, the firmware uses the command queue to issue read or write commands to the command processing system, for each command the firmware needs to write a new command queue entry, and then the firmware updates the command queue write pointer to push the command into the hardware. Each 32-bit command queue entry points to a 64-byte NVMe command buffer, the base address of the command queue being controlled by the lower 21 bits (e.g., RC0033018h [20:0]), the size of the command queue being controlled by the upper 8 bits (e.g., RC0033018h [31:24]), and the position of the command queue and command buffer being controlled by the middle two bits (e.g., RC0033018h [23:22 ]).

It should be noted that for an unmapped read command, where the read data is not from NAND, the buffer manager will provide dummy data for the unmapped read command, and the firmware needs to issue the read command to CMD _ PORC and program a register (e.g., register RC0033048h) to implement unmapped read command control. Illustratively, setting RC0033048h [16] to 1 to enable the unmapped read command data tag, using RC0033048h [9:0] for the special data tag of the unmapped read command (which must match the special data tag in the buffer manager), when RC0033048h [16] is 1 and the incoming data tag matches RC0033048h [9:0], it may be determined that this data tag is for the unmapped read command, and if PI is enabled, the PI result will be ignored and the PI inserted for each sector.

After updating the command queue entry and the command queue write pointer, the system 200 described above may begin processing new commands.

S302: reading a command table entry from a Static Random Access Memory (SRAM), the command table entry comprising a command buffer address.

Specifically, in the case where the command queue is not empty and the command slot is not full, CMD _ FETCH _ SM reads SRAM to obtain a command table entry including SQ _ ID, HW _ AUO _ CMPL, CMD _ TYPE, CMD _ BUF _ ADDR information, so that the command buffer address can be determined.

Illustratively, as shown in fig. 4, the command table entry format is a schematic diagram, the command table entry format has 32 bits, and is divided into 6 parts, each part represents different meanings, for example, the lower 8 bits represent CMD _ TAG for describing the internal command TAG, the upper 16 bits represent CMD _ BUF _ ADDR, and the 16 th bit represents CMD _ TYPE _1 for describing the command TYPE.

S303: and according to the command table entry, acquiring a command from the SRAM and storing the command into a Command Static Random Access Memory (CSRAM) arbiter.

Specifically, after reading the command table entries, CMD _ FETCH _ SM reads SRAM to FETCH the command, then computes and saves the command context to CMD DW1-DW3, then requests the CSRAM FETCH command slot, writes the command to the corresponding CSRAM entry, and then updates the command tag table and write command linked list. When the command slot is full, the new command will stop being read, and the command queue read pointer (e.g., RC003301Ch [15:8]) needs to be updated each time after the read command.

For example, as shown in fig. 5, fig. 5 is a schematic diagram of the location of a command in the SRAM, and the base address and the data read pointer in the command table both point to the scattered 64-byte NVMe commands.

It should be noted that when the fetch command state machine requests to store a new command, it needs to take a command tag as an input, then the CSRAM arbiter allocates a command queue position and saves the command, and then updates a command tag table, where the command tag table is used to save a command slot and a command tag mapping table, as shown in fig. 6.

In addition, the CSRAM arbiter will also handle other CSRAM access related arbitration, such as DATA _ XFER write DMA requests to get new write commands, the CSRAM arbiter returns the new write commands and their location queue numbers, and updates the write command link list; when the DATA _ XFER reads the DMA request to acquire the command information, the command tag is used as input, the CSRAM arbiter finds the queue number, returns the command information and updates the residual DATA length of the command; when the DATA _ XFER reads the _ PRP _ CTRL request to acquire the command information, the command slot is used as input, and the CSRAM arbiter returns the command information; when the DATA _ XFER requests to store error information, the command slot is used as input, and the CSRAM arbiter stores the error information into a corresponding command static random access memory; when DATA _ XFER NCB _ INDI _ CTRL requests to acquire command information, the CSRAM arbiter finds the slot using the command tag as input, and returns the command information; a command ABORT request that takes a command tag as input, the CSRAM arbiter finds a slot, and immediately ABORTs the read command, or that commands WCMD _ ABORT position 1 in SRAM for the write command; the command completes the request, takes the command tag as input, and the CSRAM arbiter releases the command slot and clears the valid bit. It should be understood that for a READ command, the CSRAM arbiter also requests READ _ PRP _ CTRL to clear all READ PRP entries associated with this command.

It is easy to understand that the commands are stored in CSRAM, CRSAM can store 64 commands, each of 64 bytes, and for the case of write command, DATA _ XFER determines the last DU transmission and requests the CMPL FSM to release the command slot; for a read command request, CSRAM returns last _ DU with command information to DATA _ XFER of the last DU, which requests the CMPL FSM to release the command slot after DATA is sent to the host.

S304: and processing the command and updating a command completion queue in the SRAM.

Specifically, after the CSRAM arbiter completes the related processing of the command, the command completion queue in the SRAM is updated by the command completion state machine. The command completion state machine processes the DATA _ XFER completion request and the FW command ABORT request and requests CSRAM to release the command slot or save the WCMD _ ABORT status bit as a write command, updates the command completion queue in SRAM, updates host CQ by NVMe _ CTRL if the hardware auto-completion function is enabled and the command has completed correctly, and prohibits requesting NVMe _ CTRL if the command is aborted.

For example, as shown in fig. 7, fig. 7 is a schematic diagram of a completion queue entry format, where the completion queue entry format has 64 bits, and each bit represents a different field, for example, the FIRST bit represents CMD _ GOOD for describing command completion and no error, the 7 th bit represents PCIe _ READ _ TMOUT for describing PCIe READ timeout, the 17 th to 25 th bits represent CMD _ TAG for describing command TAG, and the 33 th to 64 th bits represent FIRST _ ERR _ LBA for describing FIRST LBA error.

The above describes the extraction process in detail, and the write command flow and the read command flow are described in detail below.

The specific process of writing the command is as follows:

if the write command list is not empty, DATA _ XFER reads CSRAM to get the new write command, if the required PRP/SGL is greater than PRP1/PRP2/SGL1, DATA _ XFER reads the PRP/SGL list from the host, when PRP/SGL is available, DATA _ XFER reads DATA from the host and then writes it to SRAM, the read is split into DUs (e.g., 4KB +8B or 4KB +64B for the 4KB DU case), the first and last DUs may be partial DUs. Since the write commands are executed in sequence, the CSRAM does not need to update the remaining DATA length, after all DATA of the command is written into the SRAM, DATA _ XFER requests CMD _ PROC to update the command completion status, CMD _ PROC releases the command slot and writes the completion queue into the SRAM, if the command enables the hardware auto-completion function, CMD _ PROC sends { SQ _ ID, CID } information to NVMe _ CTRL without error completion of the command, if the command does not enable the hardware auto-completion function, the command is aborted or completed in error, then the ready completion status is later sent and NVMe _ CTRL is notified, and NVMe _ CTRL updates the host CQ.

The specific process of the read command is as follows:

when DATA _ XFER gets an early indication from the NAND control block, CMD _ PROC with CMD _ TAG and DU _ OFFSET is requested, CMD _ PROC returns the command slot, PSDT, DATA Pointer (DPTR), Metadata Pointer (MPTR), SLBA, PRIINFO, and NLB, and then DATA _ XFER reads the host memory to prepare PRP/SGL. After DATA _ XFER gets the DATA TAG from BM, CMD _ PROC with CMD _ TAG and DU _ OFFSET is requested, CMD _ PROC returns command slot, PSDT, DPTR, MPTR, SLBA, PRINFO, NLB, EILBRT, elbam, and ELBAT, CMD _ PROC also reduces the remaining DATA length saved in the command sram, and if this is the last DU, CMD _ PROC sends last _ DU signal with acknowledgement to DATA _ XFER. If DATA _ XFER READ _ PRP _ CTRL cannot find the relevant PRP/SGL of the DATA tag, CMD _ PROC with CMD _ SLOT and DU _ OFFSET will be requested, CMD _ PROC returns command SLOT, PSDT, DPTR, MPTR, SLBA, PRIINFO and NLB, then DATA _ XFER READ _ PRP _ CTRL READs the host memory to get PRP/SGL. And after the DATA _ XFER sends the last DU to the host, requesting CMD _ PROC to update the command completion status, releasing the command slot by the CMD _ PROC, releasing the PRP/SGL cache entry related to the command by the DATA _ XFER READ _ PRP _ CTRL, and writing a completion queue into the SRAM. If the command enables the hardware auto-complete function, CMD _ PROC sends SQ _ ID, CID } information to NVMe _ CTRL without the command completing without error, if the command does not enable the hardware auto-complete function, the command is aborted or completed with error, then NVMe _ CTRL will later prepare for completion status and notify it to send, NVMe _ CTRL updates host CQ.

In addition, there may be cases where the command is aborted during execution, for example, command CMD _ TAG may be written into the command abort register to abort the command, and if the command issue queue is not empty, the aborted command may still be in the queue and cannot reach the CSRAM, at which point the abort operation will be retried until the command issue queue is empty. If a read command is to be aborted, it is necessary to ensure that there is no pending data TAG in BM and NVMe _ CTRL associated with this command, if CMD _ TAG is not found, this ABORT operation will be ignored and not written to the completion queue, if CMD _ TAG is found, HW ABORTs the read command immediately and updates the completion queue with CMD _ ABORT position 1. If the write command is to be aborted, if no CMD _ TAG is found, this ABORT operation will be ignored and not written to the completion queue, if CMD _ TAG is found, the write command will not be aborted immediately, WCMD _ ABORT is treated in the command sram with WCMD _ ABORT position 1, DATA _ XFER in the same way as a fatal error, and the command is aborted after finding WCMD _ ABORT position is set to 1.

The method of the embodiments of the present application is described in detail above, and in order to better implement the above-mentioned aspects of the embodiments of the present application, correspondingly, the following also provides related equipment for implementing the above-mentioned aspects in a matching manner.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an NVMe command processing system according to an embodiment of the present application. As shown in fig. 8, the system 800 includes an updating unit 810, a reading unit 820, and a processing unit 830. Wherein the content of the first and second substances,

an update unit 810 for updating the command queue entry and the command queue write pointer;

a reading unit 820, configured to read a command table entry from the static random access memory SRAM, where the command table entry includes a command buffer address;

and the processing unit 830 is configured to obtain a command from the SRAM according to the command table entry, store the command in a command static random access memory CSRAM, process the command, and update a command completion queue in the SRAM.

As an embodiment, the processing unit 830 is specifically configured to: searching a slot from the CSRAM, and saving the command to the slot; the command tag list and the write command link list are updated.

For one embodiment, the processing unit 830 is further configured to update the command queue read pointer.

As an embodiment, the processing unit 830 is specifically configured to: if the command is a writing command and the write command link list is not empty, reading the CSRAM to acquire a new write command; the last data unit DU transfer is determined and the slot is released.

As an embodiment, the processing unit 830 is specifically configured to: and if the command is a read command, releasing the slot after sending the last DU to the host.

As an embodiment, the system further includes a receiving unit 840, where the receiving unit 840 is configured to receive a command tag, and the command tag is configured to abort a command corresponding to the command tag; the processing unit 830 is further configured to set a flag bit in a completion queue entry to 1 according to the command tag to terminate the command.

It should be understood that the structure of the NVMe command processing system is merely an example, and should not be construed as a specific limitation, and the respective units of the system may be added, reduced or combined as needed. In addition, the operations and/or functions of the units in the system are respectively for implementing the corresponding flow of the method described in fig. 3, and are not described herein again for brevity.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 9, the computing device 900 includes: a processor 910, a communication interface 920, and a memory 930, the processor 910, the communication interface 920, and the memory 930 being connected to each other by an internal bus 940.

The computing device 900 may be the NVMe command processing system of fig. 2. The functions performed by the NVMe command processing system of fig. 2 are actually performed by the processor 910 of the computing device.

The processor 910 may be formed by one or more general-purpose processors, such as a Central Processing Unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

The bus 940 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus 940 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 9, but not only one bus or type of bus.

Memory 930 may include volatile memory (volatile memory), such as Random Access Memory (RAM); the memory 730 may also include a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory (flash memory), a Hard Disk Drive (HDD), or a solid-state drive (SSD); the memory 930 may also include combinations of the above. The program codes may be functional units for implementing the NVMe command processing system 800, or method steps for implementing the NVMe command processing system as an execution subject in the method embodiment shown in fig. 3.

The present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, may implement part or all of the steps of any one of the method embodiments described above, and implement the functions of any one of the functional units described in fig. 8 above.

Embodiments of the present application also provide a computer program product, which when run on a computer or a processor, causes the computer or the processor to perform one or more steps of any of the methods described above. The respective constituent elements of the above-mentioned apparatus may be stored in the computer-readable storage medium if they are implemented in the form of software functional units and sold or used as independent products.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

It should also be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A command processing method of a solid state disk based on NVMe is characterized by comprising the following steps:

updating the command queue entry and the command queue write pointer;

reading a command table entry from a Static Random Access Memory (SRAM), the command table entry comprising a command buffer address;

according to the command table entry, obtaining a command from the SRAM and storing the command into a Command Static Random Access Memory (CSRAM) arbiter;

and processing the command and updating a command completion queue in the SRAM.

2. The method of claim 1, wherein fetching and saving commands from the SRAM to a Command Static Random Access Memory (CSRAM) according to the command table entry comprises:

searching a slot from the CSRAM, and saving the command to the slot;

the command tag list and the write command link list are updated.

3. The method of claim 1 or 2, wherein after fetching a command from the SRAM and saving it to a Command Static Random Access Memory (CSRAM), the method further comprises:

the command queue read pointer is updated.

4. The method of any of claims 1-3, wherein processing the command comprises:

if the command is a writing command and the write command link list is not empty, reading the CSRAM to acquire a new write command;

the last data unit DU transfer is determined and the slot is released.

5. The method of any of claims 1-3, wherein processing the command comprises:

and if the command is a read command, releasing the slot after sending the last DU to the host.

6. The method of any one of claims 1-5, further comprising:

receiving a command tag, wherein the command tag is used for suspending a command corresponding to the command tag;

and setting the corresponding flag bit in the completion queue entry to 1 according to the command tag so as to terminate the command.

7. An NVMe command processing system, comprising:

an update unit for updating the command queue entry and the command queue write pointer;

a read unit for reading a command table entry from a static random access memory, SRAM, the command table entry comprising a command buffer address;

and the processing unit is used for acquiring a command from the SRAM according to the command table entry, storing the command into a Command Static Random Access Memory (CSRAM), processing the command and updating a command completion queue in the SRAM.

8. The system of claim 7, wherein the processing unit is specifically configured to:

searching a slot from the CSRAM, and saving the command to the slot;

the command tag list and the write command link list are updated.

9. The system of claim 7 or 8,

the processing unit is further configured to update the command queue read pointer.

10. The system according to any one of claims 7 to 9, wherein the processing unit is specifically configured to:

the last data unit DU transfer is determined and the slot is released.

11. The system according to any one of claims 7 to 9, wherein the processing unit is specifically configured to:

12. The system of any one of claims 7-11, wherein the system further comprises a receiving unit,

the receiving unit is used for receiving a command tag, and the command tag is used for suspending a command corresponding to the command tag;

the processing unit is further configured to set a corresponding flag bit in the completion queue entry to 1 according to the command tag to terminate the command.

13. A computing device, comprising a memory and a processor, wherein execution of computer instructions stored in the memory by the processor causes the computing device to perform the method of any of claims 1-6.

14. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the functions of the method according to any one of claims 1-6.